LibreVNA/FPGA/VNA/VNA.gise

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    <transform xil_pn:end_ts="1591357024" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="-8856759851099153863" xil_pn:start_ts="1591357024">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="NotReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="OutOfDateForPredecessor"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="InputAdded"/>
      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="InputRemoved"/>
      <status xil_pn:value="OutputChanged"/>
      <status xil_pn:value="OutputRemoved"/>
    </transform>
    <transform xil_pn:end_ts="1591357058" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="7381105705363676227" xil_pn:start_ts="1591357058">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="NotReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="OutOfDateForPredecessor"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="InputAdded"/>
      <status xil_pn:value="InputChanged"/>
      <status xil_pn:value="InputRemoved"/>
      <status xil_pn:value="OutputChanged"/>
      <status xil_pn:value="OutputRemoved"/>
    </transform>
    <transform xil_pn:end_ts="1600362265" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600362259">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="NotReadyToRun"/>
      <status xil_pn:value="OutOfDateForInputs"/>
      <status xil_pn:value="OutOfDateForPredecessor"/>
      <status xil_pn:value="OutOfDateForOutputs"/>
      <status xil_pn:value="InputRemoved"/>
      <status xil_pn:value="OutputRemoved"/>
    </transform>
  </transforms>

</generated_project>