Depending on the voltage on AUX1/AUX2 the SPI port controls either the FPGA or one of the MAX2871 PLLs:
\begin{center}
\begin{tabular}{ c|c|c }
AUX1 & AUX2 & Function\\
\hline
low & low & SPI communication with FPGA\\
high & low & Direct feedthrough of SCK, MOSI, MISO and NSS to Source PLL\\
low & high & Direct feedthrough of SCK, MOSI, MISO and NSS to LO PLL\\
high & high & Invalid\\
\end{tabular}
\end{center}
When communicating with a PLL, the MUX output of the MAX2871 is forwarded to MISO and the NSS signal is forwarded to the LE pin. As the LE pin should stay low until after a valid register has been shifted in (see MAX2871 datasheet), set NSS low before switching to PLL communication mode.
\section{SPI Protocol}
Each SPI transfer starts with pulling NSS low and ends with NSS returning to high level. SPI communication is done in words of 16\,bits. The first word after NSS is pulled low is the command word and determines the amount and meaning of the following words.
The word received while transmitting the command word is the interrupt status register:
\item\textbf{SH:} Sweep halted due to halt bit set. Sweep will be resumed once the resume command is issued.
\item\textbf{OR:} Data overrun occured (only cleared by resetting the FPGA)
\item\textbf{ND:} New data available
\item\textbf{SU:} Source unlocked
\item\textbf{LU:} LO unlocked
\end{itemize}
\subsection{Writing a register}
Writing a register requires the transfer of two words: First the control word selecting the destination address and a second word containing the new register value:
Initiate the sweep config transfer by sending the command word:
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{1}{0}
\rwbits{1}{1}{0}
\rwbits{2}{1}{0}
\rwbits{3}{13}{Sweep point}
\end{tikzpicture}
\end{center}
The maximum number of points per sweep is 4501, thus the highest valid value for "Sweep point" is 4500. After the control word, send the six words of the sweep config (see section~\ref{sweepconfig}) while keeping NSS low. The sweep config is transmitted MSB first.
\subsection{Reading a sampling result}
Whenever the ND bit in the interrupt status register is set, new sampling data is available and can be read via SPI. It has to be read before the next sampling data arrives otherwise the old data will be overwritten.
Initiate the reading of sampling data by sending the command word:
Afterwards, read up to 19 words before setting NSS high. These 19 words will contain the sampling result (see section~\ref{result}), transmitted with the least significant word first.
When the halt bit is set in the SweepConfig, the FPGA will configure the Source and LO as requested but will not start the settling timer (and subsequently the sampling process) until this resume command is issued. The halted sweep is indicated by the sweep halted bit in the status register.
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{1}{0}
\rwbits{1}{1}{0}
\rwbits{2}{1}{1}
\robits{3}{13}{reserved}
\end{tikzpicture}
\end{center}
\subsection{Reading ADC limits}
The FPGA keeps track of the highest and lowest sample of each ADC to detect saturation and verify signal levels.
Initiate the reading of ADC limit data by sending the command word:
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{1}{1}
\rwbits{1}{1}{1}
\rwbits{2}{1}{1}
\robits{3}{13}{reserved}
\end{tikzpicture}
\end{center}
Afterwards, read 6 words before setting NSS high. These 6 words will contain the sampling result:
\begin{center}
\begin{tikzpicture}
\bitrect{16}{96-\bit}
\rwbits{0}{16}{Port 1 minimum}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{80-\bit}
\rwbits{0}{16}{Port 1 maximum}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{64-\bit}
\rwbits{0}{16}{Port 2 minimum}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{48-\bit}
\rwbits{0}{16}{Port 2 maximum}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{32-\bit}
\rwbits{0}{16}{Reference minimum}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{16}{Reference maximum}
\end{tikzpicture}
\end{center}
\subsection{Resetting the ADC limit}
Issuing this command result in all minimum values set to 32767 and all maximum values set to -32768.
Initiate the reading of the DFT result (see section~\ref{dft}) by sending the command word:
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{1}{1}
\rwbits{1}{1}{0}
\rwbits{2}{1}{1}
\robits{3}{13}{reserved}
\end{tikzpicture}
\end{center}
Afterwards, read 12 words before setting NSS high. These 12 words will contain the first bin of the DFT, the least significant word is transmitted first:
\begin{center}
\begin{tikzpicture}
\bitrect{16}{192-\bit}
\rwbits{0}{16}{Port 1 I[47:32]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{176-\bit}
\rwbits{0}{16}{Port 1 I[31:16]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{168-\bit}
\rwbits{0}{16}{Port 1 I[15:0]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{144-\bit}
\rwbits{0}{16}{Port 1 Q[47:32]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{128-\bit}
\rwbits{0}{16}{Port 1 Q[31:16]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{112-\bit}
\rwbits{0}{16}{Port 1 Q[15:0]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{96-\bit}
\rwbits{0}{16}{Port 2 I[47:32]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{80-\bit}
\rwbits{0}{16}{Port 2 I[31:16]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{64-\bit}
\rwbits{0}{16}{Port 2 I[15:0]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{48-\bit}
\rwbits{0}{16}{Port 2 Q[47:32]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{32-\bit}
\rwbits{0}{16}{Port 2 Q[31:16]}
\end{tikzpicture}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{16}{Port 2 Q[15:0]}
\end{tikzpicture}
\end{center}
Repeating this procedure will return the next DFT bin. For each bin, the CS pin has to be toggled and the command word needs to be sent again (each DFT bin requires a new SPI transaction). The DFT interrupt is reset once all bins have been read. Alternatively, toggling the DFT off and on (by disabling and enabling its interrupt) will also reset the interrupt flag.
\item\textbf{SPP[12:0]:} The register contains the number of samples per point in increments of 16 samples (e.g. SPP=0b0000001000=0x08 uses 128 samples per point). The value of this register is only used if SweepConfig[92:90] is set to 000. Otherwise it is overwritten for the sweep point with one of seven preselected values.
The minimum value for this register is 112, which results in a samplerate of roughly \SI{914.3}{\kilo\hertz}. If Presc is set to a lower value, the data acquisition from the ADC is not done when the next sample starts and samples will be skipped.
Each point in the sweep is done in stages. Each stage consists of (optionally) routing the source signal to one of the ports and sampling of all ADCs. A "new data" interrupt is triggered after each stage.
\item\textbf{Stages} Number of stages per point - 1. Normally the number of stages is equal to the number of ports but it can also be less (e.g. if only S11 is measured).
Allows overwriting hardware settings, regardless of whether a sweep is active or not.
\label{reg:hw_override}
\begin{center}
\begin{tikzpicture}
\bitrect{16}{16-\bit}
\rwbits{0}{1}{OWE}
\rwbits{1}{7}{Attenuator[6:0]}
\rwbits{8}{2}{SourceFilter}
\rwbits{10}{1}{BS}
\rwbits{11}{1}{P1EN}
\rwbits{12}{1}{P2EN}
\robits{13}{3}{reserved}
\end{tikzpicture}
\end{center}
\begin{itemize}
\item\textbf{OWE:} Overwrite enable. If 1, this register is used to configure the hardware. If 0, all other bits in the register are ignored. Must be set to 0 for valid sweep operation.
\item\textbf{Attenuator[6:0]:} Attenuator setting
\item\textbf{SourceFilter:} Low pass filter selection for source signal
\begin{center}
\begin{tabular}{ c|c }
Setting & Selected Band\\
\hline
00 &\SIrange{0}{900}{\mega\hertz}\\
01 &\SIrange{900}{1800}{\mega\hertz}\\
10 &\SIrange{1800}{3500}{\mega\hertz}\\
11 &\SIrange{3500}{6000}{\mega\hertz}\\
\end{tabular}
\end{center}
\item\textbf{BS: Band select.} Set to 0 for highband, set to 1 for lowband.
\item\textbf{P1EN:} Route signal to port 1. Must not be enabled at the same time as P2EN.
\item\textbf{P2EN:} Route signal to port 2. Must not be enabled at the same time as P1EN.
See datasheet of MAX2871 for bit descriptions. Bits for the fields N, FRAC, M, VCO and DIV\_A are "don't care" as they will be overwritten by the SweepConfig setting.
In addition to the single bin DFT configured through the ADC prescaler and phase increment registers (see \ref{reg:ADC} and \ref{reg:phaseinc}), the FPGA also includes a multiple point DFT. This DFT only operates on the port 1 and port 2 receivers and is intended to speed up spectrum analyzer measurements. If enabled, the DFT runs in parallel to all other calculations.
The SweepConfig contains data for the source and LO1 PLL as well as the attenuator and source filter. Each point in the sweep, needs a valid SweepConfig before the sweep is started.
The FPGA supports synchronization of the sweep across multiple devices. This feature can be enabled by setting the SYNC bit in the sweep setup register (see section~\ref{reg:sweepsetup}). When enabled, the following conditions must be met:
\begin{itemize}
\item All participating devices must be connected in a loop via the trigger input and output pins. The order of the devices is not important.
\item All devices must use the same sweep settings with the exception of the "Port 1 stage" and "Port 2 stage" settings in the sweep setup register.
\item The port stages must be configured in such a way, that for each stage exactly one port is active in one device.
\end{itemize}
The synchronization works by delaying sampling until the stimulus signal is present, even when generated by another device. For each sampling stage, performs the following steps:
