2020-08-30 22:20:00 +08:00
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#include "Flash.hpp"
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2020-09-15 05:13:32 +08:00
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#include "FreeRTOS.h"
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#include "task.h"
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#include <cstring>
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#define LOG_LEVEL LOG_LEVEL_INFO
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#define LOG_MODULE "Flash"
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#include "Log.h"
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2020-08-30 22:20:00 +08:00
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bool Flash::isPresent() {
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CS(false);
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// read JEDEC ID
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uint8_t send[4] = {0x9F};
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uint8_t recv[4];
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HAL_SPI_TransmitReceive(spi, send, recv, 4, 100);
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CS(true);
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if(recv[1] != 0xEF) {
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// wrong manufacturer ID, communication with flash not working
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return false;
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}
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return true;
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}
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void Flash::read(uint32_t address, uint16_t length, void *dest) {
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initiateRead(address);
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// read data
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HAL_SPI_Receive(spi, (uint8_t*) dest, length, 1000);
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CS(true);
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}
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bool Flash::write(uint32_t address, uint16_t length, uint8_t *src) {
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if((address & 0xFF) != 0 || length%256 != 0) {
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// only writes to complete pages allowed
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2020-09-15 05:13:32 +08:00
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LOG_ERR("Invalid write address/size: %lu/%u", address, length);
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2020-08-30 22:20:00 +08:00
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return false;
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}
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address &= 0x00FFFFFF;
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2020-09-15 05:13:32 +08:00
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LOG_DEBUG("Writing %u bytes to address %lu", length, address);
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2020-08-30 22:20:00 +08:00
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while(length > 0) {
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EnableWrite();
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CS(false);
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uint8_t cmd[4] = {
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0x02,
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2020-09-15 05:13:32 +08:00
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(uint8_t) (address >> 16) & 0xFF,
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(uint8_t) (address >> 8) & 0xFF,
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2020-08-30 22:20:00 +08:00
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(uint8_t) (address & 0xFF),
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};
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// issue read command
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HAL_SPI_Transmit(spi, cmd, 4, 100);
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// write data
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HAL_SPI_Transmit(spi, src, 256, 1000);
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CS(true);
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2020-09-15 05:13:32 +08:00
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if(!WaitBusy(20)) {
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LOG_ERR("Write timed out");
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2020-08-30 22:20:00 +08:00
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return false;
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}
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2020-09-15 05:13:32 +08:00
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// Verify
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uint8_t buf[256];
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read(address, 256, buf);
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if(memcmp(src, buf, 256)) {
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LOG_ERR("Verification error");
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return false;
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}
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address += 256;
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2020-08-30 22:20:00 +08:00
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length -= 256;
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src += 256;
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}
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return true;
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}
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void Flash::EnableWrite() {
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CS(false);
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// enable write latch
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uint8_t wel = 0x06;
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HAL_SPI_Transmit(spi, &wel, 1, 100);
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CS(true);
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}
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bool Flash::eraseChip() {
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2020-09-15 05:13:32 +08:00
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LOG_INFO("Erasing...");
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2020-08-30 22:20:00 +08:00
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EnableWrite();
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CS(false);
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// enable write latch
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uint8_t chip_erase = 0x60;
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HAL_SPI_Transmit(spi, &chip_erase, 1, 100);
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CS(true);
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return WaitBusy(25000);
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}
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void Flash::initiateRead(uint32_t address) {
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address &= 0x00FFFFFF;
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CS(false);
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uint8_t cmd[4] = {
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0x03,
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2020-09-15 05:13:32 +08:00
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(uint8_t) (address >> 16) & 0xFF,
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(uint8_t) (address >> 8) & 0xFF,
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2020-08-30 22:20:00 +08:00
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(uint8_t) (address & 0xFF),
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};
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// issue read command
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HAL_SPI_Transmit(spi, cmd, 4, 100);
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}
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bool Flash::WaitBusy(uint32_t timeout) {
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uint32_t starttime = HAL_GetTick();
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CS(false);
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uint8_t readStatus1 = 0x05;
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HAL_SPI_Transmit(spi, &readStatus1, 1, 100);
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2020-09-15 05:13:32 +08:00
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do {
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vTaskDelay(1);
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2020-08-30 22:20:00 +08:00
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uint8_t status1;
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HAL_SPI_Receive(spi, &status1, 1, 100);
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2020-09-15 05:13:32 +08:00
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if (!(status1 & 0x01)) {
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2020-08-30 22:20:00 +08:00
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CS(true);
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return true;
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}
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2020-09-15 05:13:32 +08:00
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} while (HAL_GetTick() - starttime < timeout);
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2020-08-30 22:20:00 +08:00
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// timed out
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CS(true);
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2020-09-15 05:13:32 +08:00
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LOG_ERR("Timeout occured");
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2020-08-30 22:20:00 +08:00
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return false;
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}
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