Improve behaviour on full USB buffer
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4a374e022d
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@ -284,3 +284,8 @@ void USB_LP_IRQHandler(void)
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uint16_t usb_available_buffer() {
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uint16_t usb_available_buffer() {
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return sizeof(usb_transmit_fifo) - usb_transmit_fifo_level;
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return sizeof(usb_transmit_fifo) - usb_transmit_fifo_level;
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}
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}
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void usb_clear_buffer() {
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usb_transmit_fifo_level = 0;
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data_transmission_active = 0;
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}
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@ -21,7 +21,7 @@ void usb_init(usbd_recv_callback_t receive_callback);
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bool usb_transmit(const uint8_t *data, uint16_t length);
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bool usb_transmit(const uint8_t *data, uint16_t length);
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uint16_t usb_available_buffer();
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uint16_t usb_available_buffer();
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void usb_log(const char *log, uint16_t length);
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void usb_log(const char *log, uint16_t length);
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void usb_clear_buffer();
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#ifdef __cplusplus
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#ifdef __cplusplus
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}
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}
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@ -231,6 +231,7 @@ void HW::SetIdle() {
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FPGA::Enable(FPGA::Periphery::Port2Mixer, false);
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FPGA::Enable(FPGA::Periphery::Port2Mixer, false);
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FPGA::Enable(FPGA::Periphery::RefMixer, false);
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FPGA::Enable(FPGA::Periphery::RefMixer, false);
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FPGA::Enable(FPGA::Periphery::PortSwitch, false);
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FPGA::Enable(FPGA::Periphery::PortSwitch, false);
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activeMode = Mode::Idle;
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}
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}
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HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool applyCorrections, bool port2) {
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HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool applyCorrections, bool port2) {
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@ -408,7 +408,17 @@ void VNA::SweepHalted() {
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// This function is called from a low level interrupt, need to dispatch to lower priority to allow USB
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// This function is called from a low level interrupt, need to dispatch to lower priority to allow USB
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// handling to continue
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// handling to continue
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STM::DispatchToInterrupt([](){
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STM::DispatchToInterrupt([](){
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while(usb_available_buffer() < reservedUSBbuffer);
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uint32_t start = HAL_GetTick();
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while(usb_available_buffer() < reservedUSBbuffer) {
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if(HAL_GetTick() - start > 100) {
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// still no buffer space after some time, something more serious must have gone wrong
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// -> abort sweep and return to idle
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usb_clear_buffer();
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FPGA::AbortSweep();
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HW::SetIdle();
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return;
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}
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}
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FPGA::ResumeHaltedSweep();
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FPGA::ResumeHaltedSweep();
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});
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});
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}
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}
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