minor spur/phase noise improvements
This commit is contained in:
Jan Käberich
parent
ac1e9fcec6
commit
06a7365a0c
@ -119,6 +119,29 @@ bool Si5351C::SetCLK(uint8_t clknum, uint32_t frequency, PLL source, DriveStreng
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return WriteClkConfig(c, clknum);
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}
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bool Si5351C::SetBypass(uint8_t clknum, PLLSource source, DriveStrength strength) {
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// compile CLKControl register
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uint8_t clkcontrol = 0x00;
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if (source == PLLSource::CLKIN) {
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clkcontrol |= 0x04;
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}
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switch (strength) {
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case DriveStrength::mA2:
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break;
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case DriveStrength::mA4:
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clkcontrol |= 0x01;
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break;
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case DriveStrength::mA6:
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clkcontrol |= 0x02;
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break;
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case DriveStrength::mA8:
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clkcontrol |= 0x03;
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break;
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}
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Reg reg = (Reg) ((int) Reg::CLK0Control + clknum);
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return WriteRegister(reg, clkcontrol);
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}
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bool Si5351C::SetCLKtoXTAL(uint8_t clknum) {
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Reg reg = (Reg) ((int) Reg::CLK0Control + clknum);
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LOG_INFO("Connecting CLK%d to XTAL", clknum);
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@ -163,8 +186,15 @@ bool Si5351C::WritePLLConfig(PLLConfig config, PLL pll) {
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PllData[5] = ((config.P3 >> 12) & 0xF0) | ((config.P2 >> 16) & 0x0F);
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PllData[6] = (config.P2 >> 8) & 0xFF;
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PllData[7] = config.P2 & 0xFF;
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// Check if integer mode is applicable
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Reg reg = pll == PLL::A ? Reg::CLK6Control : Reg::CLK7Control;
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if (config.P2 == 0 && config.P1 % 128 == 0) {
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SetBits(reg, 0x40);
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} else {
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ClearBits(reg, 0x40);
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}
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bool success = true;
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Reg reg = pll == PLL::A ? Reg::MSNA_CONFIG : Reg::MSNB_CONFIG;
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reg = pll == PLL::A ? Reg::MSNA_CONFIG : Reg::MSNB_CONFIG;
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success &= WriteRegisterRange(reg, PllData, sizeof(PllData));
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reg = pll == PLL::A ? Reg::CLK6Control : Reg::CLK7Control;
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if (config.IntegerMode) {
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@ -229,6 +259,11 @@ bool Si5351C::WriteClkConfig(ClkConfig config, uint8_t clknum) {
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clkcontrol |= 0x03;
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break;
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}
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// Check if integer mode is applicable
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if(config.P2 == 0 && config.P1%128 == 0) {
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// Use integer mode
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clkcontrol |= 0x40;
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}
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Reg reg = (Reg) ((int) Reg::CLK0Control + clknum);
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success &= WriteRegister(reg, clkcontrol);
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if (clknum <= 5) {
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@ -242,6 +277,7 @@ bool Si5351C::WriteClkConfig(ClkConfig config, uint8_t clknum) {
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ClkData[5] = ((config.P3 >> 12) & 0xF0) | ((config.P2 >> 16) & 0x0F);
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ClkData[6] = (config.P2 >> 8) & 0xFF;
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ClkData[7] = config.P2 & 0xFF;
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// Calculate address of register control block
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reg = (Reg) ((int) Reg::MS0_CONFIG + 8 * clknum);
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success &= WriteRegisterRange(reg, ClkData, sizeof(ClkData));
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@ -318,28 +354,6 @@ void Si5351C::FindOptimalDivider(uint32_t f_pll, uint32_t f, uint32_t &P1,
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// always using the highest modulus divider results in less than 1Hz deviation for all frequencies, that is good enough
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uint32_t best_c = (1UL << 20) - 1;
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uint32_t best_b = (uint64_t) f_rem * best_c / f;
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// uint32_t best_deviation = UINT32_MAX;
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// for (uint32_t c = (1UL << 20) - 1; c >= (1UL << 19); c--) {
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// uint32_t guess_b = (uint64_t) f_rem * c / f;
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// for (uint32_t b = guess_b; b <= guess_b + 1; b++) {
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// int32_t f_div = (uint64_t) f * b / c;
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// uint32_t deviation = abs(f_rem - f_div);
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// if (deviation < best_deviation) {
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// best_b = b;
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// best_c = c;
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// best_deviation = deviation;
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// if (deviation <= 3) {
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// break;
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// }
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// }
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// }
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// if (best_deviation <= 3) {
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// break;
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// }
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// }
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// LOG_DEBUG(
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// "Optimal divider for %luHz/%luHz is: a=%lu, b=%lu, c=%lu (%luHz deviation)",
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// f_pll, f, a, best_b, best_c, best_deviation);
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// convert to Si5351C parameters
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uint32_t floor = 128 * best_b / best_c;
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P1 = 128 * a + floor - 512;
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@ -360,4 +374,3 @@ bool Si5351C::ReadRawCLKConfig(uint8_t clknum, uint8_t *config) {
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return ReadRegisterRange(reg, config, 8);
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}
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@ -33,6 +33,7 @@ public:
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bool ConfigureCLKIn(uint32_t clkin_freq);
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bool SetPLL(PLL pll, uint32_t frequency, PLLSource src);
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bool SetCLK(uint8_t clknum, uint32_t frequency, PLL source, DriveStrength strength = DriveStrength::mA2, uint32_t PLLFreqOverride = 0);
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bool SetBypass(uint8_t clknum, PLLSource source, DriveStrength strength = DriveStrength::mA2);
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bool SetCLKtoXTAL(uint8_t clknum);
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bool SetCLKToCLKIN(uint8_t clknum);
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bool Enable(uint8_t clknum);
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@ -42,7 +42,7 @@ bool MAX2871::Init(uint32_t f_ref, bool doubler, uint16_t r, bool div2) {
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// recommended phase setting
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regs[1] |= (1UL << 15);
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SetMode(Mode::LowSpur2);
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SetMode(Mode::LowNoise);
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// for all other CP modes the PLL reports unlock condition (output signal appears to be locked)
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SetCPMode(CPMode::CP20);
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SetCPCurrent(15);
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@ -92,10 +92,10 @@ bool HW::Init() {
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Si5351.Init();
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// Use Si5351 to generate reference frequencies for other PLLs and ADC
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Si5351.SetPLL(Si5351C::PLL::A, 800000000, Si5351C::PLLSource::XTAL);
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Si5351.SetPLL(Si5351C::PLL::A, 832000000, Si5351C::PLLSource::XTAL);
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while(!Si5351.Locked(Si5351C::PLL::A));
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Si5351.SetPLL(Si5351C::PLL::B, 800000000, Si5351C::PLLSource::XTAL);
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Si5351.SetPLL(Si5351C::PLL::B, 832000000, Si5351C::PLLSource::XTAL);
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while(!Si5351.Locked(Si5351C::PLL::B));
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extRefInUse = 0;
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@ -103,8 +103,10 @@ bool HW::Init() {
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Si5351.Disable(SiChannel::ReferenceOut);
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// Both MAX2871 get a 100MHz reference
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// Si5351.SetBypass(SiChannel::Source, Si5351C::PLLSource::XTAL);
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Si5351.SetCLK(SiChannel::Source, HW::PLLRef, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::Source);
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// Si5351.SetBypass(SiChannel::LO1, Si5351C::PLLSource::XTAL);
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Si5351.SetCLK(SiChannel::LO1, HW::PLLRef, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
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Si5351.Enable(SiChannel::LO1);
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// 16MHz FPGA clock
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@ -34,7 +34,7 @@ static constexpr uint32_t IF2 = 250000;
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static constexpr uint32_t LO1_minFreq = 25000000;
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static constexpr uint32_t MaxSamples = 130944;
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static constexpr uint32_t MinSamples = 16;
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static constexpr uint32_t PLLRef = 100000000;
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static constexpr uint32_t PLLRef = 104000000;
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static constexpr uint32_t BandSwitchFrequency = 25000000;
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static constexpr uint8_t ADCprescaler = FPGA::Clockrate / ADCSamplerate;
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