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FPGA project adapted to new pinout

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Jan Käberich 2020-08-30 16:19:18 +02:00
parent 30d4ebe37b
commit 16f050a11e
21 changed files with 4079 additions and 0 deletions
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10
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*
!.gitignore
!*/
!*.vhd
!*.ucf
!*.ipf
*/ipcore_dir
!*.gise
!*.xise

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:59:45 05/05/2020
-- Design Name:
-- Module Name: MAX2871 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MAX2871 is
Generic (CLK_DIV : integer);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
REG4 : in STD_LOGIC_VECTOR (31 downto 0);
REG3 : in STD_LOGIC_VECTOR (31 downto 0);
REG1 : in STD_LOGIC_VECTOR (31 downto 0);
REG0 : in STD_LOGIC_VECTOR (31 downto 0);
RELOAD : in STD_LOGIC;
CLK_OUT : out STD_LOGIC;
MOSI : out STD_LOGIC;
LE : out STD_LOGIC;
DONE : out STD_LOGIC);
end MAX2871;
architecture Behavioral of MAX2871 is
signal clk_cnt : integer range 0 to (CLK_DIV/2)-1;
signal reg_cnt : integer range 0 to 3;
signal bit_cnt : integer range 0 to 32;
signal latched_regs : std_logic_vector(127 downto 0);
signal sclk : std_logic;
signal latch : std_logic;
signal done_int : std_logic;
begin
CLK_OUT <= sclk;
MOSI <= latched_regs(127);
LE <= latch;
DONE <= done_int;
process(CLK, RESET)
begin
if rising_edge(CLK) then
if RESET = '1' then
sclk <= '0';
latch <= '0';
done_int <= '1';
else
if done_int = '1' then
-- can start a new reload process
if RELOAD = '1' then
done_int <= '0';
latched_regs <= REG4 & REG3 & REG1 & REG0;
reg_cnt <= 0;
bit_cnt <= 0;
clk_cnt <= 0;
end if;
else
if clk_cnt < (CLK_DIV/2) - 1 then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= 0;
-- advance SPI state machine
if bit_cnt < 32 then
if sclk = '0' then
sclk <= '1';
else
-- falling edge of clk, shift out new bit
sclk <= '0';
latched_regs <= latched_regs(126 downto 0) & "0";
bit_cnt <= bit_cnt + 1;
end if;
else
-- shifted out one register, strobe latch
if latch = '0' then
latch <= '1';
else
latch <= '0';
-- move on to next register
if reg_cnt < 3 then
reg_cnt <= reg_cnt + 1;
bit_cnt <= 0;
else
-- all done
done_int <= '1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:01:43 05/05/2020
-- Design Name:
-- Module Name: MCP33131 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity MCP33131 is
Generic(CLK_DIV : integer;
CONVCYCLES : integer);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
START : in STD_LOGIC;
READY : out STD_LOGIC;
DATA : out STD_LOGIC_VECTOR (15 downto 0);
MIN : out STD_LOGIC_VECTOR (15 downto 0);
MAX : out STD_LOGIC_VECTOR (15 downto 0);
RESET_MINMAX : in STD_LOGIC;
SDO : in STD_LOGIC;
CONVSTART : out STD_LOGIC;
SCLK : out STD_LOGIC);
end MCP33131;
architecture Behavioral of MCP33131 is
signal conv_cnt : integer range 0 to CONVCYCLES-1;
signal div_cnt : integer range 0 to (CLK_DIV/2)-1;
signal sclk_phase : std_logic;
signal adc_data : std_logic_vector(15 downto 0);
type States is (Idle, Conversion, Transmission);
signal state : States;
signal min_int, max_int, data_int : signed(15 downto 0);
begin
MIN <= std_logic_vector(min_int);
MAX <= std_logic_vector(max_int);
DATA <= std_logic_vector(data_int);
process(CLK, RESET)
begin
if(rising_edge(CLK)) then
if(RESET = '1') then
state <= Idle;
READY <= '0';
CONVSTART <= '0';
sclk_phase <= '0';
CONVSTART <= '0';
conv_cnt <= 0;
div_cnt <= 0;
min_int <= to_signed(32767, 16);
max_int <= to_signed(-32768, 16);
else
if RESET_MINMAX = '1' then
min_int <= to_signed(32767, 16);
max_int <= to_signed(-32768, 16);
else
if data_int < min_int then
min_int <= data_int;
end if;
if data_int > max_int then
max_int <= data_int;
end if;
end if;
case state is
when Idle =>
SCLK <= '0';
READY <= '0';
if START = '1' then
state <= Conversion;
conv_cnt <= 0;
CONVSTART <= '1';
end if;
when Conversion =>
if(conv_cnt < CONVCYCLES-1) then
conv_cnt <= conv_cnt + 1;
else
div_cnt <= 0;
CONVSTART <= '0';
adc_data <= "0000000000000001";
state <= Transmission;
end if;
when Transmission =>
if(div_cnt < (CLK_DIV/2)-1) then
div_cnt <= div_cnt + 1;
else
if(sclk_phase = '0') then
sclk_phase <= '1';
SCLK <= '1';
else
sclk_phase <= '0';
SCLK <= '0';
if(adc_data(15) = '0') then
-- not the last bit yet
adc_data <= adc_data(14 downto 0) & SDO;
else
-- last bit, move to output and indicate ready state
data_int <= signed(adc_data(14 downto 0) & SDO);
READY <= '1';
state <= Idle;
end if;
end if;
div_cnt <= 0;
end if;
end case;
end if;
end if;
end process;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:06:31 05/12/2020
-- Design Name:
-- Module Name: ResetDelay - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ResetDelay is
Generic(CLK_DELAY : integer);
Port ( CLK : in STD_LOGIC;
IN_RESET : in STD_LOGIC;
OUT_RESET : out STD_LOGIC);
end ResetDelay;
architecture Behavioral of ResetDelay is
signal clk_cnt : integer range 0 to CLK_DELAY-1;
begin
OUT_RESET <= '1' when IN_RESET = '1' or clk_cnt < CLK_DELAY-1 else '0';
process(CLK, IN_RESET)
begin
if rising_edge(CLK) then
if IN_RESET = '1' then
clk_cnt <= 0;
else
if clk_cnt < CLK_DELAY-1 then
clk_cnt <= clk_cnt + 1;
end if;
end if;
end if;
end process;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:51:11 05/05/2020
-- Design Name:
-- Module Name: SPICommands - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity SPICommands is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
SCLK : in STD_LOGIC;
MOSI : in STD_LOGIC;
MISO : out STD_LOGIC;
NSS : in STD_LOGIC;
NEW_SAMPLING_DATA : in STD_LOGIC;
SAMPLING_RESULT : in STD_LOGIC_VECTOR (287 downto 0);
ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
SOURCE_UNLOCKED : in STD_LOGIC;
LO_UNLOCKED : in STD_LOGIC;
MAX2871_DEF_4 : out STD_LOGIC_VECTOR (31 downto 0);
MAX2871_DEF_3 : out STD_LOGIC_VECTOR (31 downto 0);
MAX2871_DEF_1 : out STD_LOGIC_VECTOR (31 downto 0);
MAX2871_DEF_0 : out STD_LOGIC_VECTOR (31 downto 0);
SWEEP_DATA : out STD_LOGIC_VECTOR (111 downto 0);
SWEEP_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
SWEEP_WRITE : out STD_LOGIC_VECTOR (0 downto 0);
SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0);
NSAMPLES : out STD_LOGIC_VECTOR (16 downto 0);
SETTLING_TIME : out STD_LOGIC_VECTOR (15 downto 0);
EXCITE_PORT1 : out STD_LOGIC;
EXCITE_PORT2 : out STD_LOGIC;
PORT1_EN : out STD_LOGIC;
PORT2_EN : out STD_LOGIC;
REF_EN : out STD_LOGIC;
AMP_SHDN : out STD_LOGIC;
SOURCE_RF_EN : out STD_LOGIC;
LO_RF_EN : out STD_LOGIC;
SOURCE_CE_EN : out STD_LOGIC;
LO_CE_EN : out STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR(2 downto 0);
SYNC_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
INTERRUPT_ASSERTED : out STD_LOGIC;
RESET_MINMAX : out STD_LOGIC;
SWEEP_HALTED : in STD_LOGIC;
SWEEP_RESUME : out STD_LOGIC;
DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0));
end SPICommands;
architecture Behavioral of SPICommands is
COMPONENT spi_slave
Generic(W : integer);
PORT(
SPI_CLK : in STD_LOGIC;
MISO : out STD_LOGIC;
MOSI : in STD_LOGIC;
CS : in STD_LOGIC;
BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
CLK : in STD_LOGIC;
COMPLETE : out STD_LOGIC
);
END COMPONENT;
-- SPI control signals
signal spi_buf_out : std_logic_vector(15 downto 0);
signal spi_buf_in : std_logic_vector(15 downto 0);
signal spi_complete : std_logic;
signal word_cnt : integer range 0 to 19;
type SPI_states is (Invalid, WriteSweepConfig, ReadResult, WriteRegister, ReadTest);
signal state : SPI_states;
signal selected_register : integer range 0 to 15;
signal sweep_config_write : std_logic;
signal unread_sampling_data : std_logic;
signal data_overrun : std_logic;
-- Configuration registers
signal interrupt_mask : std_logic_vector(15 downto 0);
signal interrupt_status : std_logic_vector(15 downto 0);
signal latched_result : std_logic_vector(271 downto 0);
signal sweepconfig_buffer : std_logic_vector(95 downto 0);
begin
SPI: spi_slave
GENERIC MAP(w => 16)
PORT MAP(
SPI_CLK => SCLK,
MISO => MISO,
MOSI => MOSI,
CS => NSS,
BUF_OUT => spi_buf_out,
BUF_IN => spi_buf_in,
CLK => CLK,
COMPLETE =>spi_complete
);
interrupt_status <= DEBUG_STATUS & SWEEP_HALTED & data_overrun & unread_sampling_data & SOURCE_UNLOCKED & LO_UNLOCKED;
INTERRUPT_ASSERTED <= '1' when (interrupt_status and interrupt_mask) /= "0000000000000000" else
'0';
SWEEP_WRITE(0) <= sweep_config_write;
process(CLK, RESET)
begin
if rising_edge(CLK) then
if RESET = '1' then
sweep_config_write <= '0';
data_overrun <= '0';
SWEEP_POINTS <= (others => '0');
NSAMPLES <= (others => '0');
SETTLING_TIME <= (others => '0');
PORT1_EN <= '0';
PORT2_EN <= '0';
REF_EN <= '0';
AMP_SHDN <= '1';
SOURCE_RF_EN <= '0';
LO_RF_EN <= '0';
SOURCE_CE_EN <= '0';
LO_CE_EN <= '0';
LEDS <= (others => '1');
SYNC_SETTING <= "00";
unread_sampling_data <= '0';
interrupt_mask <= (others => '0');
RESET_MINMAX <= '0';
else
if sweep_config_write = '1' then
sweep_config_write <= '0';
end if;
if NEW_SAMPLING_DATA = '1' then
unread_sampling_data <= '1';
if unread_sampling_data = '1' then
data_overrun <= '1';
end if;
end if;
if NSS = '1' then
word_cnt <= 0;
spi_buf_in <= interrupt_status;
RESET_MINMAX <= '0';
SWEEP_RESUME <= '0';
elsif spi_complete = '1' then
word_cnt <= word_cnt + 1;
if word_cnt = 0 then
-- initial word determines action
case spi_buf_out(15 downto 13) is
when "000" => state <= WriteSweepConfig;
-- also extract the point number
SWEEP_ADDRESS <= spi_buf_out(12 downto 0);
when "001" => state <= Invalid;
SWEEP_RESUME <= '1';
when "010" => state <= ReadTest;
spi_buf_in <= "1111000010100101";
when "011" => state <= Invalid;
RESET_MINMAX <= '1';
when "100" => state <= WriteRegister;
selected_register <= to_integer(unsigned(spi_buf_out(3 downto 0)));
when "110" => state <= ReadResult;
latched_result <= SAMPLING_RESULT(287 downto 16);
spi_buf_in <= SAMPLING_RESULT(15 downto 0);
unread_sampling_data <= '0';
when "111" => state <= ReadResult; -- can use same state as read result, but the latched data will contain the min/max ADC values
latched_result(79 downto 0) <= ADC_MINMAX(95 downto 16);
spi_buf_in <= ADC_MINMAX(15 downto 0);
when others => state <= Invalid;
end case;
else
if state = WriteRegister then
-- write received data into previously selected register
case selected_register is
when 0 => interrupt_mask <= spi_buf_out;
when 1 => SWEEP_POINTS <= spi_buf_out(12 downto 0);
when 2 => NSAMPLES(15 downto 0) <= spi_buf_out;
when 3 => NSAMPLES(16) <= spi_buf_out(0);
PORT1_EN <= spi_buf_out(15);
PORT2_EN <= spi_buf_out(14);
REF_EN <= spi_buf_out(13);
AMP_SHDN <= not spi_buf_out(12);
SOURCE_RF_EN <= spi_buf_out(11);
LO_RF_EN <= spi_buf_out(10);
LEDS <= not spi_buf_out(9 downto 7);
SYNC_SETTING <= spi_buf_out(6 downto 5);
SOURCE_CE_EN <= spi_buf_out(4);
LO_CE_EN <= spi_buf_out(3);
EXCITE_PORT1 <= spi_buf_out(1);
EXCITE_PORT2 <= spi_buf_out(2);
when 4 => SETTLING_TIME <= spi_buf_out;
when 8 => MAX2871_DEF_0(15 downto 0) <= spi_buf_out;
when 9 => MAX2871_DEF_0(31 downto 16) <= spi_buf_out;
when 10 => MAX2871_DEF_1(15 downto 0) <= spi_buf_out;
when 11 => MAX2871_DEF_1(31 downto 16) <= spi_buf_out;
when 12 => MAX2871_DEF_3(15 downto 0) <= spi_buf_out;
when 13 => MAX2871_DEF_3(31 downto 16) <= spi_buf_out;
when 14 => MAX2871_DEF_4(15 downto 0) <= spi_buf_out;
when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
when others =>
end case;
selected_register <= selected_register + 1;
elsif state = WriteSweepConfig then
if word_cnt = 7 then
-- Sweep config data is complete pass on
SWEEP_DATA <= sweepconfig_buffer & spi_buf_out;
sweep_config_write <= '1';
else
-- shift next word into buffer
sweepconfig_buffer <= sweepconfig_buffer(79 downto 0) & spi_buf_out;
end if;
elsif state = ReadResult then
-- pass on next word of latched result
spi_buf_in <= latched_result(15 downto 0);
latched_result <= "0000000000000000" & latched_result(271 downto 16);
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:27:54 05/05/2020
-- Design Name:
-- Module Name: Sampling - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sampling is
Generic(CLK_DIV : integer;
CLK_FREQ : integer;
IF_FREQ : integer;
CLK_CYCLES_PRE_DONE : integer);
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
PORT1 : in STD_LOGIC_VECTOR (15 downto 0);
PORT2 : in STD_LOGIC_VECTOR (15 downto 0);
REF : in STD_LOGIC_VECTOR (15 downto 0);
ADC_START : out STD_LOGIC;
NEW_SAMPLE : in STD_LOGIC;
DONE : out STD_LOGIC;
PRE_DONE : out STD_LOGIC;
START : in STD_LOGIC;
SAMPLES : in STD_LOGIC_VECTOR (16 downto 0);
PORT1_I : out STD_LOGIC_VECTOR (47 downto 0);
PORT1_Q : out STD_LOGIC_VECTOR (47 downto 0);
PORT2_I : out STD_LOGIC_VECTOR (47 downto 0);
PORT2_Q : out STD_LOGIC_VECTOR (47 downto 0);
REF_I : out STD_LOGIC_VECTOR (47 downto 0);
REF_Q : out STD_LOGIC_VECTOR (47 downto 0);
ACTIVE : out STD_LOGIC);
end Sampling;
architecture Behavioral of Sampling is
COMPONENT SinCos
PORT (
clk : IN STD_LOGIC;
phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
COMPONENT SinCosMult
PORT (
clk : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
signal p1_I : signed(47 downto 0);
signal p1_Q : signed(47 downto 0);
signal p2_I : signed(47 downto 0);
signal p2_Q : signed(47 downto 0);
signal r_I : signed(47 downto 0);
signal r_Q : signed(47 downto 0);
signal clk_cnt : integer range 0 to CLK_DIV - 1;
signal sample_cnt : integer range 0 to 131071;
constant phase_inc : integer := IF_FREQ * 4096 * CLK_DIV / CLK_FREQ;
signal phase : std_logic_vector(11 downto 0);
signal sine : std_logic_vector(15 downto 0);
signal cosine : std_logic_vector(15 downto 0);
signal mult1_I : std_logic_vector(31 downto 0);
signal mult1_Q : std_logic_vector(31 downto 0);
signal mult2_I : std_logic_vector(31 downto 0);
signal mult2_Q : std_logic_vector(31 downto 0);
signal multR_I : std_logic_vector(31 downto 0);
signal multR_Q : std_logic_vector(31 downto 0);
type States is (Idle, Sampling, WaitForMult, Accumulating, Ready);
signal state : States;
begin
-- Always fails for simulation, comment out
-- assert (phase_inc * CLK_FREQ / (4096*CLK_DIV) = IF_FREQ)
-- report "Phase increment not exact"
-- severity FAILURE;
LookupTable : SinCos
PORT MAP (
clk => CLK,
phase_in => phase,
cosine => cosine,
sine => sine
);
Port1_I_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => PORT1,
b => cosine,
p => mult1_I
);
Port1_Q_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => PORT1,
b => sine,
p => mult1_Q
);
Port2_I_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => PORT2,
b => cosine,
p => mult2_I
);
Port2_Q_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => PORT2,
b => sine,
p => mult2_Q
);
Ref_I_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => REF,
b => cosine,
p => multR_I
);
Ref_Q_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => REF,
b => sine,
p => multR_Q
);
process(CLK, RESET)
begin
if rising_edge(CLK) then
if RESET = '1' then
state <= Idle;
ADC_START <= '0';
DONE <= '0';
PRE_DONE <= '0';
ACTIVE <= '0';
clk_cnt <= 0;
sample_cnt <= 0;
phase <= (others => '0');
else
-- when not idle, generate pulses for ADCs
if state /= Idle then
if clk_cnt = CLK_DIV - 1 then
ADC_START <= '1';
clk_cnt <= 0;
else
clk_cnt <= clk_cnt + 1;
ADC_START <= '0';
end if;
else
ADC_START <= '0';
end if;
-- handle state transitions
case state is
when Idle =>
sample_cnt <= 0;
DONE <= '0';
PRE_DONE <= '0';
ACTIVE <= '0';
clk_cnt <= 0;
phase <= (others => '0');
p1_I <= (others => '0');
p1_Q <= (others => '0');
p2_I <= (others => '0');
p2_Q <= (others => '0');
r_I <= (others => '0');
r_Q <= (others => '0');
phase <= (others => '0');
if START = '1' then
state <= Sampling;
end if;
when Sampling =>
DONE <= '0';
PRE_DONE <= '0';
ACTIVE <= '1';
if NEW_SAMPLE = '1' then
state <= WaitForMult;
end if;
when WaitForMult =>
DONE <= '0';
PRE_DONE <= '0';
ACTIVE <= '1';
state <= Accumulating;
when Accumulating =>
-- multipliers are finished with the sample
p1_I <= p1_I + signed(mult1_I);
p1_Q <= p1_Q + signed(mult1_Q);
p2_I <= p2_I + signed(mult2_I);
p2_Q <= p2_Q + signed(mult2_Q);
r_I <= r_I + signed(multR_I);
r_Q <= r_Q + signed(multR_Q);
-- advance phase
ACTIVE <= '1';
DONE <= '0';
PRE_DONE <= '0';
phase <= std_logic_vector(unsigned(phase) + phase_inc);
if sample_cnt < unsigned(SAMPLES) then
sample_cnt <= sample_cnt + 1;
state <= Sampling;
else
state <= Ready;
end if;
when Ready =>
ACTIVE <= '1';
DONE <= '1';
PRE_DONE <= '1';
PORT1_I <= std_logic_vector(p1_I);
PORT1_Q <= std_logic_vector(p1_Q);
PORT2_I <= std_logic_vector(p2_I);
PORT2_Q <= std_logic_vector(p2_Q);
REF_I <= std_logic_vector(r_I);
REF_Q <= std_logic_vector(r_Q);
state <= Idle;
end case;
end if;
end if;
end process;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:35:02 05/06/2020
-- Design Name:
-- Module Name: Sweep - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Sweep is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
NPOINTS : in STD_LOGIC_VECTOR (12 downto 0);
CONFIG_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
CONFIG_DATA : in STD_LOGIC_VECTOR (111 downto 0);
SAMPLING_BUSY : in STD_LOGIC;
SAMPLING_DONE : in STD_LOGIC;
START_SAMPLING : out STD_LOGIC;
PORT_SELECT : out STD_LOGIC;
BAND_SELECT : out STD_LOGIC;
-- fixed part of source/LO registers
MAX2871_DEF_4 : in STD_LOGIC_VECTOR (31 downto 0);
MAX2871_DEF_3 : in STD_LOGIC_VECTOR (31 downto 0);
MAX2871_DEF_1 : in STD_LOGIC_VECTOR (31 downto 0);
MAX2871_DEF_0 : in STD_LOGIC_VECTOR (31 downto 0);
-- assembled source/LO registers
SOURCE_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
SOURCE_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
SOURCE_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
SOURCE_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
LO_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
LO_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
LO_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
LO_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
RELOAD_PLL_REGS : out STD_LOGIC;
PLL_RELOAD_DONE : in STD_LOGIC;
PLL_LOCKED : in STD_LOGIC;
SWEEP_HALTED : out STD_LOGIC;
SWEEP_RESUME : in STD_LOGIC;
ATTENUATOR : out STD_LOGIC_VECTOR(6 downto 0);
SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0);
SETTLING_TIME : in STD_LOGIC_VECTOR (15 downto 0);
EXCITE_PORT1 : in STD_LOGIC;
EXCITE_PORT2 : in STD_LOGIC;
-- Debug signals
DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0)
);
end Sweep;
architecture Behavioral of Sweep is
signal point_cnt : unsigned(12 downto 0);
type Point_states is (TriggerSetup, SettingUp, SettlingPort1, ExcitingPort1, SettlingPort2, ExcitingPort2, Done);
signal state : Point_states;
signal settling_cnt : unsigned(15 downto 0);
begin
CONFIG_ADDRESS <= std_logic_vector(point_cnt);
-- assemble registers
-- sweep config content:
-- 15 downto 0: Source N divider
-- 27 downto 16: Source Frac
-- 39 downto 28: Source M
-- 45 downto 40: Source VCO selection
-- 48 downto 46: Source DIVA
-- 55 downto 49: Attenuator selection
-- 71 downto 56: LO N divider
-- 83 downto 72: LO Frac
-- 95 downto 84: LO M
-- 101 downto 96: LO VCO selection
-- 104 downto 102: LO DIVA
-- 106 downto 105: Source filter selection
-- 111 downto 107: reserved
SOURCE_REG_0 <= MAX2871_DEF_0(31) & CONFIG_DATA(15 downto 0) & CONFIG_DATA(27 downto 16) & "000";
SOURCE_REG_1 <= MAX2871_DEF_1(31 downto 15) & CONFIG_DATA(39 downto 28) & "001";
SOURCE_REG_3 <= CONFIG_DATA(45 downto 40) & MAX2871_DEF_3(25 downto 3) & "011";
-- output power A passed on from default registers, output B disabled
SOURCE_REG_4 <= MAX2871_DEF_4(31 downto 23) & CONFIG_DATA(48 downto 46) & MAX2871_DEF_4(19 downto 9) & "000" & MAX2871_DEF_4(5 downto 3) & "100";
LO_REG_0 <= MAX2871_DEF_0(31) & CONFIG_DATA(71 downto 56) & CONFIG_DATA(83 downto 72) & "000";
LO_REG_1 <= MAX2871_DEF_1(31 downto 15) & CONFIG_DATA(95 downto 84) & "001";
LO_REG_3 <= CONFIG_DATA(101 downto 96) & MAX2871_DEF_3(25 downto 3) & "011";
-- both outputs enabled at -1dbm
LO_REG_4 <= MAX2871_DEF_4(31 downto 23) & CONFIG_DATA(104 downto 102) & MAX2871_DEF_4(19 downto 9) & "101101100";
ATTENUATOR <= CONFIG_DATA(55 downto 49);
SOURCE_FILTER <= CONFIG_DATA(106 downto 105);
BAND_SELECT <= CONFIG_DATA(110);
DEBUG_STATUS(10 downto 8) <= "000" when state = TriggerSetup else
"001" when state = SettingUp else
"010" when state = SettlingPort1 else
"011" when state = ExcitingPort1 else
"100" when state = SettlingPort2 else
"101" when state = ExcitingPort2 else
"110" when state = Done else
"111";
DEBUG_STATUS(7) <= PLL_RELOAD_DONE;
DEBUG_STATUS(6) <= PLL_RELOAD_DONE and PLL_LOCKED;
DEBUG_STATUS(5) <= SAMPLING_BUSY;
DEBUG_STATUS(4 downto 0) <= (others => '0');
process(CLK, RESET)
begin
if rising_edge(CLK) then
if RESET = '1' then
point_cnt <= (others => '0');
state <= TriggerSetup;
START_SAMPLING <= '0';
RELOAD_PLL_REGS <= '0';
else
case state is
when TriggerSetup =>
RELOAD_PLL_REGS <= '1';
if PLL_RELOAD_DONE = '0' then
state <= SettingUp;
end if;
when SettingUp =>
-- highest bit in CONFIG_DATA determines whether the sweep should be halted prior to sampling
SWEEP_HALTED <= CONFIG_DATA(111);
RELOAD_PLL_REGS <= '0';
if PLL_RELOAD_DONE = '1' and PLL_LOCKED = '1' then
-- check if halted sweep is resumed
if CONFIG_DATA(111) = '0' or SWEEP_RESUME = '1' then
SWEEP_HALTED <= '0';
if EXCITE_PORT1 = '1' then
state <= SettlingPort1;
elsif EXCITE_PORT2 = '1' then
state <= SettlingPort2;
else
state <= Done;
end if;
settling_cnt <= unsigned(SETTLING_TIME);
end if;
end if;
when SettlingPort1 =>
PORT_SELECT <= '1';
-- wait for settling time to elapse
if settling_cnt > 0 then
settling_cnt <= settling_cnt - 1;
else
START_SAMPLING <= '1';
if SAMPLING_BUSY = '1' then
state <= ExcitingPort1;
end if;
end if;
when ExcitingPort1 =>
-- wait for sampling to finish
START_SAMPLING <= '0';
if SAMPLING_BUSY = '0' then
if EXCITE_PORT2 = '1' then
state <= SettlingPort2;
else
state <= Done;
end if;
settling_cnt <= unsigned(SETTLING_TIME);
end if;
when SettlingPort2 =>
PORT_SELECT <= '0';
-- wait for settling time to elapse
if settling_cnt > 0 then
settling_cnt <= settling_cnt - 1;
else
START_SAMPLING <= '1';
if SAMPLING_BUSY = '1' then
state <= ExcitingPort2;
end if;
end if;
when ExcitingPort2 =>
-- wait for sampling to finish
START_SAMPLING <= '0';
if SAMPLING_BUSY = '0' then
if point_cnt < unsigned(NPOINTS) then
point_cnt <= point_cnt + 1;
state <= TriggerSetup;
PORT_SELECT <= '1';
else
point_cnt <= (others => '0');
state <= Done;
end if;
end if;
when others =>
end case;
end if;
end if;
end process;
end Behavioral;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 23:31:10 05/15/2020
-- Design Name:
-- Module Name: Synchronizer - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Synchronizer is
Generic(stages : integer);
Port ( CLK : in STD_LOGIC;
SYNC_IN : in STD_LOGIC;
SYNC_OUT : out STD_LOGIC);
end Synchronizer;
architecture Behavioral of Synchronizer is
signal sync_line : std_logic_vector(stages downto 0);
begin
SYNC_OUT <= sync_line(stages);
process(CLK)
begin
if rising_edge(CLK) then
sync_line <= sync_line(stages-1 downto 0) & SYNC_IN;
end if;
end process;
end Behavioral;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:46:34 05/07/2020
-- Design Name:
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_MAX2871.vhd
-- Project Name: VNA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MAX2871
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_MAX2871 IS
END Test_MAX2871;
ARCHITECTURE behavior OF Test_MAX2871 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MAX2871
Generic (CLK_DIV : integer);
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
REG4 : IN std_logic_vector(31 downto 0);
REG3 : IN std_logic_vector(31 downto 0);
REG1 : IN std_logic_vector(31 downto 0);
REG0 : IN std_logic_vector(31 downto 0);
RELOAD : IN std_logic;
CLK_OUT : OUT std_logic;
MOSI : OUT std_logic;
LE : OUT std_logic;
DONE : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal REG4 : std_logic_vector(31 downto 0) := (others => '0');
signal REG3 : std_logic_vector(31 downto 0) := (others => '0');
signal REG1 : std_logic_vector(31 downto 0) := (others => '0');
signal REG0 : std_logic_vector(31 downto 0) := (others => '0');
signal RELOAD : std_logic := '0';
--Outputs
signal CLK_OUT : std_logic;
signal MOSI : std_logic;
signal LE : std_logic;
signal DONE : std_logic;
-- Clock period definitions
constant CLK_period : time := 6.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MAX2871
GENERIC MAP(CLK_DIV => 10)
PORT MAP (
CLK => CLK,
RESET => RESET,
REG4 => REG4,
REG3 => REG3,
REG1 => REG1,
REG0 => REG0,
RELOAD => RELOAD,
CLK_OUT => CLK_OUT,
MOSI => MOSI,
LE => LE,
DONE => DONE
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
RESET <= '1';
wait for 100 ns;
RESET <= '0';
wait for CLK_period*10;
-- insert stimulus here
REG4 <= "11111111000000001111111100000000";
REG3 <= "11110000111100001111000011110000";
REG1 <= "11001100110011001100110011001100";
REG0 <= "10101010101010101010101010101010";
RELOAD <= '1';
wait for CLK_period;
RELOAD <= '0';
wait;
end process;
END;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:27:40 05/05/2020
-- Design Name:
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_MCP33131.vhd
-- Project Name: VNA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: MCP33131
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_MCP33131 IS
END Test_MCP33131;
ARCHITECTURE behavior OF Test_MCP33131 IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT MCP33131
Generic(CLK_DIV : integer;
CONVCYCLES : integer);
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
START : IN std_logic;
READY : OUT std_logic;
DATA : OUT std_logic_vector(15 downto 0);
MIN : out STD_LOGIC_VECTOR (15 downto 0);
MAX : out STD_LOGIC_VECTOR (15 downto 0);
RESET_MINMAX : in STD_LOGIC;
SDO : IN std_logic;
CONVSTART : OUT std_logic;
SCLK : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal START : std_logic := '0';
signal SDO : std_logic := '0';
signal RESET_MINMAX : STD_LOGIC := '0';
--Outputs
signal READY : std_logic;
signal DATA : std_logic_vector(15 downto 0);
signal CONVSTART : std_logic;
signal SCLK : std_logic;
-- Clock period definitions
constant CLK_period : time := 9.765 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: MCP33131
GENERIC MAP(CLK_DIV => 2,
CONVCYCLES => 71)
PORT MAP (
CLK => CLK,
RESET => RESET,
START => START,
READY => READY,
DATA => DATA,
RESET_MINMAX => RESET_MINMAX,
SDO => SDO,
CONVSTART => CONVSTART,
SCLK => SCLK
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
RESET <= '1';
wait for 100 ns;
RESET <= '0';
wait for CLK_period*10;
-- insert stimulus here
while True loop
wait for CLK_period*105;
START <= '1';
wait for CLK_period;
START <= '0';
end loop;
wait;
end process;
END;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:58:50 05/08/2020
-- Design Name:
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_PLL.vhd
-- Project Name: VNA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: PLL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_PLL IS
END Test_PLL;
ARCHITECTURE behavior OF Test_PLL IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT PLL
PORT(
CLK_IN1 : IN std_logic;
CLK_OUT1 : OUT std_logic;
RESET : IN std_logic;
LOCKED : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK_IN1 : std_logic := '0';
signal RESET : std_logic := '0';
--Outputs
signal CLK_OUT1 : std_logic;
signal LOCKED : std_logic;
-- Clock period definitions
constant CLK_IN1_period : time := 20 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: PLL PORT MAP (
CLK_IN1 => CLK_IN1,
CLK_OUT1 => CLK_OUT1,
RESET => RESET,
LOCKED => LOCKED
);
-- Clock process definitions
CLK_IN1_process :process
begin
CLK_IN1 <= '0';
wait for CLK_IN1_period/2;
CLK_IN1 <= '1';
wait for CLK_IN1_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
RESET <= '1';
wait for 100 ns;
RESET <= '0';
wait for CLK_IN1_period*10;
-- insert stimulus here
wait;
end process;
END;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:32:41 05/15/2020
-- Design Name:
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SPI.vhd
-- Project Name: VNA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: spi_slave
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_SPI IS
END Test_SPI;
ARCHITECTURE behavior OF Test_SPI IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT spi_slave
GENERIC(W : integer);
PORT(
SPI_CLK : IN std_logic;
MISO : OUT std_logic;
MOSI : IN std_logic;
CS : IN std_logic;
BUF_OUT : OUT std_logic_vector(W-1 downto 0);
BUF_IN : IN std_logic_vector(W-1 downto 0);
CLK : IN std_logic;
COMPLETE : OUT std_logic
);
END COMPONENT;
--Inputs
signal SPI_CLK : std_logic := '0';
signal MOSI : std_logic := '0';
signal CS : std_logic := '0';
signal BUF_IN : std_logic_vector(15 downto 0) := (others => '0');
signal CLK : std_logic := '0';
--Outputs
signal MISO : std_logic;
signal BUF_OUT : std_logic_vector(15 downto 0);
signal COMPLETE : std_logic;
-- Clock period definitions
constant CLK_period : time := 10 ns;
constant SPI_CLK_period : time := 100 ns;
signal data_signal : std_logic_vector(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: spi_slave
GENERIC MAP(W => 16)
PORT MAP (
SPI_CLK => SPI_CLK,
MISO => MISO,
MOSI => MOSI,
CS => CS,
BUF_OUT => BUF_OUT,
BUF_IN => BUF_IN,
CLK => CLK,
COMPLETE => COMPLETE
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure SPI(data : std_logic_vector(15 downto 0)) is
begin
MOSI <= data(15);
data_signal <= data(14 downto 0) & "0";
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SPI_CLK <= '1';
wait for SPI_CLK_period/2;
SPI_CLK <= '0';
end procedure SPI;
begin
-- hold reset state for 100 ns.
CS <= '1';
wait for 100 ns;
wait for CLK_period*10;
BUF_IN <= "1111000010100101";
-- insert stimulus here
wait for CLK_period*10;
CS <= '0';
SPI("0101010101010101");
CS <= '1';
wait for CLK_period*10;
BUF_IN <= "0000111100001111";
wait;
end process;
END;

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FPGA/VNA/Test_SPICommands.vhd Normal file
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:42:26 05/07/2020
-- Design Name:
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SPICommands.vhd
-- Project Name: VNA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SPICommands
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_SPICommands IS
END Test_SPICommands;
ARCHITECTURE behavior OF Test_SPICommands IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SPICommands
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
SCLK : IN std_logic;
MOSI : IN std_logic;
MISO : OUT std_logic;
NSS : IN std_logic;
NEW_SAMPLING_DATA : IN std_logic;
SAMPLING_RESULT : IN std_logic_vector(287 downto 0);
SOURCE_UNLOCKED : IN std_logic;
LO_UNLOCKED : IN std_logic;
MAX2871_DEF_4 : OUT std_logic_vector(31 downto 0);
MAX2871_DEF_3 : OUT std_logic_vector(31 downto 0);
MAX2871_DEF_1 : OUT std_logic_vector(31 downto 0);
MAX2871_DEF_0 : OUT std_logic_vector(31 downto 0);
SWEEP_DATA : OUT std_logic_vector(111 downto 0);
SWEEP_ADDRESS : OUT std_logic_vector(12 downto 0);
SWEEP_WRITE : OUT std_logic_vector(0 downto 0);
SWEEP_POINTS : OUT std_logic_vector(12 downto 0);
NSAMPLES : OUT std_logic_vector(16 downto 0);
SETTLING_TIME : OUT std_logic_vector(15 downto 0);
PORT1_EN : OUT std_logic;
PORT2_EN : OUT std_logic;
REF_EN : OUT std_logic;
AMP_SHDN : OUT std_logic;
SOURCE_RF_EN : OUT std_logic;
LO_RF_EN : OUT std_logic;
LEDS : OUT std_logic_vector(2 downto 0);
INTERRUPT_ASSERTED : OUT std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal SCLK : std_logic := '0';
signal MOSI : std_logic := '0';
signal NSS : std_logic := '0';
signal NEW_SAMPLING_DATA : std_logic := '0';
signal SAMPLING_RESULT : std_logic_vector(287 downto 0) := (others => '0');
signal SOURCE_UNLOCKED : std_logic := '1';
signal LO_UNLOCKED : std_logic := '1';
--Outputs
signal MISO : std_logic;
signal MAX2871_DEF_4 : std_logic_vector(31 downto 0);
signal MAX2871_DEF_3 : std_logic_vector(31 downto 0);
signal MAX2871_DEF_1 : std_logic_vector(31 downto 0);
signal MAX2871_DEF_0 : std_logic_vector(31 downto 0);
signal SWEEP_DATA : std_logic_vector(111 downto 0);
signal SWEEP_ADDRESS : std_logic_vector(12 downto 0);
signal SWEEP_WRITE : std_logic_vector(0 downto 0);
signal SWEEP_POINTS : std_logic_vector(12 downto 0);
signal NSAMPLES : std_logic_vector(16 downto 0);
signal SETTLING_TIME : std_logic_vector(15 downto 0);
signal PORT1_EN : std_logic;
signal PORT2_EN : std_logic;
signal REF_EN : std_logic;
signal AMP_SHDN : std_logic;
signal SOURCE_RF_EN : std_logic;
signal LO_RF_EN : std_logic;
signal LEDS : std_logic_vector(2 downto 0);
signal INTERRUPT_ASSERTED : std_logic;
-- Clock period definitions
constant CLK_period : time := 6.25 ns;
constant SPI_CLK_period : time := 100 ns;
signal data_signal : std_logic_vector(15 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SPICommands PORT MAP (
CLK => CLK,
RESET => RESET,
SCLK => SCLK,
MOSI => MOSI,
MISO => MISO,
NSS => NSS,
NEW_SAMPLING_DATA => NEW_SAMPLING_DATA,
SAMPLING_RESULT => SAMPLING_RESULT,
SOURCE_UNLOCKED => SOURCE_UNLOCKED,
LO_UNLOCKED => LO_UNLOCKED,
MAX2871_DEF_4 => MAX2871_DEF_4,
MAX2871_DEF_3 => MAX2871_DEF_3,
MAX2871_DEF_1 => MAX2871_DEF_1,
MAX2871_DEF_0 => MAX2871_DEF_0,
SWEEP_DATA => SWEEP_DATA,
SWEEP_ADDRESS => SWEEP_ADDRESS,
SWEEP_WRITE => SWEEP_WRITE,
SWEEP_POINTS => SWEEP_POINTS,
NSAMPLES => NSAMPLES,
SETTLING_TIME => SETTLING_TIME,
PORT1_EN => PORT1_EN,
PORT2_EN => PORT2_EN,
REF_EN => REF_EN,
AMP_SHDN => AMP_SHDN,
SOURCE_RF_EN => SOURCE_RF_EN,
LO_RF_EN => LO_RF_EN,
LEDS => LEDS,
INTERRUPT_ASSERTED => INTERRUPT_ASSERTED
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
procedure SPI(data : std_logic_vector(15 downto 0)) is
begin
MOSI <= data(15);
data_signal <= data(14 downto 0) & "0";
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
MOSI <= data_signal(15);
data_signal <= data_signal(14 downto 0) & '0';
wait for SPI_CLK_period/2;
SCLK <= '1';
wait for SPI_CLK_period/2;
SCLK <= '0';
end procedure SPI;
begin
-- hold reset state for 100 ns.
RESET <= '1';
NSS <= '1';
wait for 100 ns;
RESET <= '0';
wait for CLK_period*10;
NSS <= '0';
SPI("1100000000000000");
SPI("0000000000000000");
NSS <= '1';
wait for CLK_period*50;
-- insert stimulus here
-- write number of points
NSS <= '0';
SPI("1000000000000001");
SPI("1111000011110000");
NSS <= '1';
wait for CLK_period*100;
-- Write sweep config
NSS <= '0';
SPI("0000000000001011");
SPI("1111111100000000");
SPI("1111000011110000");
SPI("1100110011001100");
SPI("1010101010101010");
SPI("1101101101101101");
SPI("1110111011101110");
SPI("1111101111101111");
NSS <= '1';
wait for CLK_period*50;
NEW_SAMPLING_DATA <= '1';
wait for CLK_period;
NEW_SAMPLING_DATA <= '0';
wait for CLK_period*20;
NSS <= '0';
SPI("1100000000000000");
NSS <= '1';
wait for CLK_period*50;
NEW_SAMPLING_DATA <= '1';
wait for CLK_period;
NEW_SAMPLING_DATA <= '0';
wait for CLK_period*20;
NSS <= '0';
SPI("1100000000000000");
NSS <= '1';
wait;
end process;
END;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:40:38 05/05/2020
-- Design Name:
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_Sampling.vhd
-- Project Name: VNA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Sampling
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_Sampling IS
END Test_Sampling;
ARCHITECTURE behavior OF Test_Sampling IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Sampling
Generic(CLK_DIV : integer;
CLK_FREQ : integer;
IF_FREQ : integer;
CLK_CYCLES_PRE_DONE : integer);
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
PORT1 : IN std_logic_vector(15 downto 0);
PORT2 : IN std_logic_vector(15 downto 0);
REF : IN std_logic_vector(15 downto 0);
ADC_START : OUT std_logic;
NEW_SAMPLE : IN std_logic;
DONE : OUT std_logic;
PRE_DONE : OUT std_logic;
START : IN std_logic;
SAMPLES : IN std_logic_vector(16 downto 0);
PORT1_I : OUT std_logic_vector(47 downto 0);
PORT1_Q : OUT std_logic_vector(47 downto 0);
PORT2_I : OUT std_logic_vector(47 downto 0);
PORT2_Q : OUT std_logic_vector(47 downto 0);
REF_I : OUT std_logic_vector(47 downto 0);
REF_Q : OUT std_logic_vector(47 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal PORT1 : std_logic_vector(15 downto 0) := (others => '0');
signal PORT2 : std_logic_vector(15 downto 0) := (others => '0');
signal REF : std_logic_vector(15 downto 0) := (others => '0');
signal NEW_SAMPLE : std_logic := '0';
signal START : std_logic := '0';
signal SAMPLES : std_logic_vector(16 downto 0) := (others => '0');
--Outputs
signal ADC_START : std_logic;
signal DONE : std_logic;
signal PRE_DONE : std_logic;
signal PORT1_I : std_logic_vector(47 downto 0);
signal PORT1_Q : std_logic_vector(47 downto 0);
signal PORT2_I : std_logic_vector(47 downto 0);
signal PORT2_Q : std_logic_vector(47 downto 0);
signal REF_I : std_logic_vector(47 downto 0);
signal REF_Q : std_logic_vector(47 downto 0);
-- Clock period definitions
constant CLK_period : time := 6.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Sampling
Generic MAP(CLK_DIV => 165,
CLK_FREQ => 160000000,
IF_FREQ => 250000,
CLK_CYCLES_PRE_DONE => 0)
PORT MAP (
CLK => CLK,
RESET => RESET,
PORT1 => PORT1,
PORT2 => PORT2,
REF => REF,
ADC_START => ADC_START,
NEW_SAMPLE => NEW_SAMPLE,
DONE => DONE,
PRE_DONE => PRE_DONE,
START => START,
SAMPLES => SAMPLES,
PORT1_I => PORT1_I,
PORT1_Q => PORT1_Q,
PORT2_I => PORT2_I,
PORT2_Q => PORT2_Q,
REF_I => REF_I,
REF_Q => REF_Q
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
RESET <= '1';
wait for 100 ns;
RESET <= '0';
wait for CLK_period*10;
-- insert stimulus here
PORT1 <= "0111111111111111";
PORT2 <= "0111111111111111";
REF <= "0111111111111111";
SAMPLES <= "00000000000001000";
START <= '1';
while True loop
wait until ADC_START = '1';
START <= '0';
wait for CLK_period * 150;
NEW_SAMPLE <= '1';
wait for CLK_period;
NEW_SAMPLE <= '0';
end loop;
wait;
end process;
END;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:16:15 05/14/2020
-- Design Name:
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SinCos.vhd
-- Project Name: VNA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SinCos
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_SinCos IS
END Test_SinCos;
ARCHITECTURE behavior OF Test_SinCos IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SinCos
PORT(
clk : IN std_logic;
phase_in : IN std_logic_vector(11 downto 0);
cosine : OUT std_logic_vector(15 downto 0);
sine : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal phase_in : std_logic_vector(11 downto 0) := (others => '0');
--Outputs
signal cosine : std_logic_vector(15 downto 0);
signal sine : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SinCos PORT MAP (
clk => clk,
phase_in => phase_in,
cosine => cosine,
sine => sine
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
phase_in <= "000000000000";
wait for clk_period*10;
phase_in <= "000000000001";
wait for clk_period*10;
phase_in <= "000000000010";
wait for clk_period*10;
phase_in <= "000000000011";
wait for clk_period*10;
phase_in <= "000000000100";
wait;
end process;
END;

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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:55:06 05/10/2020
-- Design Name:
-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_Sync.vhd
-- Project Name: VNA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: SwitchingSync
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_Sync IS
END Test_Sync;
ARCHITECTURE behavior OF Test_Sync IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT SwitchingSync
Generic (CLK_DIV : integer);
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
SETTING : IN std_logic_vector(1 downto 0);
SYNC_OUT : OUT std_logic;
SYNC_PULSE_IN : IN std_logic
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal RESET : std_logic := '0';
signal SETTING : std_logic_vector(1 downto 0) := (others => '0');
signal SYNC_PULSE_IN : std_logic := '0';
--Outputs
signal SYNC_OUT : std_logic;
-- Clock period definitions
constant CLK_period : time := 6.25 ns;
constant SYNC_PULSE_period : time := 1031.25 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: SwitchingSync
GENERIC MAP (CLK_DIV => 160)
PORT MAP (
CLK => CLK,
RESET => RESET,
SETTING => SETTING,
SYNC_OUT => SYNC_OUT,
SYNC_PULSE_IN => SYNC_PULSE_IN
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
SYNC_process :process
begin
SYNC_PULSE_IN <= '1';
wait for CLK_period;
SYNC_PULSE_IN <= '0';
wait for SYNC_PULSE_period - CLK_period;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
RESET <= '1';
wait for 100 ns;
RESET <= '0';
wait for CLK_period*10;
-- insert stimulus here
SETTING <= "00";
wait for CLK_period*1600;
SETTING <= "01";
wait for CLK_period*1600;
SETTING <= "10";
wait for CLK_period*1600;
wait;
end process;
END;

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FPGA/VNA/VNA.gise Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="VNA.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MAX2871.vhi"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MCP33131.vhi"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="ResetDelay.vhi"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="SPICommands.vhi"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Sampling.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Sampling.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Sampling.prj"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Sampling.syr"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Sampling.vhi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Sampling.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Sampling_envsettings.html"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="Sampling_summary.html"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Sampling_xst.xrpt"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Sweep.vhi"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_MCP33131_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_MCP33131_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_top_isim_beh.exe"/>
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_4"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="spi_slave.vhi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_BIN" xil_pn:name="top.bin"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="top.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="top.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="top.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="top.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="top.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="top.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="top.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="top.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="top.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="top.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="top.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="top.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="top.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="top.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="top.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="top_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="top_isim_beh.exe"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="top_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="top_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="top_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="top_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_xst.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1588688858" xil_pn:name="TRAN_copyInitialToAbstractSimulation" xil_pn:start_ts="1588688858">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1590511156" xil_pn:in_ck="766507318003862528" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1590511156">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1590511022" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-1206566934435318832" xil_pn:start_ts="1590511022">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1590511022" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-273551377395144626" xil_pn:start_ts="1590511022">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1589440643" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1589440643">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCosMult.ngc"/>
<outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
</transform>
<transform xil_pn:end_ts="1590511156" xil_pn:in_ck="766507318003862528" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1590511156">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1590511158" xil_pn:in_ck="4178816336447958013" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-3530939538078141760" xil_pn:start_ts="1590511156">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1590511159" xil_pn:in_ck="6047462992229066111" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="6352116336892055917" xil_pn:start_ts="1590511158">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1588686459" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1588686459">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1588801396" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="6623951845608321876" xil_pn:start_ts="1588801396">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1589439388" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1589439388">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCosMult.ngc"/>
<outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
</transform>
<transform xil_pn:end_ts="1588801396" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1588801396">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1588801396" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9042377951913232490" xil_pn:start_ts="1588801396">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1588801396" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1588801396">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1588801396" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1588801396">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598796981" xil_pn:in_ck="-94812602667091528" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1598796963">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="top.lso"/>
<outfile xil_pn:name="top.ngc"/>
<outfile xil_pn:name="top.ngr"/>
<outfile xil_pn:name="top.prj"/>
<outfile xil_pn:name="top.stx"/>
<outfile xil_pn:name="top.syr"/>
<outfile xil_pn:name="top.xst"/>
<outfile xil_pn:name="top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1598796368" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1598796368">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1598796987" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1598796981">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="top.bld"/>
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1598797045" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1598796987">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="top.pcf"/>
<outfile xil_pn:name="top_map.map"/>
<outfile xil_pn:name="top_map.mrp"/>
<outfile xil_pn:name="top_map.ncd"/>
<outfile xil_pn:name="top_map.ngm"/>
<outfile xil_pn:name="top_map.xrpt"/>
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1598797075" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1598797045">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="top.ncd"/>
<outfile xil_pn:name="top.pad"/>
<outfile xil_pn:name="top.par"/>
<outfile xil_pn:name="top.ptwx"/>
<outfile xil_pn:name="top.unroutes"/>
<outfile xil_pn:name="top.xpi"/>
<outfile xil_pn:name="top_pad.csv"/>
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1598797089" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1598797075">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="top.bgn"/>
<outfile xil_pn:name="top.bin"/>
<outfile xil_pn:name="top.bit"/>
<outfile xil_pn:name="top.drc"/>
<outfile xil_pn:name="top.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1591357065" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-2382555676865099342" xil_pn:start_ts="1591357065">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1591357024" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="-8856759851099153863" xil_pn:start_ts="1591357024">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1591357058" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="7381105705363676227" xil_pn:start_ts="1591357058">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1598797075" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1598797068">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="top.twr"/>
<outfile xil_pn:name="top.twx"/>
</transform>
</transforms>
</generated_project>

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FPGA/VNA/VNA.xise Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="ipcore_dir/SweepConfigMem.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="ipcore_dir/SinCosMult.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="Test_Sampling.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="49"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="77"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
</file>
<file xil_pn:name="Test_SPICommands.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="115"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="115"/>
</file>
<file xil_pn:name="Test_PLL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="124"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="124"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="Test_Sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="124"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="124"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="124"/>
</file>
<file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Test_SPI.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="133"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="133"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="133"/>
</file>
<file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="ipcore_dir/SweepConfigMem.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/SinCos.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/SinCosMult.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|top|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="top.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="top" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="top_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="top_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="top_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="top_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="top" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_top" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="top.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="auto_project.ipf" xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MCP33131|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-05-05T15:40:10" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="6048ACB2C5F0FA1D2E943FFD4590C880" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/top" xil_pn:name="top.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

114
FPGA/VNA/spi_slave.vhd Normal file
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@ -0,0 +1,114 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:14:17 03/05/2019
-- Design Name:
-- Module Name: spi_slave - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spi_slave is
generic ( W : integer);
Port ( SPI_CLK : in STD_LOGIC;
MISO : out STD_LOGIC;
MOSI : in STD_LOGIC;
CS : in STD_LOGIC;
BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
CLK : in STD_LOGIC;
COMPLETE : out STD_LOGIC
-- RISING_TOGGLE : inout STD_LOGIC;
-- FALLING_TOGGLE : inout STD_LOGIC
);
end spi_slave;
architecture Behavioral of spi_slave is
signal miso_buffer : STD_LOGIC_VECTOR (W-1 downto 0);
signal mosi_buffer : STD_LOGIC_VECTOR (W-2 downto 0);
signal data_valid : STD_LOGIC_VECTOR(2 downto 0);
signal data_synced : STD_LOGIC_VECTOR(2 downto 0);
signal data : STD_LOGIC_VECTOR(W-1 downto 0);
signal bit_cnt : STD_LOGIC_VECTOR(W-2 downto 0);
begin
process(CLK)
begin
if rising_edge(CLK) then
data_valid(2 downto 1) <= data_valid(1 downto 0);
if data_valid(2) = '1' then
if data_synced(0) = '0' then
BUF_OUT <= data;
COMPLETE <= '1';
data_synced(0) <= '1';
else
COMPLETE <= '0';
end if;
else
COMPLETE <= '0';
data_synced(0) <= '0';
end if;
end if;
end process;
MISO <= miso_buffer(W-1) when CS = '0' else 'Z';
slave_in: process(SPI_CLK)
begin
if rising_edge(SPI_CLK) then
-- FALLING_TOGGLE <= not FALLING_TOGGLE;
data_synced(2 downto 1) <= data_synced(1 downto 0);
if bit_cnt(W-2) = '1' then
-- this was the last bit
data_valid(0) <= '1';
data <= mosi_buffer(W-2 downto 0) & MOSI;
else
if data_valid(0) = '1' and data_synced(2) = '1' then
data_valid(0) <= '0';
end if;
mosi_buffer <= mosi_buffer(W-3 downto 0) & MOSI;
end if;
end if;
end process;
slave_out: process(SPI_CLK, CS, BUF_IN, bit_cnt)
begin
if CS = '1' then
bit_cnt <= (others => '0');
miso_buffer <= BUF_IN;
elsif falling_edge(SPI_CLK) then
if bit_cnt(W-2) = '0' then
bit_cnt <= bit_cnt(W-3 downto 0) & '1';
miso_buffer <= miso_buffer(W-2 downto 0) & '0';
else
bit_cnt <= (others => '0');
miso_buffer <= BUF_IN;
end if;
end if;
end process;
end Behavioral;

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FPGA/VNA/top.ucf Normal file
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@ -0,0 +1,147 @@
CONFIG VCCAUX = 3.3;
NET "CLK" PERIOD = 62.5 ns;
NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[4]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[3]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[2]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[1]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[0]" IOSTANDARD = LVCMOS33;
NET "LEDS[7]" IOSTANDARD = LVCMOS33;
NET "LEDS[6]" IOSTANDARD = LVCMOS33;
NET "LEDS[5]" IOSTANDARD = LVCMOS33;
NET "LEDS[4]" IOSTANDARD = LVCMOS33;
NET "LEDS[3]" IOSTANDARD = LVCMOS33;
NET "LEDS[2]" IOSTANDARD = LVCMOS33;
NET "LEDS[1]" IOSTANDARD = LVCMOS33;
NET "LEDS[0]" IOSTANDARD = LVCMOS33;
NET "AMP_PWDN" IOSTANDARD = LVCMOS33;
NET "CLK" IOSTANDARD = LVCMOS33;
NET "FILT_IN_C2" IOSTANDARD = LVCMOS33;
NET "FILT_IN_C1" IOSTANDARD = LVCMOS33;
NET "FILT_OUT_C2" IOSTANDARD = LVCMOS33;
NET "FILT_OUT_C1" IOSTANDARD = LVCMOS33;
NET "LO1_CE" IOSTANDARD = LVCMOS33;
NET "LO1_LD" IOSTANDARD = LVCMOS33;
NET "LO1_LE" IOSTANDARD = LVCMOS33;
NET "LO1_CLK" IOSTANDARD = LVCMOS33;
NET "LO1_MOSI" IOSTANDARD = LVCMOS33;
NET "LO1_MUX" IOSTANDARD = LVCMOS33;
NET "MCU_AUX1" IOSTANDARD = LVCMOS33;
NET "LO1_RF_EN" IOSTANDARD = LVCMOS33;
NET "SOURCE_RF_EN" IOSTANDARD = LVCMOS33;
NET "SOURCE_MUX" IOSTANDARD = LVCMOS33;
NET "SOURCE_LE" IOSTANDARD = LVCMOS33;
NET "SOURCE_MOSI" IOSTANDARD = LVCMOS33;
NET "SOURCE_LD" IOSTANDARD = LVCMOS33;
NET "SOURCE_CLK" IOSTANDARD = LVCMOS33;
NET "SOURCE_CE" IOSTANDARD = LVCMOS33;
NET "RESET" IOSTANDARD = LVCMOS33;
NET "REF_SDO" IOSTANDARD = LVCMOS33;
NET "REF_SCLK" IOSTANDARD = LVCMOS33;
NET "REF_CONVSTART" IOSTANDARD = LVCMOS33;
NET "PORT2_SDO" IOSTANDARD = LVCMOS33;
NET "PORT2_SCLK" IOSTANDARD = LVCMOS33;
NET "PORT2_CONVSTART" IOSTANDARD = LVCMOS33;
NET "PORT1_SDO" IOSTANDARD = LVCMOS33;
NET "PORT1_SCLK" IOSTANDARD = LVCMOS33;
NET "PORT1_CONVSTART" IOSTANDARD = LVCMOS33;
NET "MCU_SCK" IOSTANDARD = LVCMOS33;
NET "MCU_NSS" IOSTANDARD = LVCMOS33;
NET "MCU_MISO" IOSTANDARD = LVCMOS33;
NET "MCU_MOSI" IOSTANDARD = LVCMOS33;
NET "MCU_INTR" IOSTANDARD = LVCMOS33;
NET "MCU_AUX2" IOSTANDARD = LVCMOS33;
NET "MCU_AUX3" IOSTANDARD = LVCMOS33;
NET "PORT1_SCLK" SLEW = FAST;
NET "PORT2_SCLK" SLEW = FAST;
NET "REF_SCLK" SLEW = FAST;
NET "ATTENUATION[6]" LOC = P9;
NET "ATTENUATION[5]" LOC = P10;
NET "ATTENUATION[4]" LOC = P11;
NET "ATTENUATION[3]" LOC = P12;
NET "ATTENUATION[2]" LOC = P14;
NET "ATTENUATION[1]" LOC = P15;
NET "ATTENUATION[0]" LOC = P16;
NET "LEDS[0]" LOC = P92;
NET "LEDS[1]" LOC = P93;
NET "LEDS[2]" LOC = P88;
NET "LEDS[3]" LOC = P87;
NET "LEDS[4]" LOC = P85;
NET "LEDS[5]" LOC = P84;
NET "LEDS[6]" LOC = P83;
NET "LEDS[7]" LOC = P82;
NET "AMP_PWDN" LOC = P8;
NET "BAND_SELECT_HIGH" LOC = P21;
NET "BAND_SELECT_LOW" LOC = P17;
NET "CLK" LOC = P50;
NET "FILT_IN_C1" LOC = P26;
NET "FILT_IN_C2" LOC = P24;
NET "FILT_OUT_C1" LOC = P22;
NET "FILT_OUT_C2" LOC = P23;
NET "LO1_CE" LOC = P45;
NET "LO1_CLK" LOC = P48;
NET "LO1_LD" LOC = P56;
NET "LO1_LE" LOC = P46;
NET "LO1_MOSI" LOC = P47;
NET "LO1_MUX" LOC = P51;
NET "LO1_RF_EN" LOC = P55;
NET "MCU_AUX1" LOC = P78;
NET "MCU_AUX2" LOC = P75;
NET "MCU_AUX3" LOC = P74;
NET "MCU_INTR" LOC = P59;
NET "MCU_MISO" LOC = P62;
NET "MCU_MOSI" LOC = P61;
NET "MCU_NSS" LOC = P67;
NET "MCU_SCK" LOC = P66;
NET "MCU_SCK" CLOCK_DEDICATED_ROUTE = FALSE;
# PlanAhead Generated physical constraints
NET "PORT1_CONVSTART" LOC = P139;
NET "PORT1_MIX1_EN" LOC = P141;
NET "PORT1_MIX2_EN" LOC = P140;
NET "PORT1_SCLK" LOC = P137;
NET "PORT1_SDO" LOC = P138;
NET "PORT1_SELECT" LOC = P142;
NET "PORT2_CONVSTART" LOC = P44;
NET "PORT2_MIX1_EN" LOC = P58;
NET "PORT2_MIX2_EN" LOC = P57;
NET "PORT2_SCLK" LOC = P41;
NET "PORT2_SDO" LOC = P43;
NET "PORT2_SELECT" LOC = P40;
NET "PORT_SELECT1" LOC = P6;
NET "PORT_SELECT2" LOC = P7;
NET "REF_CONVSTART" LOC = P5;
NET "REF_MIX1_EN" LOC = P144;
NET "REF_MIX2_EN" LOC = P143;
NET "REF_SCLK" LOC = P1;
NET "REF_SDO" LOC = P2;
NET "RESET" LOC = P79;
NET "SOURCE_CE" LOC = P27;
NET "SOURCE_CLK" LOC = P32;
NET "SOURCE_LD" LOC = P35;
NET "SOURCE_LE" LOC = P29;
NET "SOURCE_MOSI" LOC = P30;
NET "SOURCE_MUX" LOC = P33;
NET "SOURCE_RF_EN" LOC = P34;
# PlanAhead Generated IO constraints
NET "BAND_SELECT_HIGH" IOSTANDARD = LVCMOS33;
NET "BAND_SELECT_LOW" IOSTANDARD = LVCMOS33;
NET "PORT1_MIX1_EN" IOSTANDARD = LVCMOS33;
NET "PORT1_MIX2_EN" IOSTANDARD = LVCMOS33;
NET "PORT1_SELECT" IOSTANDARD = LVCMOS33;
NET "PORT2_MIX1_EN" IOSTANDARD = LVCMOS33;
NET "PORT2_MIX2_EN" IOSTANDARD = LVCMOS33;
NET "PORT2_SELECT" IOSTANDARD = LVCMOS33;
NET "PORT_SELECT1" IOSTANDARD = LVCMOS33;
NET "PORT_SELECT2" IOSTANDARD = LVCMOS33;
NET "REF_MIX1_EN" IOSTANDARD = LVCMOS33;
NET "REF_MIX2_EN" IOSTANDARD = LVCMOS33;

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----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:47:31 05/05/2020
-- Design Name:
-- Module Name: top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top is
Port ( CLK : in STD_LOGIC;
RESET : in STD_LOGIC;
MCU_MOSI : in STD_LOGIC;
MCU_NSS : in STD_LOGIC;
MCU_INTR : out STD_LOGIC;
MCU_SCK : in STD_LOGIC;
MCU_MISO : out STD_LOGIC;
MCU_AUX1 : in STD_LOGIC;
MCU_AUX2 : in STD_LOGIC;
MCU_AUX3 : in STD_LOGIC;
PORT2_CONVSTART : out STD_LOGIC;
PORT2_SDO : in STD_LOGIC;
PORT2_SCLK : out STD_LOGIC;
PORT2_MIX2_EN : out STD_LOGIC;
PORT2_MIX1_EN : out STD_LOGIC;
PORT1_CONVSTART : out STD_LOGIC;
PORT1_SDO : in STD_LOGIC;
PORT1_SCLK : out STD_LOGIC;
PORT1_MIX2_EN : out STD_LOGIC;
PORT1_MIX1_EN : out STD_LOGIC;
LO1_MUX : in STD_LOGIC;
LO1_RF_EN : out STD_LOGIC;
LO1_LD : in STD_LOGIC;
LO1_CLK : out STD_LOGIC;
LO1_MOSI : out STD_LOGIC;
LO1_LE : out STD_LOGIC;
LO1_CE : out STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR (7 downto 0);
REF_MIX2_EN : out STD_LOGIC;
REF_MIX1_EN : out STD_LOGIC;
ATTENUATION : out STD_LOGIC_VECTOR (6 downto 0);
AMP_PWDN : out STD_LOGIC;
PORT1_SELECT : out STD_LOGIC; -- Port 1 additional isolation switch enable
PORT2_SELECT : out STD_LOGIC; -- Port 2 additional isolation switch enable
PORT_SELECT1 : out STD_LOGIC; -- Enable source -> port 1 switch
PORT_SELECT2 : out STD_LOGIC; -- Enable source -> port 2 switch
BAND_SELECT_HIGH : out STD_LOGIC;
BAND_SELECT_LOW : out STD_LOGIC;
FILT_OUT_C1 : out STD_LOGIC;
FILT_OUT_C2 : out STD_LOGIC;
FILT_IN_C1 : out STD_LOGIC;
FILT_IN_C2 : out STD_LOGIC;
SOURCE_RF_EN : out STD_LOGIC;
SOURCE_LD : in STD_LOGIC;
SOURCE_MUX : in STD_LOGIC;
SOURCE_CLK : out STD_LOGIC;
SOURCE_MOSI : out STD_LOGIC;
SOURCE_LE : out STD_LOGIC;
SOURCE_CE : out STD_LOGIC;
REF_CONVSTART : out STD_LOGIC;
REF_SDO : in STD_LOGIC;
REF_SCLK : out STD_LOGIC);
end top;
architecture Behavioral of top is
component PLL
port
(-- Clock in ports
CLK_IN1 : in std_logic;
-- Clock out ports
CLK_OUT1 : out std_logic;
-- Status and control signals
RESET : in std_logic;
LOCKED : out std_logic
);
end component;
COMPONENT ResetDelay
GENERIC(CLK_DELAY : integer);
PORT(
CLK : IN std_logic;
IN_RESET : IN std_logic;
OUT_RESET : OUT std_logic
);
END COMPONENT;
COMPONENT Sweep
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
NPOINTS : IN std_logic_vector(12 downto 0);
CONFIG_DATA : IN std_logic_vector(111 downto 0);
SAMPLING_BUSY : in STD_LOGIC;
SAMPLING_DONE : IN std_logic;
MAX2871_DEF_4 : IN std_logic_vector(31 downto 0);
MAX2871_DEF_3 : IN std_logic_vector(31 downto 0);
MAX2871_DEF_1 : IN std_logic_vector(31 downto 0);
MAX2871_DEF_0 : IN std_logic_vector(31 downto 0);
PLL_RELOAD_DONE : IN std_logic;
PLL_LOCKED : IN std_logic;
SETTLING_TIME : IN std_logic_vector(15 downto 0);
CONFIG_ADDRESS : OUT std_logic_vector(12 downto 0);
START_SAMPLING : OUT std_logic;
PORT_SELECT : OUT std_logic;
BAND_SELECT : out STD_LOGIC;
SOURCE_REG_4 : OUT std_logic_vector(31 downto 0);
SOURCE_REG_3 : OUT std_logic_vector(31 downto 0);
SOURCE_REG_1 : OUT std_logic_vector(31 downto 0);
SOURCE_REG_0 : OUT std_logic_vector(31 downto 0);
LO_REG_4 : OUT std_logic_vector(31 downto 0);
LO_REG_3 : OUT std_logic_vector(31 downto 0);
LO_REG_1 : OUT std_logic_vector(31 downto 0);
LO_REG_0 : OUT std_logic_vector(31 downto 0);
RELOAD_PLL_REGS : OUT std_logic;
SWEEP_HALTED : out STD_LOGIC;
SWEEP_RESUME : in STD_LOGIC;
ATTENUATOR : OUT std_logic_vector(6 downto 0);
SOURCE_FILTER : OUT std_logic_vector(1 downto 0);
EXCITE_PORT1 : out STD_LOGIC;
EXCITE_PORT2 : out STD_LOGIC;
DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0)
);
END COMPONENT;
COMPONENT Sampling
Generic(CLK_DIV : integer;
CLK_FREQ : integer;
IF_FREQ : integer;
CLK_CYCLES_PRE_DONE : integer);
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
PORT1 : IN std_logic_vector(15 downto 0);
PORT2 : IN std_logic_vector(15 downto 0);
REF : IN std_logic_vector(15 downto 0);
NEW_SAMPLE : IN std_logic;
START : IN std_logic;
SAMPLES : IN std_logic_vector(16 downto 0);
ADC_START : OUT std_logic;
DONE : OUT std_logic;
PRE_DONE : OUT std_logic;
PORT1_I : OUT std_logic_vector(47 downto 0);
PORT1_Q : OUT std_logic_vector(47 downto 0);
PORT2_I : OUT std_logic_vector(47 downto 0);
PORT2_Q : OUT std_logic_vector(47 downto 0);
REF_I : OUT std_logic_vector(47 downto 0);
REF_Q : OUT std_logic_vector(47 downto 0);
ACTIVE : OUT std_logic
);
END COMPONENT;
COMPONENT MCP33131
Generic(CLK_DIV : integer;
CONVCYCLES : integer);
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
START : IN std_logic;
SDO : IN std_logic;
READY : OUT std_logic;
DATA : OUT std_logic_vector(15 downto 0);
MIN : out STD_LOGIC_VECTOR (15 downto 0);
MAX : out STD_LOGIC_VECTOR (15 downto 0);
RESET_MINMAX : in STD_LOGIC;
CONVSTART : OUT std_logic;
SCLK : OUT std_logic
);
END COMPONENT;
COMPONENT MAX2871
Generic (CLK_DIV : integer);
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
REG4 : IN std_logic_vector(31 downto 0);
REG3 : IN std_logic_vector(31 downto 0);
REG1 : IN std_logic_vector(31 downto 0);
REG0 : IN std_logic_vector(31 downto 0);
RELOAD : IN std_logic;
CLK_OUT : OUT std_logic;
MOSI : OUT std_logic;
LE : OUT std_logic;
DONE : OUT std_logic
);
END COMPONENT;
COMPONENT SPICommands
PORT(
CLK : IN std_logic;
RESET : IN std_logic;
SCLK : IN std_logic;
MOSI : IN std_logic;
NSS : IN std_logic;
NEW_SAMPLING_DATA : IN std_logic;
SAMPLING_RESULT : IN std_logic_vector(287 downto 0);
ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
SOURCE_UNLOCKED : IN std_logic;
LO_UNLOCKED : IN std_logic;
MISO : OUT std_logic;
MAX2871_DEF_4 : OUT std_logic_vector(31 downto 0);
MAX2871_DEF_3 : OUT std_logic_vector(31 downto 0);
MAX2871_DEF_1 : OUT std_logic_vector(31 downto 0);
MAX2871_DEF_0 : OUT std_logic_vector(31 downto 0);
SWEEP_DATA : OUT std_logic_vector(111 downto 0);
SWEEP_ADDRESS : OUT std_logic_vector(12 downto 0);
SWEEP_WRITE : OUT std_logic_vector(0 to 0);
SWEEP_POINTS : OUT std_logic_vector(12 downto 0);
NSAMPLES : OUT std_logic_vector(16 downto 0);
SETTLING_TIME : out STD_LOGIC_VECTOR (15 downto 0);
EXCITE_PORT1 : out STD_LOGIC;
EXCITE_PORT2 : out STD_LOGIC;
PORT1_EN : out STD_LOGIC;
PORT2_EN : out STD_LOGIC;
REF_EN : out STD_LOGIC;
AMP_SHDN : out STD_LOGIC;
SOURCE_RF_EN : out STD_LOGIC;
LO_RF_EN : out STD_LOGIC;
SOURCE_CE_EN : out STD_LOGIC;
LO_CE_EN : out STD_LOGIC;
LEDS : out STD_LOGIC_VECTOR(2 downto 0);
SYNC_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
INTERRUPT_ASSERTED : OUT std_logic;
RESET_MINMAX : out STD_LOGIC;
SWEEP_HALTED : in STD_LOGIC;
SWEEP_RESUME : out STD_LOGIC;
DEBUG_STATUS : in STD_LOGIC_VECTOR (10 downto 0)
);
END COMPONENT;
COMPONENT SweepConfigMem
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(111 DOWNTO 0);
clkb : IN STD_LOGIC;
addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(111 DOWNTO 0)
);
END COMPONENT;
COMPONENT Synchronizer
GENERIC(stages : integer);
PORT(
CLK : IN std_logic;
SYNC_IN : IN std_logic;
SYNC_OUT : OUT std_logic
);
END COMPONENT;
signal clk160 : std_logic;
signal clk_locked : std_logic;
signal inv_clk_locked : std_logic;
signal int_reset : std_logic;
-- PLL signals
signal source_reg_4 : std_logic_vector(31 downto 0);
signal source_reg_3 : std_logic_vector(31 downto 0);
signal source_reg_1 : std_logic_vector(31 downto 0);
signal source_reg_0 : std_logic_vector(31 downto 0);
signal lo_reg_4 : std_logic_vector(31 downto 0);
signal lo_reg_3 : std_logic_vector(31 downto 0);
signal lo_reg_1 : std_logic_vector(31 downto 0);
signal lo_reg_0 : std_logic_vector(31 downto 0);
signal reload_plls : std_logic;
signal source_reloaded : std_logic;
signal lo_reloaded : std_logic;
signal plls_reloaded : std_logic;
signal plls_locked : std_logic;
signal source_unlocked : std_logic;
signal lo_unlocked : std_logic;
-- ADC signals
signal adc_trigger_sample : std_logic;
signal adc_port1_ready : std_logic;
signal adc_port1_data : std_logic_vector(15 downto 0);
signal adc_port2_data : std_logic_vector(15 downto 0);
signal adc_ref_data : std_logic_vector(15 downto 0);
signal adc_minmax : std_logic_vector(95 downto 0);
signal adc_reset_minmax : std_logic;
-- Sampling signals
signal sampling_busy : std_logic;
signal sampling_done : std_logic;
signal sampling_start : std_logic;
signal sampling_samples : std_logic_vector(16 downto 0);
signal sampling_result : std_logic_vector(287 downto 0);
-- Sweep signals
signal sweep_points : std_logic_vector(12 downto 0);
signal sweep_config_data : std_logic_vector(111 downto 0);
signal sweep_config_address : std_logic_vector(12 downto 0);
signal source_filter : std_logic_vector(1 downto 0);
signal sweep_port_select : std_logic;
signal sweep_config_write_address : std_logic_vector(12 downto 0);
signal sweep_config_write_data : std_logic_vector(111 downto 0);
signal sweep_config_write : std_logic_vector(0 downto 0);
signal sweep_reset : std_logic;
signal sweep_halted : std_logic;
signal sweep_resume : std_logic;
signal sweep_excite_port1 : std_logic;
signal sweep_excite_port2 : std_logic;
signal sweep_band : std_logic;
-- Configuration signals
signal settling_time : std_logic_vector(15 downto 0);
signal def_reg_4 : std_logic_vector(31 downto 0);
signal def_reg_3 : std_logic_vector(31 downto 0);
signal def_reg_1 : std_logic_vector(31 downto 0);
signal def_reg_0 : std_logic_vector(31 downto 0);
signal user_leds : std_logic_vector(2 downto 0);
signal port1mix_en : std_logic;
signal port2mix_en : std_logic;
signal refmix_en : std_logic;
-- PLL/SPI internal mux
signal fpga_select : std_logic;
signal fpga_source_SCK : std_logic;
signal fpga_source_MOSI : std_logic;
signal fpga_source_LE : std_logic;
signal fpga_LO1_SCK : std_logic;
signal fpga_LO1_MOSI : std_logic;
signal fpga_LO1_LE : std_logic;
signal fpga_miso : std_logic;
-- synchronized asynchronous inputs
signal aux1_sync : std_logic;
signal aux2_sync : std_logic;
signal aux3_sync : std_logic;
signal lo_ld_sync : std_logic;
signal source_ld_sync : std_logic;
signal debug : std_logic_vector(10 downto 0);
signal intr : std_logic;
begin
-- Reference CLK LED
LEDS(0) <= user_leds(2);
-- Lock status of PLLs
LEDS(1) <= clk_locked;
LEDS(2) <= SOURCE_LD;
LEDS(3) <= LO1_LD;
-- Sweep and active port
PORT_SELECT2 <= sweep_port_select;
PORT2_SELECT <= sweep_port_select;
PORT_SELECT1 <= not sweep_port_select;
PORT1_SELECT <= not sweep_port_select;
BAND_SELECT_HIGH <= not sweep_band;
BAND_SELECT_LOW <= sweep_band;
PORT1_MIX2_EN <= port1mix_en;
PORT1_MIX1_EN <= not port1mix_en;
PORT2_MIX2_EN <= port2mix_en;
PORT2_MIX1_EN <= not port2mix_en;
REF_MIX2_EN <= refmix_en;
REF_MIX1_EN <= not refmix_en;
LEDS(4) <= not (not sweep_reset and sweep_port_select);
LEDS(5) <= not (not sweep_reset and not sweep_port_select);
-- Uncommitted LEDs
LEDS(7 downto 6) <= user_leds(1 downto 0);
--LEDS(7) <= '0';
MCU_INTR <= intr;
--LEDS(6) <= intr;
MainCLK : PLL
port map(
-- Clock in ports
CLK_IN1 => CLK,
-- Clock out ports
CLK_OUT1 => clk160,
-- Status and control signals
RESET => RESET,
LOCKED => clk_locked
);
inv_clk_locked <= not clk_locked and not RESET;
Inst_ResetDelay: ResetDelay
GENERIC MAP(CLK_DELAY => 100)
PORT MAP(
CLK => clk160,
IN_RESET => inv_clk_locked,
OUT_RESET => int_reset
);
Sync_AUX1 : Synchronizer
GENERIC MAP(stages => 2)
PORT MAP(
CLK => clk160,
SYNC_IN => MCU_AUX1,
SYNC_OUT => aux1_sync
);
Sync_AUX2 : Synchronizer
GENERIC MAP(stages => 2)
PORT MAP(
CLK => clk160,
SYNC_IN => MCU_AUX2,
SYNC_OUT => aux2_sync
);
Sync_AUX3 : Synchronizer
GENERIC MAP(stages => 2)
PORT MAP(
CLK => clk160,
SYNC_IN => MCU_AUX3,
SYNC_OUT => aux3_sync
);
Sync_LO_LD : Synchronizer
GENERIC MAP(stages => 2)
PORT MAP(
CLK => clk160,
SYNC_IN => LO1_LD,
SYNC_OUT => lo_ld_sync
);
Sync_SOURCE_LD : Synchronizer
GENERIC MAP(stages => 2)
PORT MAP(
CLK => clk160,
SYNC_IN => SOURCE_LD,
SYNC_OUT => source_ld_sync
);
Source: MAX2871
GENERIC MAP(CLK_DIV => 10)
PORT MAP(
CLK => clk160,
RESET => int_reset,
REG4 => source_reg_4,
REG3 => source_reg_3,
REG1 => source_reg_1,
REG0 => source_reg_0,
RELOAD => reload_plls,
CLK_OUT => fpga_source_SCK,
MOSI => fpga_source_MOSI,
LE => fpga_source_LE,
DONE => source_reloaded
);
LO1: MAX2871
GENERIC MAP(CLK_DIV => 10)
PORT MAP(
CLK => clk160,
RESET => int_reset,
REG4 => lo_reg_4,
REG3 => lo_reg_3,
REG1 => lo_reg_1,
REG0 => lo_reg_0,
RELOAD => reload_plls,
CLK_OUT => fpga_LO1_SCK,
MOSI => fpga_LO1_MOSI,
LE => fpga_LO1_LE,
DONE => lo_reloaded
);
plls_reloaded <= source_reloaded and lo_reloaded;
plls_locked <= source_ld_sync and lo_ld_sync;
Port1ADC: MCP33131
GENERIC MAP(CLK_DIV => 2,
CONVCYCLES => 73)
PORT MAP(
CLK => clk160,
RESET => int_reset,
START => adc_trigger_sample,
READY => adc_port1_ready,
DATA => adc_port1_data,
MIN => adc_minmax(15 downto 0),
MAX => adc_minmax(31 downto 16),
RESET_MINMAX => adc_reset_minmax,
SDO => PORT1_SDO,
CONVSTART => PORT1_CONVSTART,
SCLK => PORT1_SCLK
);
Port2ADC: MCP33131
GENERIC MAP(CLK_DIV => 2,
CONVCYCLES => 73)
PORT MAP(
CLK => clk160,
RESET => int_reset,
START => adc_trigger_sample,
READY => open, -- synchronous ADCs, ready indicated by port 1 ADC
DATA => adc_port2_data,
MIN => adc_minmax(47 downto 32),
MAX => adc_minmax(63 downto 48),
RESET_MINMAX => adc_reset_minmax,
SDO => PORT2_SDO,
CONVSTART => PORT2_CONVSTART,
SCLK => PORT2_SCLK
);
RefADC: MCP33131
GENERIC MAP(CLK_DIV => 2,
CONVCYCLES => 73)
PORT MAP(
CLK => clk160,
RESET => int_reset,
START => adc_trigger_sample,
READY => open, -- synchronous ADCs, ready indicated by port 1 ADC
DATA => adc_ref_data,
MIN => adc_minmax(79 downto 64),
MAX => adc_minmax(95 downto 80),
RESET_MINMAX => adc_reset_minmax,
SDO => REF_SDO,
CONVSTART => REF_CONVSTART,
SCLK => REF_SCLK
);
Sampler: Sampling
GENERIC MAP(CLK_DIV => 112,
CLK_FREQ => 102400000,
IF_FREQ => 250000,
CLK_CYCLES_PRE_DONE => 0)
PORT MAP(
CLK => clk160,
RESET => sweep_reset,
PORT1 => adc_port1_data,
PORT2 => adc_port2_data,
REF => adc_ref_data,
ADC_START => adc_trigger_sample,
NEW_SAMPLE => adc_port1_ready,
DONE => sampling_done,
PRE_DONE => open,
START => sampling_start,
SAMPLES => sampling_samples,
PORT1_I => sampling_result(287 downto 240),
PORT1_Q => sampling_result(239 downto 192),
PORT2_I => sampling_result(191 downto 144),
PORT2_Q => sampling_result(143 downto 96),
REF_I => sampling_result(95 downto 48),
REF_Q => sampling_result(47 downto 0),
ACTIVE => sampling_busy
);
sweep_reset <= not aux3_sync;
SweepModule: Sweep PORT MAP(
CLK => clk160,
RESET => sweep_reset,
NPOINTS => sweep_points,
CONFIG_ADDRESS => sweep_config_address,
CONFIG_DATA => sweep_config_data,
SAMPLING_BUSY => sampling_busy,
SAMPLING_DONE => sampling_done,
START_SAMPLING => sampling_start,
PORT_SELECT => sweep_port_select,
BAND_SELECT => sweep_band,
MAX2871_DEF_4 => def_reg_4,
MAX2871_DEF_3 => def_reg_3,
MAX2871_DEF_1 => def_reg_1,
MAX2871_DEF_0 => def_reg_0,
SOURCE_REG_4 => source_reg_4,
SOURCE_REG_3 => source_reg_3,
SOURCE_REG_1 => source_reg_1,
SOURCE_REG_0 => source_reg_0,
LO_REG_4 => lo_reg_4,
LO_REG_3 => lo_reg_3,
LO_REG_1 => lo_reg_1,
LO_REG_0 => lo_reg_0,
RELOAD_PLL_REGS => reload_plls,
PLL_RELOAD_DONE => plls_reloaded,
PLL_LOCKED => plls_locked,
SWEEP_HALTED => sweep_halted,
SWEEP_RESUME => sweep_resume,
ATTENUATOR => ATTENUATION,
SOURCE_FILTER => source_filter,
SETTLING_TIME => settling_time,
EXCITE_PORT1 => sweep_excite_port1,
EXCITE_PORT2 => sweep_excite_port2,
DEBUG_STATUS => debug
);
-- Source filter mapping
FILT_IN_C1 <= '0' when source_filter = "00" or source_filter = "10" else '1';
FILT_IN_C2 <= '0' when source_filter = "11" or source_filter = "10" else '1';
FILT_OUT_C1 <= '0' when source_filter = "00" or source_filter = "10" else '1';
FILT_OUT_C2 <= '0' when source_filter = "00" or source_filter = "01" else '1';
-- PLL/SPI mux
-- only select FPGA SPI slave when both AUX1 and AUX2 are low
fpga_select <= MCU_NSS when aux1_sync = '0' and aux2_sync = '0' else '1';
-- direct connection between MCU and SOURCE when AUX1 is high
SOURCE_CLK <= MCU_SCK when aux1_sync = '1' else fpga_source_SCK;
SOURCE_MOSI <= MCU_MOSI when aux1_sync = '1' else fpga_source_MOSI;
SOURCE_LE <= MCU_NSS when aux1_sync = '1' else fpga_source_LE;
-- direct connection between MCU and LO1 when AUX2 is high
LO1_CLK <= MCU_SCK when aux2_sync = '1' else fpga_LO1_SCK;
LO1_MOSI <= MCU_MOSI when aux2_sync = '1' else fpga_LO1_MOSI;
LO1_LE <= MCU_NSS when aux2_sync = '1' else fpga_LO1_LE;
-- select MISO source
MCU_MISO <= SOURCE_MUX when aux1_sync = '1' else LO1_MUX when aux2_sync = '1' else fpga_miso;
lo_unlocked <= not lo_ld_sync;
source_unlocked <= not source_ld_sync;
SPI: SPICommands PORT MAP(
CLK => clk160,
RESET => int_reset,
SCLK => MCU_SCK,
MOSI => MCU_MOSI,
MISO => fpga_miso,
NSS => fpga_select,
NEW_SAMPLING_DATA => sampling_done,
SAMPLING_RESULT => sampling_result,
ADC_MINMAX => adc_minmax,
SOURCE_UNLOCKED => source_unlocked,
LO_UNLOCKED => lo_unlocked,
MAX2871_DEF_4 => def_reg_4,
MAX2871_DEF_3 => def_reg_3,
MAX2871_DEF_1 => def_reg_1,
MAX2871_DEF_0 => def_reg_0,
SWEEP_DATA => sweep_config_write_data,
SWEEP_ADDRESS => sweep_config_write_address,
SWEEP_WRITE => sweep_config_write,
SWEEP_POINTS => sweep_points,
NSAMPLES => sampling_samples,
SETTLING_TIME => settling_time,
PORT1_EN => port1mix_en,
PORT2_EN => port2mix_en,
REF_EN => refmix_en,
AMP_SHDN => AMP_PWDN,
SOURCE_RF_EN => SOURCE_RF_EN,
LO_RF_EN => LO1_RF_EN,
SOURCE_CE_EN => SOURCE_CE,
LO_CE_EN => LO1_CE,
LEDS => user_leds,
SYNC_SETTING => open,
INTERRUPT_ASSERTED => intr,
RESET_MINMAX => adc_reset_minmax,
SWEEP_HALTED => sweep_halted,
SWEEP_RESUME => sweep_resume,
EXCITE_PORT1 => sweep_excite_port1,
EXCITE_PORT2 => sweep_excite_port2,
DEBUG_STATUS => debug
);
ConfigMem : SweepConfigMem
PORT MAP (
clka => clk160,
ena => '1',
wea => sweep_config_write,
addra => sweep_config_write_address,
dina => sweep_config_write_data,
clkb => clk160,
addrb => sweep_config_address,
doutb => sweep_config_data
);
end Behavioral;