Partial documentation

Documentation/.gitignore

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+*.aux
+*.log
+*.synctex.gz
+*.xcf
+*.out
+*.toc
+

Documentation/DeveloperInfo/FPGA_protocol.tex

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+\documentclass{article}
+\usepackage
+[
+        a4paper,% other options: a3paper, a5paper, etc
+        left=2cm,
+        right=2cm,
+        top=2cm,
+        bottom=2cm,
+        % use vmargin=2cm to make vertical margins equal to 2cm.
+        % us  hmargin=3cm to make horizontal margins equal to 3cm.
+        % use margin=3cm to make all margins  equal to 3cm.
+]
+{geometry}
+\usepackage{tikz}
+\usepackage{siunitx} 
+
+\pgfdeclarelayer{background}
+\pgfdeclarelayer{foreground}
+\pgfsetlayers{background,main,foreground}
+
+\newcommand{\bitrect}[2]{
+  \begin{pgfonlayer}{foreground}
+    \draw [thick] (0,0) rectangle (#1,1);
+    \pgfmathsetmacro\result{#1-1}
+    \foreach \x in {1,...,\result}
+      \draw [thick] (\x,1) -- (\x, 0.8);
+  \end{pgfonlayer}
+%  \node [below left, align=right] at (0,0) {Type \\ Reset};
+  \bitlabels{#1}{#2}
+}
+\newcommand{\rwbits}[3]{
+  \draw [thick] (#1,0) rectangle ++(#2,1) node[pos=0.5]{#3};
+  \pgfmathsetmacro\start{#1+0.5}
+  \pgfmathsetmacro\finish{#1+#2-0.5}
+%  \foreach \x in {\start,...,\finish}
+%    \node [below, align=center] at (\x, 0) {R/W \\ 0};
+}
+\newcommand{\robits}[3]{
+  \begin{pgfonlayer}{background}
+    \draw [thick, fill=lightgray] (#1,0) rectangle ++(#2,1) node[pos=0.5]{#3};
+  \end{pgfonlayer}
+  \pgfmathsetmacro\start{#1+0.5}
+  \pgfmathsetmacro\finish{#1+#2-0.5}
+%  \foreach \x in {\start,...,\finish}
+%    \node [below, align=center] at (\x, 0) {RO \\ 0};
+}
+\newcommand{\bitlabels}[2]{
+  \foreach \bit in {1,...,#1}{
+     \pgfmathsetmacro\result{#2}
+     \node [above] at (\bit-0.5, 1) {\pgfmathprintnumber{\result}};
+   }
+}
+
+\begin{document}
+
+\section{Digital Interface}
+\begin{center}
+\begin{tabular}{ c|c|c }
+Pin & Direction & Function\\
+ \hline
+SCK & in & SCK for SPI communication/SCK for PLL communication\\
+MOSI & in & MOSI for SPI communication/MOSI for PLL communication\\
+MISO & out & MISO for SPI communication/MUX for PLL communication\\
+NSS & in & Chip Select for SPI communication/LE for PLL communication\\
+INTR & out & Active high interrupt indicator\\
+RESET & in & FPGA reset\\
+AUX1 & in & Selector for direct communication with Source PLL\\
+AUX2 & in & Selector for direct communication with LO PLL\\
+AUX3 & in & Active low sweep enable. Has to be high when changing settings\\
+\end{tabular}
+\end{center}
+Depending on the voltage on AUX1/AUX2 the SPI port controls either the FPGA or one of the MAX2871 PLLs:
+\begin{center}
+\begin{tabular}{ c|c|c }
+AUX1 & AUX2 & Function\\
+ \hline
+low & low & SPI communication with FPGA\\
+high & low & Direct feedthrough of SCK, MOSI, MISO and NSS to Source PLL\\
+low & high & Direct feedthrough of SCK, MOSI, MISO and NSS to LO PLL\\
+high & high & Invalid\\
+\end{tabular}
+\end{center}
+When communicating with a PLL, the MUX output of the MAX2871 is forwarded to MISO and the NSS signal is forwarded to the LE pin. As the LE pin should stay low until after a valid register has been shifted in (see MAX2871 datasheet), set NSS low before switching to PLL communication mode.
+
+\section{SPI Protocol}
+Each SPI transfer starts with pulling NSS low and ends with NSS returning to high level. SPI communication is done in words of 16\,bits. The first word after NSS is pulled low is the command word and determines the amount and meaning of the following words.
+The word received while transmitting the command word is the interrupt status register:
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\robits{0}{11}{reserved}
+\rwbits{11}{1}{SH}
+\rwbits{12}{1}{OR}
+\rwbits{13}{1}{ND}
+\rwbits{14}{1}{SU}
+\rwbits{15}{1}{LU}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{SH:} Sweep halted due to halt bit set. Sweep will be resumed once the resume command is issued.
+\item \textbf{OR:} Data overrun occured (only cleared by resetting the FPGA)
+\item \textbf{ND:} New data available
+\item \textbf{SU:} Source unlocked
+\item \textbf{LU:} LO unlocked
+\end{itemize}
+\subsection{Writing a register}
+Writing a register requires the transfer of two words: First the control word selecting the destination address and a second word containing the new register value:
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{1}{1}
+\rwbits{1}{1}{0}
+\rwbits{2}{1}{0}
+\robits{3}{9}{reserved}
+\rwbits{12}{4}{Register Address}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{Register Value}
+\end{tikzpicture}
+\end{center}
+\subsection{Writing SweepConfig}
+Initiate the sweep config transfer by sending the command word:
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{1}{0}
+\rwbits{1}{1}{0}
+\rwbits{2}{1}{0}
+\rwbits{3}{13}{Sweep point}
+\end{tikzpicture}
+\end{center}
+The maximum number of points per sweep is 4501, thus the highest valid value for "Sweep point" is 4500. After the control word, send the six words of the sweep config (see section~\ref{sweepconfig}) while keeping NSS low. The sweep config is transmitted MSB first.
+
+\subsection{Reading a sampling result}
+Whenever the ND bit in the interrupt status register is set, new sampling data is available and can be read via SPI. It has to be read before the next sampling data arrives otherwise the old data will be overwritten.
+
+Initiate the reading of sampling data by sending the command word:
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{1}{1}
+\rwbits{1}{1}{1}
+\rwbits{2}{1}{0}
+\robits{3}{13}{reserved}
+\end{tikzpicture}
+\end{center}
+Afterwards, read 18 words before setting NSS high. These 18 words will contain the sampling result (see section~\ref{result}), transmitted with the least significant word first.
+
+\subsection{Resuming a halted sweep}
+When the halt bit is set in the SweepConfig, the FPGA will configure the Source and LO as requested but will not start the settling timer (and subsequently the sampling process) until this resume command is issued. The halted sweep is indicated by the sweep halted bit in the status register.
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{1}{0}
+\rwbits{1}{1}{0}
+\rwbits{2}{1}{1}
+\robits{3}{13}{reserved}
+\end{tikzpicture}
+\end{center}
+
+\subsection{Reading ADC limits}
+The FPGA keeps track of the highest and lowest sample of each ADC to detect saturation and verify signal levels.
+
+Initiate the reading of ADC limit data by sending the command word:
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{1}{1}
+\rwbits{1}{1}{1}
+\rwbits{2}{1}{1}
+\robits{3}{13}{reserved}
+\end{tikzpicture}
+\end{center}
+Afterwards, read 6 words before setting NSS high. These 6 words will contain the sampling result:
+
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{96-\bit}
+\rwbits{0}{16}{Port 1 minimum}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{80-\bit}
+\rwbits{0}{16}{Port 1 maximum}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{64-\bit}
+\rwbits{0}{16}{Port 2 minimum}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{48-\bit}
+\rwbits{0}{16}{Port 2 maximum}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{32-\bit}
+\rwbits{0}{16}{Reference minimum}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{Reference maximum}
+\end{tikzpicture}
+\end{center}
+
+\subsection{Resetting the ADC limit}
+Issuing this command result in all minimum values set to 32767 and all maximum values set to -32768.
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{1}{0}
+\rwbits{1}{1}{1}
+\rwbits{2}{1}{1}
+\robits{3}{13}{reserved}
+\end{tikzpicture}
+\end{center}
+
+\section{Registers}
+\subsection{Interrupt Mask Register: 0x00}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\robits{0}{11}{reserved}
+\rwbits{11}{1}{SHIE}
+\rwbits{12}{1}{ORIE}
+\rwbits{13}{1}{NDIE}
+\rwbits{14}{1}{SUIE}
+\rwbits{15}{1}{LUIE}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{SHIE:} Sweep halted interrupt enable
+\item \textbf{ORIE:} Data overrun interrupt enable 
+\item \textbf{NDIE:} New data interrupt enable
+\item \textbf{SUIE:} Source unlocked interrupt enable
+\item \textbf{LUIE:} LO unlocked interrupt enable 
+\end{itemize}
+
+\subsection{Sweep Points Register: 0x01}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{Number of points per sweep - 1}
+\end{tikzpicture}
+\end{center}
+The register contains the number of points per sweep negative one, e.g. set to 11b if the sweep contains four points.
+
+\subsection{Samples Per Point Register: 0x02}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\robits{0}{6}{reserved}
+\rwbits{6}{10}{SPP[9:0]}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{SPP[9:0]:} The register contains the number of samples per point in increments of 128 samples (e.g. SPP=0b0000001000=0x08 uses 1024 samples per point). The value of this register is only used if SweepConfig[92:90] is set to 000. Otherwise it is overwritten for the sweep point with one of seven preselected values.
+\end{itemize}
+
+\subsection{System Control Register: 0x03}
+\begin{center}
+\begin{tikzpicture}
+\footnotesize
+\bitrect{16}{16-\bit}
+\rwbits{0}{1}{P1EN}
+\rwbits{1}{1}{P2EN}
+\rwbits{2}{1}{REN}
+\rwbits{3}{1}{AMEN}
+\rwbits{4}{1}{SOEN}
+\rwbits{5}{1}{LOEN}
+\rwbits{6}{1}{RLED}
+\rwbits{7}{1}{LED6}
+\rwbits{8}{1}{LED7}
+\rwbits{9}{2}{Window[1:0]}
+\rwbits{11}{1}{SCEN}
+\rwbits{12}{1}{LCEN}
+\rwbits{13}{1}{EXP2}
+\rwbits{14}{1}{EXP1}
+\rwbits{15}{1}{PSEN}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{P1EN:} Port 1 Mixers/Amplifier enable
+\item \textbf{P2EN:} Port 2 Mixers/Amplifier enable
+\item \textbf{REN:} Reference Mixers/Amplifier enable
+\item \textbf{AMEN:} Source amplifier enable
+\item \textbf{SOEN:} Source enable
+\item \textbf{LOEN:} LO enable
+\item \textbf{RLED:} External frequency LED control
+\item \textbf{LED6:}{User LED 6 control}
+\item \textbf{LED7:}{User LED 7 control}
+\item \textbf{Window[1:0]:}{Type of window to be used in calculation of real/imag of the sampling result}
+\begin{center}
+\begin{tabular}{ c|c }
+Setting & Window type\\
+ \hline
+00 & Rectangular (no window)\\
+01 & Kaiser\\
+10 & Hann\\
+11 & Flat Top\\
+\end{tabular}
+\end{center}
+\item \textbf{SCEN:}{Source chip enable}
+\item \textbf{LCEN:}{LO chip enable}
+\item \textbf{EXP1:}{Excite Port1 during sweep}
+\item \textbf{EXP2:}{Excite Port2 during sweep}
+\item \textbf{PSEN:}{Port switch enable}
+\end{itemize}
+
+\subsection{ADC Prescaler register: 0x04}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\robits{0}{8}{reserved}
+\rwbits{8}{8}{Presc[7:0]}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{Presc[7:0]:} Amount of FPGA clock cycles between ADC samples.
+$$ SR_{ADC} = \frac{\SI{102.4}{\mega\hertz}}{Presc} $$
+The minimum value for this register is 111, which results in a samplerate of roughly \SI{922.5}{\kilo\hertz}. If Presc is set to a lower value, the data acquisition from the ADC is not done when the next sample starts and samples will be skipped.
+\end{itemize}
+
+\subsection{Phase Increment: 0x05}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\robits{0}{4}{reserved}
+\rwbits{4}{12}{Phase Increment[11:0]}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{Phase Increment[7:0]:} Phase angle between ADC samples for DFT bin calculation in $\frac{2\pi}{4096}$rad.
+For a given ADC samplerate $SR_{ADC}$ and final IF frequency $f_{IF2}$ set this value to
+$$ PhaseInc = \frac{4096 * f_{IF2}}{SR_{ADC}} $$
+For the the default IF frequency of $f_{IF2} = \SI{250}{\kilo\hertz}$ this evaluates to 10*Presc (see ADC prescaler register).
+\end{itemize}
+
+\subsection{MAX2871 Default Values Registers: 0x08-0x0F}
+See datasheet of MAX2871 for bit descriptions. Bits for the fields N, FRAC, M, VCO and DIV\_A are "don't care" as they will be overwritten by the SweepConfig setting.
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{MAX2871 Register 0[15:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{MAX2871 Register 0[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{MAX2871 Register 1[15:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{MAX2871 Register 1[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{MAX2871 Register 3[15:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{MAX2871 Register 3[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{MAX2871 Register 4[15:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{MAX2871 Register 4[31:16]}
+\end{tikzpicture}
+\end{center}
+
+\section{SweepConfig}
+\label{sweepconfig}
+The SweepConfig contains data for the source and LO1 PLL as well as the attenuator and source filter. Each point in the sweep, needs a valid SweepConfig before the sweep is started.
+
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{96-\bit}
+\rwbits{0}{1}{HS}
+\rwbits{1}{2}{SettlingTime}
+\rwbits{3}{3}{Samples}
+\rwbits{6}{2}{SourceFilter}
+\rwbits{8}{8}{LO M[11:4]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{80-\bit}
+\rwbits{0}{4}{LO M[3:0]}
+\rwbits{4}{12}{LO FRAC[11:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{64-\bit}
+\rwbits{0}{3}{LO DIV\_A[2:0]}
+\rwbits{3}{6}{LO VCO[5:0]}
+\rwbits{9}{7}{LO N[6:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{48-\bit}
+\rwbits{0}{1}{BS}
+\rwbits{1}{7}{Attenuator[6:0]}
+\rwbits{8}{8}{Source M[11:4]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{32-\bit}
+\rwbits{0}{4}{Source M[3:0]}
+\rwbits{4}{12}{Source FRAC[11:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{3}{Source DIV\_A[2:0]}
+\rwbits{3}{6}{Source VCO[5:0]}
+\rwbits{9}{7}{Source N[6:0]}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{HS: Halt sweep.} If set, settling and sampling of this sweep point will be postponed until the sweep resume command is issued.
+\item \textbf{SettlingTime:} Amount of time between locking of PLLs and beginning of ADC sampling
+\begin{center}
+\begin{tabular}{ c|c }
+Setting & Time\\
+ \hline
+00 & \SI{20}{\micro\second}\\
+01 & \SI{60}{\micro\second}\\
+10 & \SI{180}{\micro\second}\\
+11 & \SI{540}{\micro\second}\\
+\end{tabular}
+\end{center}
+\item \textbf{Samples:} Number of ADC samples to take
+\begin{center}
+\begin{tabular}{ c|c|c }
+Setting & Samples & Equivalent IF bandwidth\\
+ \hline
+000 & Defined by SPP register & \SI{914}{\kilo\hertz}/SPP\\
+001 & 128 & \SI{10}{\kilo\hertz}\\
+010 & 384 & \SI{3}{\kilo\hertz}\\
+011 & 896 & \SI{1}{\kilo\hertz}\\
+100 & 3072 & \SI{300}{\hertz}\\
+101 & 9088 & \SI{100}{\hertz}\\
+110 & 30464 & \SI{30}{\hertz}\\
+111 & 91392 & \SI{10}{\hertz}\\
+\end{tabular}
+\end{center}
+\item \textbf{SourceFilter:} Low pass filter selection for source signal
+\begin{center}
+\begin{tabular}{ c|c }
+Setting & Selected Band\\
+ \hline
+00 & \SIrange{0}{900}{\mega\hertz}\\
+01 & \SIrange{900}{1800}{\mega\hertz}\\
+10 & \SIrange{1800}{3500}{\mega\hertz}\\
+11 & \SIrange{3500}{6000}{\mega\hertz}\\
+\end{tabular}
+\end{center}
+\item \textbf{BS: Band select.} Set to 0 for highband, set to 1 for lowband.
+\item \textbf{Attenuator:} Attenuation of source signal in \SI{0.25}{\decibel}.
+\end{itemize}
+
+\section{Sampling Result}
+\label{result}
+Each point in the sweep generates two sampling results. The first one contains the measurement when the source was routed to Port 1, the second sampling result was taken when the source was routed to Port 2. The sampling result does not indicate which point in the sweep it belongs to, that information is implicitly given by the order of transmitted sampling results.
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{288-\bit}
+\rwbits{0}{16}{Port 1 I[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{272-\bit}
+\rwbits{0}{16}{Port 1 I[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{256-\bit}
+\rwbits{0}{16}{Port 1 I[15:0]}
+\end{tikzpicture}
+
+\begin{tikzpicture}
+\bitrect{16}{240-\bit}
+\rwbits{0}{16}{Port 1 Q[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{224-\bit}
+\rwbits{0}{16}{Port 1 Q[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{208-\bit}
+\rwbits{0}{16}{Port 1 Q[15:0]}
+\end{tikzpicture}
+
+\begin{tikzpicture}
+\bitrect{16}{192-\bit}
+\rwbits{0}{16}{Port 2 I[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{176-\bit}
+\rwbits{0}{16}{Port 2 I[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{160-\bit}
+\rwbits{0}{16}{Port 2 I[15:0]}
+\end{tikzpicture}
+
+\begin{tikzpicture}
+\bitrect{16}{144-\bit}
+\rwbits{0}{16}{Port 2 Q[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{128-\bit}
+\rwbits{0}{16}{Port 2 Q[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{112-\bit}
+\rwbits{0}{16}{Port 2 Q[15:0]}
+\end{tikzpicture}
+
+\begin{tikzpicture}
+\bitrect{16}{96-\bit}
+\rwbits{0}{16}{Reference Signal I[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{80-\bit}
+\rwbits{0}{16}{Reference Signal I[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{64-\bit}
+\rwbits{0}{16}{Reference Signal I[15:0]}
+\end{tikzpicture}
+
+\begin{tikzpicture}
+\bitrect{16}{48-\bit}
+\rwbits{0}{16}{Reference Signal Q[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{32-\bit}
+\rwbits{0}{16}{Reference Signal Q[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{Reference Signal Q[15:0]}
+\end{tikzpicture}
+\end{center}
+
+\end{document}

Documentation/UserManual/manual.tex

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+\documentclass[a4paper,11pt]{article}
+
+\usepackage[utf8]{inputenc}
+\usepackage[T1]{fontenc} % LY1 also works
+\usepackage[margin=1in]{geometry}
+
+%% Font settings suggested by fbb documentation.
+\usepackage{textcomp} % to get the right copyright, etc.
+\usepackage[lining,tabular]{fbb} % so math uses tabular lining figures
+\usepackage[scaled=.95,type1]{cabin} % sans serif in style of Gill Sans
+\usepackage[varqu,varl]{zi4}% inconsolata typewriter
+\useosf % change normal text to use proportional oldstyle figures
+%\usetosf would provide tabular oldstyle figures in text
+
+\usepackage{microtype}
+\usepackage{siunitx}
+\DeclareSIUnit{\belmilliwatt}{Bm}
+\DeclareSIUnit{\dBm}{\deci\belmilliwatt}
+\sisetup{range-phrase=--, range-units=single, binary-units = true}
+\usepackage{graphicx}
+\usepackage{tikz}
+%\usepackage{hyperref}
+\usetikzlibrary{arrows, shadows}
+\tikzset{%
+  cascaded/.style = {%
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+      shadow scale = 1,
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+    fill = white, 
+    draw,
+    thick,
+    minimum width = 1.5cm,
+    minimum height = 2cm}}
+    
+\usepackage{enumitem}
+\setlist{leftmargin=*}
+\usepackage{listings}
+\lstset{
+	basicstyle=\ttfamily,
+	frame=single,
+	breaklines=true,
+	morecomment=[l][\color{green}]{\#},
+}
+\usepackage[os=win]{menukeys}
+\renewmenumacro{\keys}[+]{shadowedroundedkeys}
+
+\usepackage{booktabs,caption}
+\usepackage[flushleft]{threeparttable}
+\newcolumntype{L}[1]{>{\raggedright\let\newline\\\arraybackslash\hspace{0pt}}m{#1}}
+\newcolumntype{C}[1]{>{\centering\let\newline\\\arraybackslash\hspace{0pt}}m{#1}}
+\newcolumntype{R}[1]{>{\raggedleft\let\newline\\\arraybackslash\hspace{0pt}}m{#1}}
+\usepackage{tabularx} 
+
+\usepackage{stackengine}
+\usepackage{scalerel}
+\usepackage{xcolor,mdframed}
+
+\newcommand\danger[1][5ex]{%
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+}
+
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+   \makebox[0pt]{% ignore the withd of !
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+         %\fontsize{32pt}{32pt}\selectfont% make the ! bigger
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+         \raisebox{-5pt}{% move ! up a little
+            {\danger}% type the bold red !
+         }%
+      }%
+   }%
+}{\end{mdframed}}
+
+\newcommand\info[1][5ex]{%
+  \renewcommand\stacktype{L}%
+  \scaleto{\stackon[1.2pt]{\color{blue}$\bigcirc$}{\raisebox{-1.5pt}{\small i}}}{#1}%
+}
+
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+   \begin{mdframed}[%
+      backgroundcolor={blue!15}, hidealllines=true,
+      skipabove=0.7\baselineskip, skipbelow=0.7\baselineskip,
+      splitbottomskip=2pt, splittopskip=4pt, #1]%
+   \makebox[0pt]{% ignore the withd of !
+      \smash{% ignor the height of !
+         %\fontsize{32pt}{32pt}\selectfont% make the ! bigger
+         \hspace*{-45pt}% move ! to the left
+         \raisebox{-5pt}{% move ! up a little
+            {\info}% type the bold red !
+         }%
+      }%
+   }%
+}{\end{mdframed}}
+
+\usepackage{hyperref}
+\newcommand{\vna}{VNA}
+
+\title{\vna{} User Manual}
+%\author{Jan Käberich (\url{j.kaeberich@gmx.de})}
+\begin{document}
+\maketitle
+
+%\begin{abstract}
+%The Testcard is a platform for the characterization of small energy sources. It is able to charge/discharge up to eight energy sources with a predefined pattern and record their voltages.
+%\end{abstract}
+
+\setcounter{tocdepth}{2}
+\tableofcontents
+\clearpage
+
+%\section*{Nomenclature}
+%
+%\begin{description}
+%\item[Testcard] Board with the hardware to characterize up to eight energy sources.
+%\item[CLI] Command Line Interface. Program running on the computer which controls the testcard.
+%\item[Channel] One of the eight measurement units on the testcard.
+%\begin{description}
+%\item[Voltage] Voltage of the energy source connected to the channel.
+%\item[Current] Current flowing through the energy source connected to the channel. Defined as the current flowing from the energy source to the testcard, thus the source is discharged for positive and charged for negative values.
+%\end{description}
+%\item[Load] Application of a current at the channels for a specified timespan.
+%\item[Measurement] Single measurement of channel voltages at a specified point in time.
+%\item[Trace] Periodic measurement of channel voltages.
+%\item[Sequence] A combination of loads, measurements and traces.
+%\end{description}
+
+\section{Overview}
+
+\begin{tikzpicture}
+\begin{scope}[xshift=1.5cm]
+    \node[anchor=south west,inner sep=0] (image) at (0,0) {\includegraphics[width=0.76\textwidth]{TopDrawing.pdf}};
+    \begin{scope}[x={(image.south east)},y={(image.north west)}]
+		\node [anchor=south, align=center] (port1) at (0,1) {Port 1};
+		\node [anchor=south, align=center] (port2) at (0,0.2) {Port 2};
+		\node [anchor=west, align=center] (leds) at (1.05,0.8) {LEDs\\ \footnotesize Ready\\ \footnotesize Debug\\ \footnotesize Port1\\ \footnotesize Port2\\ \footnotesize Ext. Reference\\ \footnotesize Source unlocked\\ \footnotesize LO unlocked\\ \footnotesize FPGA unlocked\\ \footnotesize Booting\\ \footnotesize Power};
+		\node [anchor=west, align=center] (usb) at (1.1,0.4) {USB};
+		\node [anchor=west, align=center] (refout) at (1.1,0.2) {Reference\\Output};
+		\node [anchor=west, align=center] (refin) at (1.1,0) {Reference \\Input};
+
+        \draw [-*, ultra thick, gray] (port1) to[] (0.02,0.89);
+        \draw [-*, ultra thick, gray] (port2) to[] (0.02,0.09);
+        \draw [-*, ultra thick, gray] (leds) to[] (0.8,0.84);
+        \draw [-*, ultra thick, gray] (usb) to[] (0.91,0.5);
+        \draw [-*, ultra thick, gray] (refout) to[] (0.97,0.23);
+        \draw [-*, ultra thick, gray] (refin) to[] (0.97,0.1);
+    \end{scope}
+\end{scope}
+\end{tikzpicture}%
+
+\subsection{USB}
+The \vna{} uses a USB-C connector as the power supply and for data transmission. The hardware supports the USB power delivery standard\footnote{Work in progress, the device will not negotiate USB-PD yet}, requires \SI{5}{\volt} and draws up to \SI{1.2}{\ampere} of current.
+
+The implemented USB device is limited to USB 2.0 Fullspeed and data transmission will work with any USB 2.0 or 3.0 port (no USB-C required). However, the current consumption exceeds the specifications for USB 2.0 and 3.0 ports and the \vna{} may be unable to fully boot when the USB host limits the current.
+\subsection{RF ports}
+RF connector to connect the DUT. Both ports are identical and the device architecture support full S-Parameter measurements (S11, S21, S12 and S22).
+\begin{important}
+The RF ports have no input protection, do not apply a signal with more than +\SI{10}{\dBm} of power.
+\end{important}
+\subsection{LEDs}
+Ten LEDs indicate the status:
+\begin{description}
+\item [Ready (green)] Indicates fully booted \vna{}, ready to take measurements
+\item [Debug (green)] Not used at the moment
+\item [Port 1 (green)] Active output signal on port 1
+\item [Port 2 (green)] Active output signal on port 2
+\item [Ext. Reference (green)] External reference in use
+\item [Source unlocked (red)] The source PLL failed to lock (it may turn on briefly during a sweep, this is not a problem)
+\item [LO unlocked (red)] The 1.LO PLL failed to lock (it may turn on briefly during a sweep, this is not a problem)
+\item [FPGA unlocked (red)] The FPGA clock PLL failed to lock
+\item [Booting (red)] Indicates boot process, also used for error codes
+\item [Power (green)] USB power valid
+\end{description}
+\subsection{Reference Output}
+Optional reference output port (user selectable \SI{10}{\mega\hertz} or \SI{100}{\mega\hertz}). The output power is approximately +\SI{3}{\dBm}.
+\subsection{Reference Input}
+High impedance reference input port. When applying a \SI{10}{\mega\hertz} input signal, it can be used to overwrite the internal TCXO.
+\begin{information}
+Due to the high impedance input, the external input may detect a valid signal when picking up external radiation. If this is a problem, either terminate the reference input connector or disable automatic reference switching.
+\end{information}
+
+\section{Getting started}
+\begin{enumerate}
+\item Connect the \vna{} to a computer using the USB port. After a couple of seconds, only the "Power" and "Ready" LEDs should stay on. If the "Ready" LED does not turn on or the "Booting" LED indicates an error code, there is a problem und the device will not function properly. See section~\ref{troubleshooting} for possible solutions.
+\item Start the PC application to connect to the \vna{}. The window should look similar to this:
+\makebox[\textwidth][c]{
+\includegraphics[width=\textwidth]{ApplicationOverview.png}
+}
+\end{enumerate}
+\subsection{GUI elements types}
+The \vna{} application is made up of six areas containing different types of control:
+\begin{itemize}
+\item The \textbf{Trace Display Area} shows the measured data in various diagrams.
+\item The \textbf{Toolbars} provide access to commonly used device settings.
+\item The \textbf{Menu} at the top left handles less common settings or more complex actions (often with additional popup windows).
+\item The \textbf{Docks} mostly provide access to display related settings such as traces and markers.
+\item The \textbf{Statusbar} at the bottom show some basic informations about the connected device.
+\item The \textbf{Modeswitch} at the top right allows changing the \vna{} operating mode. Although it is primarily designed as a vector network analyzer, the hardware architecture allow some other operating modes with certain limitations.
+\end{itemize}
+Depending on the current operating mode, the available toolbars, docks and menu entries change. It is also possible to rearrange the docks and toolbars.
+
+\subsection{Common GUI elements}
+Certain control elements are always available, regardless of the selected mode. They control settings of the \vna{} that are not specific to any of the operating modes.
+\subsubsection{Reference Toolbar}
+The reference toolbar controls the external reference output as well as the input.
+\begin{center}
+\includegraphics[height=0.7cm]{ToolbarReference.png}
+\end{center}
+The reference can be set to "Int" (internal TCXO), "Ext" (external \SI{10}{\mega\hertz} signal) or to automatic mode. In automatic mode, the reference will switch to the external input when a signal is detected, otherwise it will use the internal TCXO.
+
+The external reference output may either be disabled or set to \SI{10}{\mega\hertz} or \SI{100}{\mega\hertz}.
+
+\subsubsection{Device Log Dock}
+This dock shows the debug output of the \vna{} (the same messages as on the internal UART port). It may help to identify problems, otherwise it is not required for operation.
+\begin{center}
+\includegraphics[width=\textwidth]{DockDeviceLog.png}
+\end{center}
+
+\subsubsection{Device Menu}
+The device menu controls the connection state, allows low level hardware access and to perform firmware updates:
+\begin{itemize}
+\item \textbf{Update Device List:} Scans the USB port for connected devices. Clicking this action simply updates the list of devices, no connection is established.
+\item \textbf{Connect to:} Select which \vna{} to connect to. Different devices are identified by their serial number.
+\item \textbf{Disconnect:} Disconnect from the \vna{}.
+\item \textbf{Manual Control:} Starts the manual control dialog in which all hardware settings are accessible (mostly used for testing purposes):
+\begin{center}
+\includegraphics[width=\textwidth]{DialogManualControl.png}
+\end{center}
+\item \textbf{Firmware Update:} Load a new microcontroller firmware and FPGA configuration into the \vna{}. Do not disconnect power while updating the firmware!
+\begin{center}
+\includegraphics[width=0.6\textwidth]{DialogFirmwareUpdate.png}
+\end{center}
+\end{itemize}
+
+\subsubsection{Window Menu}
+The window menu allows hiding not needed toolbars and docks. It also contains some application preferences.
+
+\section{Operating Modes}
+\subsection{Vector Network Analyzer}
+In this operating mode, the \vna{} takes S-parameter measurements. A source signal is generated and alternately applied to the RF ports. The incoming signal at both RF ports is measured, resulting in the four S-parameters S11 and S21 (when the source signal is routed to port 1) as well as S12 and S22 (when it is routed to port 2).
+\subsection{Signal Generator}
+\subsection{Spectrum Analyzer}
+
+\section{Troubleshooting}
+\label{troubleshooting}
+If the was an error in the boot process, the "Booting" LED will blink an error code repeatedly:
+\begin{center}
+\begin{threeparttable}
+\begin{tabularx}{\textwidth}{L{1cm}|X|L{7cm}}
+    \toprule
+    \textbf{Error Code} & \textbf{Meaning} & \textbf{Possible solution}\\
+     \hline
+      1   	&      Failed to detect FLASH memory  & \\
+    \hline
+      2   	&      Invalid FLASH content  & Perform firmware update\\
+    \hline
+      3   	&      Failed to configure FPGA & Check FPGA bitstream generator settings\\
+    \hline
+      4   	&      Hardware initialization failed & Verify that FPGA bitstream and uC firmware are created from the same release\\
+      \bottomrule
+\end{tabularx}
+\end{threeparttable}
+\end{center}
+\end{document}