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disable source if not used in active stage

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This commit is contained in:
Jan Käberich 2022-11-07 00:46:54 +01:00
parent 93ade5afe6
commit 1a1c9fd345
4 changed files with 18 additions and 9 deletions
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3
FPGA/VNA/Sweep.vhd
View File

@ -80,6 +80,8 @@ entity Sweep is
PORT1_ACTIVE : out STD_LOGIC;
PORT2_ACTIVE : out STD_LOGIC;
SOURCE_CE : out STD_LOGIC;
-- Debug signals
DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0);
RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0)
@ -121,6 +123,7 @@ begin
ATTENUATOR <= config_reg(45 downto 39);
SOURCE_FILTER <= config_reg(89 downto 88);
BAND_SELECT <= config_reg(48);
SOURCE_CE <= source_active;
NSAMPLES <= USER_NSAMPLES when config_reg(92 downto 90) = "000" else
std_logic_vector(to_unsigned(6, 13)) when config_reg(92 downto 90) = "001" else

15
FPGA/VNA/VNA.gise
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@ -224,7 +224,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1661101063" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1661101062">
<transform xil_pn:end_ts="1667776201" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1667776201">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@ -253,7 +253,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1661101072" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1661101063">
<transform xil_pn:end_ts="1667776245" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1667776235">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -275,7 +275,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1661101076" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1661101072">
<transform xil_pn:end_ts="1667776248" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1667776245">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
@ -284,7 +284,7 @@
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1661101188" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1661101076">
<transform xil_pn:end_ts="1667776396" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1667776248">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -298,7 +298,7 @@
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1661101201" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1661101188">
<transform xil_pn:end_ts="1667776409" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1667776396">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -312,9 +312,8 @@
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1661101208" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1661101201">
<transform xil_pn:end_ts="1667776416" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1667776409">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="top.bgn"/>
@ -366,7 +365,7 @@
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1661101201" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1661101197">
<transform xil_pn:end_ts="1667776409" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1667776405">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

BIN
FPGA/VNA/top.bin
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Binary file not shown.

9
FPGA/VNA/top.vhd
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@ -151,6 +151,7 @@ architecture Behavioral of top is
PORT1_ACTIVE : out STD_LOGIC;
PORT2_ACTIVE : out STD_LOGIC;
SOURCE_CE : out STD_LOGIC;
RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0);
DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0)
);
@ -399,6 +400,8 @@ architecture Behavioral of top is
signal sweep_excite_port1 : std_logic;
signal sweep_excite_port2 : std_logic;
signal sweep_source_CE : std_logic;
signal sweep_trigger_in : std_logic;
signal sweep_trigger_out : std_logic;
@ -413,6 +416,7 @@ architecture Behavioral of top is
signal port2mix_en : std_logic;
signal refmix_en : std_logic;
signal portswitch_en : std_logic;
signal SPI_source_CE : std_logic;
-- PLL/SPI internal mux
signal fpga_select : std_logic;
@ -722,6 +726,7 @@ begin
PORT1_ACTIVE => sweep_excite_port1,
PORT2_ACTIVE => sweep_excite_port2,
SOURCE_CE => sweep_source_CE,
DEBUG_STATUS => debug,
RESULT_INDEX => sampling_result(303 downto 288)
);
@ -751,6 +756,8 @@ begin
LO1_MUX when aux2_sync = '1' else
fpga_miso when MCU_NSS = '0' else
'Z';
SOURCE_CE <= SPI_source_CE when sweep_reset = '1' else sweep_source_CE;
lo_unlocked <= not lo_ld_sync;
source_unlocked <= not source_ld_sync;
@ -782,7 +789,7 @@ begin
AMP_SHDN => AMP_PWDN,
SOURCE_RF_EN => SOURCE_RF_EN,
LO_RF_EN => LO1_RF_EN,
SOURCE_CE_EN => SOURCE_CE,
SOURCE_CE_EN => SPI_source_CE,
LO_CE_EN => LO1_CE,
PORTSWITCH_EN => portswitch_en,
LEDS => user_leds,