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improve MCP33131 sample timing

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This commit is contained in:
Jan Käberich 2024-02-26 15:37:07 +01:00
parent ef5f9c1ab5
commit 21eb612601
6 changed files with 101 additions and 61 deletions
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33
FPGA/VNA/MCP33131.vhd
View File

@ -42,15 +42,16 @@ entity MCP33131 is
RESET_MINMAX : in STD_LOGIC;
SDO : in STD_LOGIC;
CONVSTART : out STD_LOGIC;
SCLK : out STD_LOGIC);
SCLK : inout STD_LOGIC);
end MCP33131;
architecture Behavioral of MCP33131 is
signal conv_cnt : integer range 0 to CONVCYCLES-1;
signal div_cnt : integer range 0 to (CLK_DIV/2)-1;
signal bit_cnt : integer range 0 to 15;
signal sclk_phase : std_logic;
signal adc_data : std_logic_vector(15 downto 0);
type States is (Idle, Conversion, WAIT_tEN, Transmission);
type States is (Idle, Conversion, WAIT_tEN, Transmission, Done);
signal state : States;
signal min_int, max_int, data_int : signed(15 downto 0);
begin
@ -58,6 +59,14 @@ begin
MIN <= std_logic_vector(min_int);
MAX <= std_logic_vector(max_int);
DATA <= std_logic_vector(data_int);
SCLK <= sclk_phase;
process(SCLK)
begin
if(falling_edge(SCLK)) then
adc_data <= adc_data(14 downto 0) & SDO;
end if;
end process;
process(CLK, RESET)
begin
@ -70,6 +79,7 @@ begin
CONVSTART <= '0';
conv_cnt <= 0;
div_cnt <= 0;
bit_cnt <= 0;
min_int <= to_signed(32767, 16);
max_int <= to_signed(-32768, 16);
else
@ -86,8 +96,8 @@ begin
end if;
case state is
when Idle =>
SCLK <= '0';
READY <= '0';
bit_cnt <= 0;
if START = '1' then
state <= Conversion;
conv_cnt <= 0;
@ -99,7 +109,6 @@ begin
else
div_cnt <= 0;
CONVSTART <= '0';
adc_data <= "0000000000000001";
state <= WAIT_tEN;
end if;
when WAIT_tEN =>
@ -110,22 +119,20 @@ begin
else
if(sclk_phase = '0') then
sclk_phase <= '1';
SCLK <= '1';
else
sclk_phase <= '0';
SCLK <= '0';
if(adc_data(15) = '0') then
-- not the last bit yet
adc_data <= adc_data(14 downto 0) & SDO;
if bit_cnt = 15 then
state <= Done;
else
-- last bit, move to output and indicate ready state
data_int <= signed(adc_data(14 downto 0) & SDO);
READY <= '1';
state <= Idle;
bit_cnt <= bit_cnt + 1;
end if;
end if;
div_cnt <= 0;
end if;
when Done =>
data_int <= signed(adc_data);
READY <= '1';
state <= Idle;
end case;
end if;
end if;

2
FPGA/VNA/Test_MCP33131.vhd
View File

@ -53,7 +53,7 @@ ARCHITECTURE behavior OF Test_MCP33131 IS
RESET_MINMAX : in STD_LOGIC;
SDO : IN std_logic;
CONVSTART : OUT std_logic;
SCLK : OUT std_logic
SCLK : INOUT std_logic
);
END COMPONENT;

105
FPGA/VNA/VNA.gise
View File

@ -41,7 +41,9 @@
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_MCP33131_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_MCP33131_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
@ -135,7 +137,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1604764195" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1604764195">
<transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1708955295">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
@ -165,56 +167,87 @@
<outfile xil_pn:name="top.vhd"/>
<outfile xil_pn:name="window.vhd"/>
</transform>
<transform xil_pn:end_ts="1604764128" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="3044368668303368987" xil_pn:start_ts="1604764128">
<transform xil_pn:end_ts="1708955295" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-1206566934435318832" xil_pn:start_ts="1708955295">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1604764128" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7898843873652552295" xil_pn:start_ts="1604764128">
<transform xil_pn:end_ts="1708955295" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-273551377395144626" xil_pn:start_ts="1708955295">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1604763670" xil_pn:in_ck="6306144844996157057" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604763670">
<transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1708955295">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
<outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
</transform>
<transform xil_pn:end_ts="1604764195" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1604764195">
<transform xil_pn:end_ts="1708955295" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1708955295">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1604764196" xil_pn:in_ck="4954137158046299803" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3520630626282717961" xil_pn:start_ts="1604764195">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="DFT.vhd"/>
<outfile xil_pn:name="MAX2871.vhd"/>
<outfile xil_pn:name="MCP33131.vhd"/>
<outfile xil_pn:name="ResetDelay.vhd"/>
<outfile xil_pn:name="SPIConfig.vhd"/>
<outfile xil_pn:name="Sampling.vhd"/>
<outfile xil_pn:name="Sweep.vhd"/>
<outfile xil_pn:name="Synchronizer.vhd"/>
<outfile xil_pn:name="Test_DFT.vhd"/>
<outfile xil_pn:name="Test_MAX2871.vhd"/>
<outfile xil_pn:name="Test_MCP33131.vhd"/>
<outfile xil_pn:name="Test_PLL.vhd"/>
<outfile xil_pn:name="Test_SPI.vhd"/>
<outfile xil_pn:name="Test_SPICommands.vhd"/>
<outfile xil_pn:name="Test_Sampling.vhd"/>
<outfile xil_pn:name="Test_SinCos.vhd"/>
<outfile xil_pn:name="Test_Window.vhd"/>
<outfile xil_pn:name="Test_Windowing.vhd"/>
<outfile xil_pn:name="Windowing.vhd"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
<outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
<outfile xil_pn:name="spi_slave.vhd"/>
<outfile xil_pn:name="top.vhd"/>
<outfile xil_pn:name="window.vhd"/>
</transform>
<transform xil_pn:end_ts="1604764196" xil_pn:in_ck="-6978407093755538946" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8357625476205656394" xil_pn:start_ts="1604764196">
<transform xil_pn:end_ts="1708955298" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-3530939538078141760" xil_pn:start_ts="1708955295">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="Test_MCP33131_beh.prj"/>
<outfile xil_pn:name="Test_MCP33131_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1708955298" xil_pn:in_ck="4191604156099045257" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="6352116336892055917" xil_pn:start_ts="1708955298">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="Test_MCP33131_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
</transform>
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600270761">
<status xil_pn:value="SuccessfullyRun"/>
@ -224,7 +257,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1667776201" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1667776201">
<transform xil_pn:end_ts="1708953094" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1708953094">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@ -253,7 +286,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1667776245" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1667776235">
<transform xil_pn:end_ts="1708958126" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1708958116">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -271,11 +304,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1659800190" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1659800190">
<transform xil_pn:end_ts="1708952937" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1708952937">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1667776248" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1667776245">
<transform xil_pn:end_ts="1708958131" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1708958126">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
@ -284,7 +317,7 @@
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1667776396" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1667776248">
<transform xil_pn:end_ts="1708958154" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1708958131">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -298,7 +331,7 @@
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1667776409" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1667776396">
<transform xil_pn:end_ts="1708958170" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1708958154">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -312,7 +345,7 @@
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1667776416" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1667776409">
<transform xil_pn:end_ts="1708958180" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1708958170">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@ -365,7 +398,7 @@
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1667776409" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1667776405">
<transform xil_pn:end_ts="1708958170" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1708958166">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

14
FPGA/VNA/VNA.xise
View File

@ -23,11 +23,11 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
@ -109,7 +109,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="window.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL">
@ -405,8 +405,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_DFT" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_MCP33131" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_MCP33131" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -424,7 +424,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_MCP33131" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -476,7 +476,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|window|Behavioral" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MCP33131|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

BIN
FPGA/VNA/top.bin
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FPGA/VNA/top.vhd
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@ -44,12 +44,12 @@ entity top is
TRIGGER_OUT : out STD_LOGIC;
PORT2_CONVSTART : out STD_LOGIC;
PORT2_SDO : in STD_LOGIC;
PORT2_SCLK : out STD_LOGIC;
PORT2_SCLK : inout STD_LOGIC;
PORT2_MIX2_EN : out STD_LOGIC;
PORT2_MIX1_EN : out STD_LOGIC;
PORT1_CONVSTART : out STD_LOGIC;
PORT1_SDO : in STD_LOGIC;
PORT1_SCLK : out STD_LOGIC;
PORT1_SCLK : inout STD_LOGIC;
PORT1_MIX2_EN : out STD_LOGIC;
PORT1_MIX1_EN : out STD_LOGIC;
LO1_MUX : in STD_LOGIC;
@ -83,7 +83,7 @@ entity top is
SOURCE_CE : out STD_LOGIC;
REF_CONVSTART : out STD_LOGIC;
REF_SDO : in STD_LOGIC;
REF_SCLK : out STD_LOGIC);
REF_SCLK : inout STD_LOGIC);
end top;
architecture Behavioral of top is
@ -213,7 +213,7 @@ architecture Behavioral of top is
MAX : out STD_LOGIC_VECTOR (15 downto 0);
RESET_MINMAX : in STD_LOGIC;
CONVSTART : OUT std_logic;
SCLK : OUT std_logic
SCLK : INOUT std_logic
);
END COMPONENT;
COMPONENT MAX2871