Fix generator output spikes
- Add manual overwrite in FPGA for hardware that is usually handled by sweep control - Use static hardware configuration for generator (no sweep active anymore)
This commit is contained in:
Jan Käberich
parent
36f826f7a6
commit
43b588c2f6
Binary file not shown.
@ -343,10 +343,10 @@ The register contains the number of points per sweep negative one, e.g. set to 1
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\rwbits{9}{2}{Window[1:0]}
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\rwbits{11}{1}{SCEN}
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\rwbits{12}{1}{LCEN}
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\robits{13}{3}{reserved}
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\robits{13}{2}{reserved}
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%\rwbits{13}{1}{EXP2}
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%\rwbits{14}{1}{EXP1}
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%\rwbits{15}{1}{PSEN}
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\rwbits{15}{1}{PSEN}
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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@ -426,7 +426,40 @@ Each point in the sweep is done in stages. Each stage consists of (optionally) r
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\item \textbf{IH:} Individual halt: Sets the behavior of the "halt sweep" bit (see section~\ref{sweepconfig}). If 1, the sampling is halted before each stage. If 0, the sampling is only halted before the point and all stages are executed without additional halts inbetween.
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\item \textbf{Port 1 stage} Number of stage during which the source signal is routed to port 1. Must not have the same value as Port 2 stage.
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\item \textbf{Port 2 stage} Number of stage during which the source signal is routed to port 2. Must not have the same value as Port 1 stage.
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\end{itemize}
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\subsection{Hardware override register: 0x07}
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Allows overwriting hardware settings, regardless of whether a sweep is active or not.
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\label{reg:hw_override}
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\begin{center}
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\begin{tikzpicture}
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\bitrect{16}{16-\bit}
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\rwbits{0}{1}{OWE}
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\rwbits{1}{7}{Attenuator[6:0]}
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\rwbits{8}{2}{SourceFilter}
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\rwbits{10}{1}{BS}
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\rwbits{11}{1}{P1EN}
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\rwbits{12}{1}{P2EN}
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\robits{13}{3}{reserved}
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\end{tikzpicture}
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\end{center}
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\begin{itemize}
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\item \textbf{OWE:} Overwrite enable. If 1, this register is used to configure the hardware. If 0, all other bits in the register are ignored. Must be set to 0 for valid sweep operation.
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\item \textbf{Attenuator[6:0]:} Attenuator setting
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\item \textbf{SourceFilter:} Low pass filter selection for source signal
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\begin{center}
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\begin{tabular}{ c|c }
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Setting & Selected Band\\
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\hline
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00 & \SIrange{0}{900}{\mega\hertz}\\
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01 & \SIrange{900}{1800}{\mega\hertz}\\
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10 & \SIrange{1800}{3500}{\mega\hertz}\\
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11 & \SIrange{3500}{6000}{\mega\hertz}\\
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\end{tabular}
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\end{center}
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\item \textbf{BS: Band select.} Set to 0 for highband, set to 1 for lowband.
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\item \textbf{P1EN:} Route signal to port 1. Must not be enabled at the same time as P2EN.
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\item \textbf{P2EN:} Route signal to port 2. Must not be enabled at the same time as P1EN.
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\end{itemize}
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\subsection{MAX2871 Default Values Registers: 0x08-0x0F}
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@ -72,6 +72,10 @@ entity SPICommands is
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SWEEP_HALTED : in STD_LOGIC;
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SWEEP_RESUME : out STD_LOGIC;
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-- hardware overwrite signals
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SPI_OVERWRITE_ENABLED : out STD_LOGIC;
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SPI_OVERWRITE_DATA : out STD_LOGIC_VECTOR(14 downto 0);
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-- DFT signals
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DFT_BIN1_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
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DFT_DIFFBIN_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
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@ -166,6 +170,9 @@ begin
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INTERRUPT_ASSERTED <= '0';
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latched_result <= (others => '0');
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SPI_OVERWRITE_ENABLED <= '0';
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SPI_OVERWRITE_DATA <= (others => '0');
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DFT_BIN1_PHASEINC <= (others => '0');
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DFT_DIFFBIN_PHASEINC <= (others => '0');
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dft_next <= '0';
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@ -249,6 +256,8 @@ begin
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INDIVIDUAL_HALT <= spi_buf_out(12);
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PORT1_STAGE <= spi_buf_out(5 downto 3);
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PORT2_STAGE <= spi_buf_out(2 downto 0);
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when 7 => SPI_OVERWRITE_ENABLED <= spi_buf_out(15);
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SPI_OVERWRITE_DATA <= spi_buf_out(14 downto 0);
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when 8 => MAX2871_DEF_0(15 downto 0) <= spi_buf_out;
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when 9 => MAX2871_DEF_0(31 downto 16) <= spi_buf_out;
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when 10 => MAX2871_DEF_1(15 downto 0) <= spi_buf_out;
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@ -224,7 +224,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1648844622" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1648844621">
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<transform xil_pn:end_ts="1655996970" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1655996970">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
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@ -253,7 +253,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1648846416" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1648846407">
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<transform xil_pn:end_ts="1655998603" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1655998594">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -275,7 +275,7 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1648846420" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1648846416">
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<transform xil_pn:end_ts="1655998607" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1655998603">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_ngo"/>
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@ -284,7 +284,7 @@
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<outfile xil_pn:name="top.ngd"/>
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<outfile xil_pn:name="top_ngdbuild.xrpt"/>
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</transform>
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<transform xil_pn:end_ts="1648846449" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1648846420">
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<transform xil_pn:end_ts="1655998649" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1655998607">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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@ -298,7 +298,7 @@
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<outfile xil_pn:name="top_summary.xml"/>
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<outfile xil_pn:name="top_usage.xml"/>
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</transform>
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<transform xil_pn:end_ts="1648846462" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1648846449">
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<transform xil_pn:end_ts="1655998662" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1655998649">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
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@ -312,7 +312,7 @@
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<outfile xil_pn:name="top_pad.txt"/>
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<outfile xil_pn:name="top_par.xrpt"/>
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</transform>
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<transform xil_pn:end_ts="1648846469" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1648846462">
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<transform xil_pn:end_ts="1655998669" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1655998662">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
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@ -365,7 +365,7 @@
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="InputRemoved"/>
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</transform>
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<transform xil_pn:end_ts="1648846462" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1648846459">
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<transform xil_pn:end_ts="1655998662" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1655998659">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
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BIN
FPGA/VNA/top.bin
BIN
FPGA/VNA/top.bin
Binary file not shown.
@ -268,6 +268,8 @@ architecture Behavioral of top is
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RESET_MINMAX : out STD_LOGIC;
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SWEEP_HALTED : in STD_LOGIC;
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SWEEP_RESUME : out STD_LOGIC;
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SPI_OVERWRITE_ENABLED : out STD_LOGIC;
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SPI_OVERWRITE_DATA : out STD_LOGIC_VECTOR(14 downto 0);
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DFT_BIN1_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
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DFT_DIFFBIN_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
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DFT_RESULT_READY : in STD_LOGIC;
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@ -339,6 +341,8 @@ architecture Behavioral of top is
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signal source_unlocked : std_logic;
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signal lo_unlocked : std_logic;
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signal source_filter : std_logic_vector(1 downto 0);
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-- ADC signals
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signal adc_trigger_sample : std_logic;
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signal adc_port1_ready : std_logic;
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@ -372,8 +376,9 @@ architecture Behavioral of top is
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signal sweep_port2_stage : STD_LOGIC_VECTOR (2 downto 0);
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signal sweep_config_data : std_logic_vector(95 downto 0);
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signal sweep_config_address : std_logic_vector(12 downto 0);
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signal source_filter : std_logic_vector(1 downto 0);
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signal sweep_source_filter : std_logic_vector(1 downto 0);
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signal sweep_band : std_logic;
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signal sweep_attenuator : std_logic_vector(6 downto 0);
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signal sweep_config_write_address : std_logic_vector(12 downto 0);
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signal sweep_config_write_data : std_logic_vector(95 downto 0);
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@ -419,6 +424,10 @@ architecture Behavioral of top is
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signal debug : std_logic_vector(10 downto 0);
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signal intr : std_logic;
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-- HW overwrite signals
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signal HW_overwrite_enabled : std_logic;
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signal HW_overwrite_data : std_logic_vector(14 downto 0);
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-- DFT signals
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signal dft_bin1_phaseinc : std_logic_vector (15 downto 0);
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signal dft_diffbin_phaseinc : std_logic_vector (15 downto 0);
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@ -436,20 +445,20 @@ begin
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LEDS(2) <= SOURCE_LD;
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LEDS(3) <= LO1_LD;
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-- Sweep and active port
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PORT_SELECT2 <= sweep_excite_port2 and portswitch_en;
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PORT2_SELECT <= sweep_excite_port2 and portswitch_en;
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PORT_SELECT1 <= sweep_excite_port1 and portswitch_en;
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PORT1_SELECT <= sweep_excite_port1 and portswitch_en;
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BAND_SELECT_HIGH <= not sweep_band;
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BAND_SELECT_LOW <= sweep_band;
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PORT_SELECT2 <= (sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(3);
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PORT2_SELECT <= (sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(3);
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PORT_SELECT1 <= (sweep_excite_port1 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(4);
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PORT1_SELECT <= (sweep_excite_port1 and portswitch_en) when HW_overwrite_enabled = '0' else HW_overwrite_data(4);
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BAND_SELECT_HIGH <= not sweep_band when HW_overwrite_enabled = '0' else not HW_overwrite_data(5);
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BAND_SELECT_LOW <= sweep_band when HW_overwrite_enabled = '0' else HW_overwrite_data(5);
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PORT1_MIX2_EN <= port1mix_en;
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PORT1_MIX1_EN <= not port1mix_en;
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PORT2_MIX2_EN <= port2mix_en;
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PORT2_MIX1_EN <= not port2mix_en;
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REF_MIX2_EN <= refmix_en;
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REF_MIX1_EN <= not refmix_en;
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LEDS(4) <= not (not sweep_reset and sweep_excite_port2 and portswitch_en);
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LEDS(5) <= not (not sweep_reset and sweep_excite_port1 and portswitch_en);
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LEDS(4) <= not (not sweep_reset and sweep_excite_port2 and portswitch_en) when HW_overwrite_enabled = '0' else not HW_overwrite_data(3);
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LEDS(5) <= not (not sweep_reset and sweep_excite_port1 and portswitch_en) when HW_overwrite_enabled = '0' else not HW_overwrite_data(4);
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-- Uncommitted LEDs
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LEDS(7 downto 6) <= user_leds(1 downto 0);
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--LEDS(7) <= '0';
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@ -675,8 +684,8 @@ begin
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PLL_LOCKED => plls_locked,
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SWEEP_HALTED => sweep_halted,
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SWEEP_RESUME => sweep_resume,
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ATTENUATOR => ATTENUATION,
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SOURCE_FILTER => source_filter,
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ATTENUATOR => sweep_attenuator,
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SOURCE_FILTER => sweep_source_filter,
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STAGES => sweep_stages,
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INDIVIDUAL_HALT => sweep_individual_halt,
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PORT1_STAGE => sweep_port1_stage,
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@ -689,11 +698,14 @@ begin
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);
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-- Source filter mapping
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source_filter <= sweep_source_filter when HW_overwrite_enabled = '0' else HW_overwrite_data(7 downto 6);
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FILT_IN_C1 <= '0' when source_filter = "00" or source_filter = "10" else '1';
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FILT_IN_C2 <= '0' when source_filter = "11" or source_filter = "10" else '1';
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FILT_OUT_C1 <= '0' when source_filter = "00" or source_filter = "10" else '1';
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FILT_OUT_C2 <= '0' when source_filter = "00" or source_filter = "01" else '1';
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ATTENUATION <= sweep_attenuator when HW_overwrite_enabled = '0' else HW_overwrite_data(14 downto 8);
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-- PLL/SPI mux
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-- only select FPGA SPI slave when both AUX1 and AUX2 are low
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fpga_select <= nss_sync when aux1_sync = '0' and aux2_sync = '0' else '1';
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@ -756,6 +768,8 @@ begin
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INDIVIDUAL_HALT => sweep_individual_halt,
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PORT1_STAGE => sweep_port1_stage,
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PORT2_STAGE => sweep_port2_stage,
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SPI_OVERWRITE_ENABLED => HW_overwrite_enabled,
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SPI_OVERWRITE_DATA => HW_overwrite_data,
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DFT_BIN1_PHASEINC => dft_bin1_phaseinc,
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DFT_DIFFBIN_PHASEINC => dft_diffbin_phaseinc,
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DFT_RESULT_READY => dft_ready,
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@ -259,6 +259,7 @@ inline void App_Process() {
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// insert the last received packet (restarts the timed out operation)
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USBPacketReceived(last_measure_packet);
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}
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HW::updateDeviceStatus();
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}
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}
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@ -356,6 +356,27 @@ uint16_t FPGA::GetStatus() {
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return (uint16_t) status[0] << 8 | status[1];
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}
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void FPGA::OverwriteHardware(uint8_t attenuation, LowpassFilter filter, bool lowband, bool port1_enabled, bool port2_enabled) {
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uint16_t val = 0;
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val |= 0x8000; // enable overwrite
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val |= (attenuation & 0x7F) << 8;
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val |= (int) filter << 6;
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if (lowband) {
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val |= 0x0020;
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}
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if (port1_enabled) {
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val |= 0x0010;
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}
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if (port2_enabled) {
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val |= 0x0008;
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}
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WriteRegister(Reg::HardwareOverwrite, val);
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}
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void FPGA::DisableHardwareOverwrite() {
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WriteRegister(Reg::HardwareOverwrite, 0x0000);
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}
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FPGA::ADCLimits FPGA::GetADCLimits() {
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uint16_t cmd = 0xE000;
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SwitchBytes(cmd);
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@ -18,6 +18,7 @@ enum class Reg {
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ADCPrescaler = 0x04,
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PhaseIncrement = 0x05,
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SweepSetup = 0x06,
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HardwareOverwrite = 0x07,
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MAX2871Def0LSB = 0x08,
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MAX2871Def0MSB = 0x09,
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MAX2871Def1LSB = 0x0A,
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@ -134,6 +135,9 @@ void ResetADCLimits();
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void ResumeHaltedSweep();
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uint16_t GetStatus();
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void OverwriteHardware(uint8_t attenuation, LowpassFilter filter, bool lowband, bool port1_enabled, bool port2_enabled);
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void DisableHardwareOverwrite();
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void StartSweep();
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void AbortSweep();
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@ -2,73 +2,59 @@
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#include "Generator.hpp"
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#include "Manual.hpp"
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#include "Hardware.hpp"
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#include "HW_HAL.hpp"
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#include "max2871.hpp"
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#include "Si5351C.hpp"
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void Generator::Setup(Protocol::GeneratorSettings g) {
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if(g.activePort == 0) {
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// both ports disabled, no need to configure PLLs
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HW::SetIdle();
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return;
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}
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Protocol::ManualControlV1 m;
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// LOs not required
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m.LO1CE = 0;
|
||||
m.LO1Frequency = 1000000000;
|
||||
m.LO1RFEN = 0;
|
||||
m.LO1RFEN = 0;
|
||||
m.LO2EN = 0;
|
||||
m.LO2Frequency = 60000000;
|
||||
m.Port1EN = 0;
|
||||
m.Port2EN = 0;
|
||||
m.RefEN = 0;
|
||||
m.Samples = 131072;
|
||||
m.WindowType = (int) FPGA::Window::None;
|
||||
using namespace HWHAL;
|
||||
|
||||
switch(g.activePort) {
|
||||
case 1:
|
||||
m.AmplifierEN = 1;
|
||||
m.PortSwitch = 0;
|
||||
break;
|
||||
case 2:
|
||||
m.AmplifierEN = 1;
|
||||
m.PortSwitch = 1;
|
||||
break;
|
||||
void Generator::Setup(Protocol::GeneratorSettings g) {
|
||||
HW::SetMode(HW::Mode::Generator);
|
||||
if(g.activePort == 0) {
|
||||
// both ports disabled, no need to configure PLLs
|
||||
Si5351.Disable(SiChannel::LowbandSource);
|
||||
FPGA::Disable(FPGA::Periphery::SourceChip);
|
||||
FPGA::Disable(FPGA::Periphery::Amplifier);
|
||||
FPGA::Disable(FPGA::Periphery::SourceRF);
|
||||
FPGA::Disable(FPGA::Periphery::PortSwitch);
|
||||
FPGA::DisableHardwareOverwrite();
|
||||
return;
|
||||
}
|
||||
|
||||
g.frequency = Cal::FrequencyCorrectionToDevice(g.frequency);
|
||||
auto amplitude = HW::GetAmplitudeSettings(g.cdbm_level, g.frequency, g.applyAmplitudeCorrection, g.activePort == 2);
|
||||
// Select correct source
|
||||
bool bandSelect;
|
||||
FPGA::LowpassFilter lp = FPGA::LowpassFilter::M947;
|
||||
if(g.frequency < HW::BandSwitchFrequency) {
|
||||
m.SourceLowEN = 1;
|
||||
m.SourceLowFrequency = g.frequency;
|
||||
m.SourceHighCE = 0;
|
||||
m.SourceHighRFEN = 0;
|
||||
m.SourceHighFrequency = HW::BandSwitchFrequency;
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::M947;
|
||||
m.SourceHighPower = (int) MAX2871::Power::n4dbm;
|
||||
m.SourceHighband = false;
|
||||
m.SourceLowPower = (int) amplitude.lowBandPower;
|
||||
bandSelect = true;
|
||||
FPGA::Disable(FPGA::Periphery::SourceChip);
|
||||
Si5351.SetCLK(SiChannel::LowbandSource, g.frequency, Si5351C::PLL::B,
|
||||
amplitude.lowBandPower);
|
||||
Si5351.Enable(SiChannel::LowbandSource);
|
||||
} else {
|
||||
m.SourceLowEN = 0;
|
||||
m.SourceLowFrequency = HW::BandSwitchFrequency;
|
||||
m.SourceHighCE = 1;
|
||||
m.SourceHighRFEN = 1;
|
||||
m.SourceHighFrequency = g.frequency;
|
||||
bandSelect = false;
|
||||
Si5351.Disable(SiChannel::LowbandSource);
|
||||
FPGA::Enable(FPGA::Periphery::SourceChip);
|
||||
FPGA::SetMode(FPGA::Mode::SourcePLL);
|
||||
Source.SetPowerOutA(amplitude.highBandPower);
|
||||
Source.SetFrequency(g.frequency);
|
||||
Source.Update();
|
||||
FPGA::SetMode(FPGA::Mode::FPGA);
|
||||
if(g.frequency < 900000000UL) {
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::M947;
|
||||
lp = FPGA::LowpassFilter::M947;
|
||||
} else if(g.frequency < 1800000000UL) {
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::M1880;
|
||||
lp = FPGA::LowpassFilter::M1880;
|
||||
} else if(g.frequency < 3500000000UL) {
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::M3500;
|
||||
lp = FPGA::LowpassFilter::M3500;
|
||||
} else {
|
||||
m.SourceHighLowpass = (int) FPGA::LowpassFilter::None;
|
||||
lp = FPGA::LowpassFilter::None;
|
||||
}
|
||||
m.SourceHighband = true;
|
||||
m.SourceHighPower = (int) amplitude.highBandPower;
|
||||
m.SourceLowPower = (int) Si5351C::DriveStrength::mA2;
|
||||
}
|
||||
|
||||
m.attenuator = amplitude.attenuator;
|
||||
Manual::Setup(m);
|
||||
FPGA::OverwriteHardware(amplitude.attenuator, lp, bandSelect, g.activePort == 1, g.activePort == 2);
|
||||
HW::SetOutputUnlevel(amplitude.unlevel);
|
||||
FPGA::Enable(FPGA::Periphery::Amplifier, true);
|
||||
FPGA::Enable(FPGA::Periphery::SourceRF, true);
|
||||
FPGA::Enable(FPGA::Periphery::PortSwitch, true);
|
||||
}
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
#include "Manual.hpp"
|
||||
#include "delay.hpp"
|
||||
#include "SpectrumAnalyzer.hpp"
|
||||
#include "Communication.h"
|
||||
#include <cstring>
|
||||
|
||||
#define LOG_LEVEL LOG_LEVEL_INFO
|
||||
@ -139,6 +140,8 @@ bool HW::Init() {
|
||||
return false;
|
||||
}
|
||||
|
||||
FPGA::DisableHardwareOverwrite();
|
||||
|
||||
// Set default ADC samplerate
|
||||
FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, ADCprescaler);
|
||||
// Set phase increment according to
|
||||
@ -229,6 +232,7 @@ void HW::SetIdle() {
|
||||
unlevel = false;
|
||||
FPGA::AbortSweep();
|
||||
FPGA::SetMode(FPGA::Mode::FPGA);
|
||||
FPGA::DisableHardwareOverwrite();
|
||||
FPGA::Enable(FPGA::Periphery::SourceChip, false);
|
||||
FPGA::Enable(FPGA::Periphery::SourceRF, false);
|
||||
FPGA::Enable(FPGA::Periphery::LO1Chip, false);
|
||||
@ -289,7 +293,7 @@ HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool
|
||||
|
||||
bool HW::TimedOut() {
|
||||
constexpr uint64_t timeout = 1000000;
|
||||
if(activeMode != Mode::Idle && Delay::get_us() - lastISR > timeout) {
|
||||
if(activeMode != Mode::Idle && activeMode != Mode::Generator && Delay::get_us() - lastISR > timeout) {
|
||||
return true;
|
||||
} else {
|
||||
return false;
|
||||
@ -420,6 +424,28 @@ uint64_t HW::getLastISRTimestamp() {
|
||||
return lastISR;
|
||||
}
|
||||
|
||||
void HW::updateDeviceStatus() {
|
||||
if(activeMode == Mode::Idle || activeMode == Mode::Generator) {
|
||||
static uint32_t last_update = 0;
|
||||
if(HAL_GetTick() - last_update >= 1000) {
|
||||
last_update = HAL_GetTick();
|
||||
HW::Ref::update();
|
||||
Protocol::PacketInfo packet;
|
||||
packet.type = Protocol::PacketType::DeviceStatusV1;
|
||||
// Enable PLL chips for temperature reading
|
||||
bool srcEn = FPGA::IsEnabled(FPGA::Periphery::SourceChip);
|
||||
bool LOEn = FPGA::IsEnabled(FPGA::Periphery::LO1Chip);
|
||||
FPGA::Enable(FPGA::Periphery::SourceChip);
|
||||
FPGA::Enable(FPGA::Periphery::LO1Chip);
|
||||
HW::getDeviceStatus(&packet.statusV1, true);
|
||||
// restore PLL state
|
||||
FPGA::Enable(FPGA::Periphery::SourceChip, srcEn);
|
||||
FPGA::Enable(FPGA::Periphery::LO1Chip, LOEn);
|
||||
Communication::Send(packet);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint16_t HW::getDFTPhaseInc() {
|
||||
return DFTphaseInc;
|
||||
}
|
||||
|
||||
@ -88,6 +88,7 @@ static constexpr Protocol::DeviceInfo Info = {
|
||||
enum class Mode {
|
||||
Idle,
|
||||
Manual,
|
||||
Generator,
|
||||
VNA,
|
||||
SA,
|
||||
};
|
||||
@ -101,6 +102,8 @@ uint64_t getLastISRTimestamp();
|
||||
|
||||
void SetOutputUnlevel(bool unlev);
|
||||
|
||||
void updateDeviceStatus();
|
||||
|
||||
using AmplitudeSettings = struct _amplitudeSettings {
|
||||
uint8_t attenuator;
|
||||
union {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user