Bugfixes and improvements for new hardware

2020-09-14 23:13:32 +02:00 · 2020-09-14 23:13:32 +02:00 · 4cbd60e62d
commit 4cbd60e62d
parent 7d9d5e27eb
33 changed files with 747 additions and 193 deletions
--- a/FPGA/.gitignore
+++ b/FPGA/.gitignore
@ -7,4 +7,5 @@
 */ipcore_dir
 !*.gise
 !*.xise
+!*.py

--- a/FPGA/VNA/VNA.gise
+++ b/FPGA/VNA/VNA.gise
@ -223,7 +223,7 @@
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1600073684" xil_pn:in_ck="-94812602667091528" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600073666">
+    <transform xil_pn:end_ts="1600104613" xil_pn:in_ck="-94812602667091528" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600104595">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
@ -241,11 +241,11 @@
      <outfile xil_pn:name="webtalk_pn.xml"/>
      <outfile xil_pn:name="xst"/>
    </transform>
-    <transform xil_pn:end_ts="1598796368" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1598796368">
+    <transform xil_pn:end_ts="1600116406" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1600116406">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
    </transform>
-    <transform xil_pn:end_ts="1600073692" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600073686">
+    <transform xil_pn:end_ts="1600116413" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600116406">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_ngo"/>
@ -254,7 +254,7 @@
      <outfile xil_pn:name="top.ngd"/>
      <outfile xil_pn:name="top_ngdbuild.xrpt"/>
    </transform>
-    <transform xil_pn:end_ts="1600073728" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600073692">
+    <transform xil_pn:end_ts="1600116446" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600116413">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
@ -270,7 +270,7 @@
      <outfile xil_pn:name="top_summary.xml"/>
      <outfile xil_pn:name="top_usage.xml"/>
    </transform>
-    <transform xil_pn:end_ts="1600073755" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600073728">
+    <transform xil_pn:end_ts="1600116473" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600116446">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -284,7 +284,7 @@
      <outfile xil_pn:name="top_pad.txt"/>
      <outfile xil_pn:name="top_par.xrpt"/>
    </transform>
-    <transform xil_pn:end_ts="1600073768" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="4970201210546912173" xil_pn:start_ts="1600073755">
+    <transform xil_pn:end_ts="1600116486" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1600116473">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="WarningsGenerated"/>
      <status xil_pn:value="ReadyToRun"/>
@ -330,7 +330,7 @@
      <status xil_pn:value="OutputChanged"/>
      <status xil_pn:value="OutputRemoved"/>
    </transform>
-    <transform xil_pn:end_ts="1600073755" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600073748">
+    <transform xil_pn:end_ts="1600116473" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600116466">
      <status xil_pn:value="SuccessfullyRun"/>
      <status xil_pn:value="ReadyToRun"/>
      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
--- a/FPGA/VNA/VNA.xise
+++ b/FPGA/VNA/VNA.xise
@ -406,7 +406,7 @@
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Float" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
--- a/FPGA/VNA/top.ucf
+++ b/FPGA/VNA/top.ucf
@ -68,10 +68,10 @@ NET "ATTENUATION[3]" LOC = P12;
 NET "ATTENUATION[2]" LOC = P14;
 NET "ATTENUATION[1]" LOC = P15;
 NET "ATTENUATION[0]" LOC = P16;
-NET "LEDS[0]" LOC = P92;
-NET "LEDS[1]" LOC = P93;
-NET "LEDS[2]" LOC = P88;
-NET "LEDS[3]" LOC = P87;
+NET "LEDS[0]" LOC = P87;
+NET "LEDS[1]" LOC = P92;
+NET "LEDS[2]" LOC = P93;
+NET "LEDS[3]" LOC = P88;
 NET "LEDS[4]" LOC = P85;
 NET "LEDS[5]" LOC = P84;
 NET "LEDS[6]" LOC = P83;
--- a/FPGA/VNA/top.vhd
+++ b/FPGA/VNA/top.vhd
@ -365,10 +365,10 @@ begin
 	LEDS(2) <= SOURCE_LD;
 	LEDS(3) <= LO1_LD;
 	-- Sweep and active port
-	PORT_SELECT2 <= sweep_port_select;
-	PORT2_SELECT <= sweep_port_select;
-	PORT_SELECT1 <= not sweep_port_select;
-	PORT1_SELECT <= not sweep_port_select;
+	PORT_SELECT2 <= not sweep_port_select;
+	PORT2_SELECT <= not sweep_port_select;
+	PORT_SELECT1 <= sweep_port_select;
+	PORT1_SELECT <= sweep_port_select;
 	BAND_SELECT_HIGH <= not sweep_band;
 	BAND_SELECT_LOW <= sweep_band;
 	PORT1_MIX2_EN <= port1mix_en;
@ -377,8 +377,8 @@ begin
 	PORT2_MIX1_EN <= not port2mix_en;
 	REF_MIX2_EN <= refmix_en;
 	REF_MIX1_EN <= not refmix_en;
-	LEDS(4) <= not (not sweep_reset and sweep_port_select);
-	LEDS(5) <= not (not sweep_reset and not sweep_port_select);
+	LEDS(4) <= not (not sweep_reset and not sweep_port_select);
+	LEDS(5) <= not (not sweep_reset and sweep_port_select);
 	-- Uncommitted LEDs
 	LEDS(7 downto 6) <= user_leds(1 downto 0);	
 	--LEDS(7) <= '0';
@ -608,7 +608,10 @@ begin
 	LO1_MOSI <= MCU_MOSI when aux2_sync = '1' else fpga_LO1_MOSI;
 	LO1_LE <= MCU_NSS when aux2_sync = '1' else fpga_LO1_LE;
 	-- select MISO source
-	MCU_MISO <= SOURCE_MUX when aux1_sync = '1' else LO1_MUX when aux2_sync = '1' else fpga_miso;
+	MCU_MISO <= SOURCE_MUX when aux1_sync = '1' else
+					LO1_MUX when aux2_sync = '1' else
+					fpga_miso when MCU_NSS = '0' else
+					'Z';

 	lo_unlocked <= not lo_ld_sync;
 	source_unlocked <= not source_ld_sync;
--- a/FPGA/WindowCoefficientGenerator.py
+++ b/FPGA/WindowCoefficientGenerator.py
@ -0,0 +1,46 @@
+#!/usr/bin/env python3
+
+import math
+
+# Adapt these constants to your window requirements
+NUMBER_OF_COEFFICIENTS = 128
+BITS_PER_COEFFICIENT = 16
+
+# If set to true, the coefficients will be scaled to include the window amplitude correction factor.
+# They will also be scaled to 1/8 to have enough headroom for the correction.
+INCLUDE_AMPLITUDE_CORRECTION = True
+
+# Don't change anything below this line
+
+class Window:
+    def __init__(self, name, function, correction):
+        self.name = name
+        self.function = function
+        self.correction = correction
+    
+    def StartFile(self):
+        self.file = open(self.name+".txt", "w")
+
+    def AddCoefficient(self, normalized_index):
+        if not hasattr(self, 'file'):
+            self.StartFile()
+        value = self.function(normalized_index)
+        if INCLUDE_AMPLITUDE_CORRECTION:
+            value = value * self.correction / 8.0
+        value = int(value * (2 ** (BITS_PER_COEFFICIENT-1)))
+        # prevent overflow
+        if value >= (2 ** (BITS_PER_COEFFICIENT-1)):
+            value = value - 1
+        output = "{0:b}".format(value)
+        self.file.write(output.zfill(BITS_PER_COEFFICIENT)+"\n")
+
+def calc_hann(i):
+    return math.sin(math.pi * i) ** 2   
+
+WindowList = []
+WindowList.append(Window("Hann", calc_hann, 2.0))
+
+for i in range(NUMBER_OF_COEFFICIENTS):
+    norm_i = (i+0.5) / NUMBER_OF_COEFFICIENTS
+    for w in WindowList:
+        w.AddCoefficient(norm_i)
--- a/Software/PC_Application/Application
+++ b/Software/PC_Application/Application
--- a/Software/PC_Application/Device/device.cpp
+++ b/Software/PC_Application/Device/device.cpp
@ -357,9 +357,11 @@ void Device::ReceivedData()
            break;
        case Protocol::PacketType::Ack:
            emit AckReceived();
+//            transmissionFinished(TransmissionResult::Ack);
            break;
        case Protocol::PacketType::Nack:
            emit NackReceived();
+//            transmissionFinished(TransmissionResult::Nack);
            break;
        default:
            break;
@ -389,7 +391,7 @@ QString Device::serial() const

 void Device::startNextTransmission()
 {
-    if(transmissionQueue.empty() || !m_connected) {
+    if(transmissionQueue.isEmpty() || !m_connected) {
        // nothing more to transmit
        transmissionActive = false;
        return;
@ -416,9 +418,13 @@ void Device::transmissionFinished(TransmissionResult result)
 {
    transmissionTimer.stop();
    // remove transmitted packet
-    auto t = transmissionQueue.dequeue();
-    if(t.callback) {
-        t.callback(result);
+    if(!transmissionQueue.isEmpty()) {
+        auto t = transmissionQueue.dequeue();
+        if(t.callback) {
+            t.callback(result);
+        }
+        startNextTransmission();
+    } else {
+        transmissionActive = false;
    }
-    startNextTransmission();
 }
--- a/Software/PC_Application/Device/firmwareupdatedialog.cpp
+++ b/Software/PC_Application/Device/firmwareupdatedialog.cpp
@ -57,6 +57,7 @@ void FirmwareUpdateDialog::on_bStart_clicked()
        abortWithError("Invalid magic header constant");
        return;
    }
+    file->seek(0);
    state = State::ErasingFLASH;
    connect(dev, &Device::AckReceived, this, &FirmwareUpdateDialog::receivedAck);
    connect(dev, &Device::NackReceived, this, &FirmwareUpdateDialog::receivedNack);
@ -73,6 +74,7 @@ void FirmwareUpdateDialog::addStatus(QString line)

 void FirmwareUpdateDialog::abortWithError(QString error)
 {
+    timer.stop();
    disconnect(dev, &Device::AckReceived, this, &FirmwareUpdateDialog::receivedAck);
    disconnect(dev, &Device::NackReceived, this, &FirmwareUpdateDialog::receivedNack);

@ -129,9 +131,10 @@ void FirmwareUpdateDialog::receivedAck()
            state = State::TriggeringUpdate;
            dev->SendCommandWithoutPayload(Protocol::PacketType::PerformFirmwareUpdate);
            timer.start(5000);
+        } else {
+            sendNextFirmwareChunk();
+            timer.start(1000);
        }
-        sendNextFirmwareChunk();
-        timer.start(1000);
        break;
    case State::TriggeringUpdate:
        addStatus("Rebooting device...");
@ -149,7 +152,15 @@ void FirmwareUpdateDialog::receivedAck()

 void FirmwareUpdateDialog::receivedNack()
 {
-    abortWithError("Nack received, device does not support firmware update");
+    switch(state) {
+    case State::ErasingFLASH:
+        abortWithError("Nack received, device does not support firmware update");
+        break;
+    default:
+        abortWithError("Nack received, something went wrong");
+        break;
+    }
+
 }

 void FirmwareUpdateDialog::sendNextFirmwareChunk()
--- a/Software/VNA_embedded/.cproject
+++ b/Software/VNA_embedded/.cproject
@ -29,7 +29,7 @@
            			
            <storageModule moduleId="cdtBuildSystem" version="4.0.0">
                				
-                <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="fr.ac6.managedbuild.config.gnu.cross.exe.debug" postannouncebuildStep="Generating hex and Printing size information:" postbuildStep="arm-none-eabi-objcopy -O ihex &quot;${BuildArtifactFileBaseName}.elf&quot; &quot;${BuildArtifactFileBaseName}.hex&quot; &amp;&amp; arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;">
+                <configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=" parent="fr.ac6.managedbuild.config.gnu.cross.exe.debug" postannouncebuildStep="Generating hex and Printing size information:" postbuildStep="arm-none-eabi-objcopy -O binary &quot;${BuildArtifactFileBaseName}.elf&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; &amp;&amp; arm-none-eabi-objcopy -O ihex &quot;${BuildArtifactFileBaseName}.elf&quot; &quot;${BuildArtifactFileBaseName}.hex&quot; &amp;&amp; arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;">
                    					
                    <folderInfo id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410." name="/" resourcePath="">
                        						
@ -779,7 +779,7 @@
        		
        <configuration configurationName="Debug">
            			
-            <resource resourceType="PROJECT" workspacePath="/VNA_embedded"/>
+            <resource resourceType="PROJECT" workspacePath="VNA_embedded"/>
            		
        </configuration>
        		
--- a/Software/VNA_embedded/.mxproject
+++ b/Software/VNA_embedded/.mxproject
--- a/Software/VNA_embedded/Application/App.cpp
+++ b/Software/VNA_embedded/Application/App.cpp
@ -12,6 +12,7 @@
 #include "Flash.hpp"
 #include "FreeRTOS.h"
 #include "task.h"
+#include "Led.hpp"

 #define LOG_LEVEL	LOG_LEVEL_INFO
 #define LOG_MODULE	"App"
@ -66,6 +67,8 @@ void App_Start() {
 	handle = xTaskGetCurrentTaskHandle();
 	usb_init(communication_usb_input);
 	Log_Init();
+	LED::Init();
+	LED::Pulsating();
 	Communication::SetCallback(USBPacketReceived);
 	// Pass on logging output to USB
 	Log_SetRedirect(usb_log);
@ -74,23 +77,34 @@ void App_Start() {
 #ifdef HAS_FLASH
 	if(!flash.isPresent()) {
 		LOG_CRIT("Failed to detect onboard FLASH");
+		LED::Error(1);
 	}
 	auto fw_info = Firmware::GetFlashContentInfo(&flash);
 	if(fw_info.valid) {
 		if(fw_info.CPU_need_update) {
 			// Function will not return, the device will reboot with the new firmware instead
-			Firmware::PerformUpdate(&flash);
+//			Firmware::PerformUpdate(&flash, fw_info);
+		}
+		if(!FPGA::Configure(&flash, fw_info.FPGA_bitstream_address, fw_info.FPGA_bitstream_size)) {
+			LOG_CRIT("FPGA configuration failed");
+			LED::Error(3);
 		}
-		FPGA::Configure(&flash, fw_info.FPGA_bitstream_address, fw_info.FPGA_bitstream_size);
 	} else {
 		LOG_CRIT("Invalid bitstream/firmware, not configuring FPGA");
+		LED::Error(2);
 	}
 #else
 	// The FPGA configures itself from the flash, allow time for this
 	vTaskDelay(2000);
 #endif
+#if HW_REVISION == 'B'
+	// Enable supply to RF circuit
+	EN_6V_GPIO_Port->BSRR = EN_6V_Pin;
+#endif
+
 	if (!VNA::Init()) {
 		LOG_CRIT("Initialization failed, unable to start");
+		LED::Error(4);
 	}

 #if HW_REVISION == 'A'
@ -102,6 +116,7 @@ void App_Start() {
 	bool sweepActive = false;
 	Protocol::ReferenceSettings reference;

+	LED::Off();
 	while (1) {
 		uint32_t notification;
 		if(xTaskNotifyWait(0x00, UINT32_MAX, &notification, 100) == pdPASS) {
@ -190,7 +205,7 @@ void App_Start() {
 					break;
 #ifdef HAS_FLASH
 				case Protocol::PacketType::ClearFlash:
-					FPGA::AbortSweep();
+					VNA::SetIdle();
 					sweepActive = false;
 					LOG_DEBUG("Erasing FLASH in preparation for firmware update...");
 					if(flash.eraseChip()) {
@ -203,10 +218,15 @@ void App_Start() {
 					break;
 				case Protocol::PacketType::FirmwarePacket:
 					LOG_INFO("Writing firmware packet at address %u", packet.firmware.address);
-					flash.write(packet.firmware.address, sizeof(packet.firmware.data), packet.firmware.data);
-					Communication::SendWithoutPayload(Protocol::PacketType::Ack);
+					if(flash.write(packet.firmware.address, sizeof(packet.firmware.data), packet.firmware.data)) {
+						Communication::SendWithoutPayload(Protocol::PacketType::Ack);
+					} else {
+						LOG_ERR("Failed to write FLASH");
+						Communication::SendWithoutPayload(Protocol::PacketType::Nack);
+					}
 					break;
 				case Protocol::PacketType::PerformFirmwareUpdate: {
+					LOG_INFO("Firmware update process triggered");
 					auto fw_info = Firmware::GetFlashContentInfo(&flash);
 					if(fw_info.valid) {
 						Protocol::PacketInfo p;
@ -214,7 +234,7 @@ void App_Start() {
 						Communication::Send(p);
 						// Some delay to allow communication to finish
 						vTaskDelay(1000);
-						Firmware::PerformUpdate(&flash);
+						Firmware::PerformUpdate(&flash, fw_info);
 						// should never get here
 						Communication::SendWithoutPayload(Protocol::PacketType::Nack);
 					}
@ -230,8 +250,7 @@ void App_Start() {
 		}

 		if(sweepActive && HAL_GetTick() - lastNewPoint > 1000) {
-			LOG_WARN("Timed out waiting for point, last received point was %d", result.pointNum);
-			LOG_WARN("FPGA status: 0x%04x", FPGA::GetStatus());
+			LOG_WARN("Timed out waiting for point, last received point was %d (Status 0x%04x)", result.pointNum, FPGA::GetStatus());
 			FPGA::AbortSweep();
 			// restart the current sweep
 			VNA::Init();
--- a/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
+++ b/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
@ -14,10 +14,17 @@ static uint16_t ISRMaskReg = 0x0000;

 using namespace FPGAHAL;

+static void SwitchBytes(uint16_t &value) {
+	value = (value & 0xFF00) >> 8 | (value & 0x00FF) << 8;
+}
+static void SwitchBytes(int16_t &value) {
+	value = (value & 0xFF00) >> 8 | (value & 0x00FF) << 8;
+}
+
 void WriteRegister(FPGA::Reg reg, uint16_t value) {
-	uint16_t cmd[2] = {(uint16_t) (0x8000 | (uint16_t) reg), value};
+	uint8_t cmd[4] = {0x80, (uint8_t) reg, (uint8_t) (value >> 8), (uint8_t) (value & 0xFF)};
 	Low(CS);
-	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) cmd, 2, 100);
+	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) cmd, 4, 100);
 	High(CS);
 }

@ -34,8 +41,18 @@ bool FPGA::Configure(Flash *f, uint32_t start_address, uint32_t bitstream_size)
 	High(PROGRAM_B);
 	while(!isHigh(INIT_B));

+	if(isHigh(DONE)) {
+		LOG_ERR("DONE not asserted, aborting configuration");
+		return false;
+	}
+
+	uint32_t lastmessage = HAL_GetTick();
 	uint8_t buf[256];
 	while(bitstream_size > 0) {
+		if(HAL_GetTick() - lastmessage > 100) {
+			LOG_DEBUG("Remaining: %lu", bitstream_size);
+			lastmessage = HAL_GetTick();
+		}
 		uint16_t size = sizeof(buf);
 		if(size > bitstream_size) {
 			size = bitstream_size;
@ -73,18 +90,20 @@ bool FPGA::Init(HaltedCallback cb) {
 	Delay::ms(10);

 	// Check if FPGA response is as expected
-	uint16_t cmd[2] = {0x4000, 0x0000};
-	uint16_t recv[2];
+	uint8_t cmd[4] = {0x40, 0x00, 0x00, 0x00};
+	uint8_t recv[4];
 	Low(CS);
-	HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) cmd, (uint8_t*) recv, 2, 100);
+	HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) cmd, (uint8_t*) recv, 4, 100);
 	High(CS);

-	if(recv[1] != 0xF0A5) {
-		LOG_ERR("Initialization failed, got 0x%04x instead of 0xF0A5", recv[1]);
+	uint16_t resp = (uint16_t) recv[2] << 8 | recv[3];
+	uint16_t status = (uint16_t) recv[0] << 8 | recv[1];
+	if(resp != 0xF0A5) {
+		LOG_ERR("Initialization failed, got 0x%04x instead of 0xF0A5", resp);
 		return false;
 	}

-	LOG_DEBUG("Initialized, status register: 0x%04x", recv[0]);
+	LOG_DEBUG("Initialized, status register: 0x%04x", status);
 	return true;
 }

@ -183,8 +202,15 @@ void FPGA::WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceReg
 	}
 	send[5] = (Source_M & 0x000F) << 12 | Source_FRAC;
 	send[6] = Source_DIV_A << 13 | Source_VCO << 7 | Source_N;
+	SwitchBytes(send[0]);
+	SwitchBytes(send[1]);
+	SwitchBytes(send[2]);
+	SwitchBytes(send[3]);
+	SwitchBytes(send[4]);
+	SwitchBytes(send[5]);
+	SwitchBytes(send[6]);
 	Low(CS);
-	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) send, 7, 100);
+	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) send, 14, 100);
 	High(CS);
 }

@ -194,17 +220,18 @@ static inline int64_t sign_extend_64(int64_t x, uint16_t bits) {
 }

 static FPGA::ReadCallback callback;
-static uint16_t raw[18];
+static uint8_t raw[36];
 static bool halted;

 bool FPGA::InitiateSampleRead(ReadCallback cb) {
 	callback = cb;
-	uint16_t cmd = 0xC000;
+	uint8_t cmd[2] = {0xC0, 0x00};
 	uint16_t status;

 	Low(CS);
-	HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) &cmd, (uint8_t*) &status, 1,
-			100);
+	HAL_SPI_TransmitReceive(&FPGA_SPI, cmd, (uint8_t*) &status, 2, 100);
+
+	SwitchBytes(status);

 	if (status & 0x0010) {
 		halted = true;
@ -227,27 +254,28 @@ bool FPGA::InitiateSampleRead(ReadCallback cb) {
 	}

 	// Start data read
-	HAL_SPI_Receive_DMA(&FPGA_SPI, (uint8_t*) raw, 18);
+	HAL_SPI_Receive_DMA(&FPGA_SPI, raw, 36);
 	return true;
 }

+static int64_t assembleSampleResultValue(uint8_t *raw) {
+	return sign_extend_64(
+			(uint16_t) raw[0] << 8 | raw[1] | (uint32_t) raw[2] << 24
+					| (uint32_t) raw[3] << 16 | (uint64_t) raw[4] << 40
+					| (uint64_t) raw[5] << 32, 48);
+}
+
 extern "C" {
 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) {
 	FPGA::SamplingResult result;
 	High(CS);
 	// Assemble data from words
-	result.P1I = sign_extend_64(
-			(uint64_t) raw[17] << 32 | (uint32_t) raw[16] << 16 | raw[15], 48);
-	result.P1Q = sign_extend_64(
-			(uint64_t) raw[14] << 32 | (uint32_t) raw[13] << 16 | raw[12], 48);
-	result.P2I = sign_extend_64(
-			(uint64_t) raw[11] << 32 | (uint32_t) raw[10] << 16 | raw[9], 48);
-	result.P2Q = sign_extend_64(
-			(uint64_t) raw[8] << 32 | (uint32_t) raw[7] << 16 | raw[6], 48);
-	result.RefI = sign_extend_64(
-			(uint64_t) raw[5] << 32 | (uint32_t) raw[4] << 16 | raw[3], 48);
-	result.RefQ = sign_extend_64(
-			(uint64_t) raw[2] << 32 | (uint32_t) raw[1] << 16 | raw[0], 48);
+	result.P1I = assembleSampleResultValue(&raw[30]);
+	result.P1Q = assembleSampleResultValue(&raw[24]);
+	result.P2I = assembleSampleResultValue(&raw[18]);
+	result.P2Q = assembleSampleResultValue(&raw[12]);
+	result.RefI = assembleSampleResultValue(&raw[6]);
+	result.RefQ = assembleSampleResultValue(&raw[0]);
 	if (callback) {
 		callback(result);
 	}
@ -293,36 +321,45 @@ void FPGA::SetMode(Mode mode) {
 }

 uint16_t FPGA::GetStatus() {
-	uint16_t cmd = 0x4000;
-	uint16_t status;
+	uint8_t cmd[2] = {0x40, 0x00};
+	uint8_t status[2];
 	Low(CS);
-	HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) &cmd, (uint8_t*) &status, 1,
+	HAL_SPI_TransmitReceive(&FPGA_SPI, (uint8_t*) &cmd, (uint8_t*) &status, 2,
 			100);
 	High(CS);
-	return status;
+	return (uint16_t) status[0] << 8 | status[1];
 }

 FPGA::ADCLimits FPGA::GetADCLimits() {
 	uint16_t cmd = 0xE000;
+	SwitchBytes(cmd);
 	Low(CS);
-	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 1, 100);
+	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 2, 100);
 	ADCLimits limits;
-	HAL_SPI_Receive(&FPGA_SPI, (uint8_t*) &limits, 6, 100);
+	HAL_SPI_Receive(&FPGA_SPI, (uint8_t*) &limits, 12, 100);
 	High(CS);
+	SwitchBytes(limits.P1max);
+	SwitchBytes(limits.P1min);
+	SwitchBytes(limits.P2max);
+	SwitchBytes(limits.P2min);
+	SwitchBytes(limits.Rmax);
+	SwitchBytes(limits.Rmin);
 	return limits;
 }

 void FPGA::ResetADCLimits() {
 	uint16_t cmd = 0x6000;
+	SwitchBytes(cmd);
 	Low(CS);
-	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 1, 100);
+	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 2, 100);
 	High(CS);
 }

 void FPGA::ResumeHaltedSweep() {
 	uint16_t cmd = 0x2000;
+	SwitchBytes(cmd);
 	Low(CS);
-	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 1, 100);
+	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) &cmd, 2, 100);
 	High(CS);
 }

--- a/Software/VNA_embedded/Application/Drivers/Flash.cpp
+++ b/Software/VNA_embedded/Application/Drivers/Flash.cpp
@ -1,5 +1,13 @@
 #include "Flash.hpp"

+#include "FreeRTOS.h"
+#include "task.h"
+#include <cstring>
+
+#define LOG_LEVEL	LOG_LEVEL_INFO
+#define LOG_MODULE	"Flash"
+#include "Log.h"
+
 bool Flash::isPresent() {
 	CS(false);
 	// read JEDEC ID
@ -24,16 +32,18 @@ void Flash::read(uint32_t address, uint16_t length, void *dest) {
 bool Flash::write(uint32_t address, uint16_t length, uint8_t *src) {
 	if((address & 0xFF) != 0 || length%256 != 0) {
 		// only writes to complete pages allowed
+		LOG_ERR("Invalid write address/size: %lu/%u", address, length);
 		return false;
 	}
 	address &= 0x00FFFFFF;
+	LOG_DEBUG("Writing %u bytes to address %lu", length, address);
 	while(length > 0) {
 		EnableWrite();
 		CS(false);
 		uint8_t cmd[4] = {
 			0x02,
-			((uint8_t) address >> 16) & 0xFF,
-			((uint8_t) address >> 8) & 0xFF,
+			(uint8_t) (address >> 16) & 0xFF,
+			(uint8_t) (address >> 8) & 0xFF,
 			(uint8_t) (address & 0xFF),
 		};
 		// issue read command
@ -41,9 +51,18 @@ bool Flash::write(uint32_t address, uint16_t length, uint8_t *src) {
 		// write data
 		HAL_SPI_Transmit(spi, src, 256, 1000);
 		CS(true);
-		if(!WaitBusy(5)) {
+		if(!WaitBusy(20)) {
+			LOG_ERR("Write timed out");
 			return false;
 		}
+		// Verify
+		uint8_t buf[256];
+		read(address, 256, buf);
+		if(memcmp(src, buf, 256)) {
+			LOG_ERR("Verification error");
+			return false;
+		}
+		address += 256;
 		length -= 256;
 		src += 256;
 	}
@ -59,6 +78,7 @@ void Flash::EnableWrite() {
 }

 bool Flash::eraseChip() {
+	LOG_INFO("Erasing...");
 	EnableWrite();
 	CS(false);
 	// enable write latch
@ -73,8 +93,8 @@ void Flash::initiateRead(uint32_t address) {
 	CS(false);
 	uint8_t cmd[4] = {
 		0x03,
-		((uint8_t) address >> 16) & 0xFF,
-		((uint8_t) address >> 8) & 0xFF,
+		(uint8_t) (address >> 16) & 0xFF,
+		(uint8_t) (address >> 8) & 0xFF,
 		(uint8_t) (address & 0xFF),
 	};
 	// issue read command
@ -86,15 +106,17 @@ bool Flash::WaitBusy(uint32_t timeout) {
 	CS(false);
 	uint8_t readStatus1 = 0x05;
 	HAL_SPI_Transmit(spi, &readStatus1, 1, 100);
-	while(HAL_GetTick() - starttime > timeout) {
+	do {
+		vTaskDelay(1);
 		uint8_t status1;
 		HAL_SPI_Receive(spi, &status1, 1, 100);
-		if(!(status1 & 0x01)) {
+		if (!(status1 & 0x01)) {
 			CS(true);
 			return true;
 		}
-	}
+	} while (HAL_GetTick() - starttime < timeout);
 	// timed out
 	CS(true);
+	LOG_ERR("Timeout occured");
 	return false;
 }
--- a/Software/VNA_embedded/Application/Drivers/Log.h
+++ b/Software/VNA_embedded/Application/Drivers/Log.h
@ -6,7 +6,7 @@ extern "C" {

 //#define LOG_BLOCKING

-#define LOG_USART			2
+#define LOG_USART			3
 #define LOG_SENDBUF_LENGTH	1024
 //#define LOG_USE_MUTEX

--- a/Software/VNA_embedded/Application/Drivers/Si5351C.cpp
+++ b/Software/VNA_embedded/Application/Drivers/Si5351C.cpp
@ -2,7 +2,7 @@

 #include <cmath>

-#define LOG_LEVEL	LOG_LEVEL_DEBUG
+#define LOG_LEVEL	LOG_LEVEL_INFO
 #define LOG_MODULE	"SI5351"
 #include "Log.h"

--- a/Software/VNA_embedded/Application/Drivers/max2871.cpp
+++ b/Software/VNA_embedded/Application/Drivers/max2871.cpp
@ -296,12 +296,14 @@ void MAX2871::UpdateFrequency() {
 }

 void MAX2871::Write(uint8_t reg, uint32_t val) {
-	uint16_t data[2];
+	uint8_t data[4];
 	// split value into two 16 bit words
-	data[0] = val >> 16;
-	data[1] = (val & 0xFFF8) | reg;
+	data[0] = (val >> 24) & 0xFF;
+	data[1] = (val >> 16) & 0xFF;
+	data[2] = (val >> 8) & 0xFF;
+	data[3] = (val & 0xF8) | reg;
 	Delay::us(1);
-	HAL_SPI_Transmit(hspi, (uint8_t*) data, 2, 20);
+	HAL_SPI_Transmit(hspi, (uint8_t*) data, 4, 20);
 	LE->BSRR = LEpin;
 	Delay::us(1);
 	LE->BSRR = LEpin << 16;
@ -309,15 +311,16 @@ void MAX2871::Write(uint8_t reg, uint32_t val) {

 // Assumes that the MUX pin is already configured as "Read register 6" and connected to MISO
 uint32_t MAX2871::Read() {
-	uint16_t transmit[2] = {0x0000, 0x0006};
-	HAL_SPI_Transmit(hspi, (uint8_t*) transmit, 2, 20);
+	uint8_t transmit[4] = {0x00, 0x00, 0x00, 0x06};
+	HAL_SPI_Transmit(hspi, (uint8_t*) transmit, 4, 20);
 	LE->BSRR = LEpin;
 	memset(transmit, 0, sizeof(transmit));
-	uint16_t recv[2];
-	HAL_SPI_TransmitReceive(hspi, (uint8_t*) transmit, (uint8_t*) recv, 2, 20);
+	uint8_t recv[4];
+	HAL_SPI_TransmitReceive(hspi, (uint8_t*) transmit, (uint8_t*) recv, 4, 20);
 	LE->BSRR = LEpin << 16;
 	// assemble readback result
-	uint32_t result = ((uint32_t) recv[0] << 16) | (recv[1] & 0xFFFF);
+	uint32_t result = ((uint32_t) recv[0] << 24) | ((uint32_t) recv[1] << 16
+	) | ((uint32_t) recv[2] << 8) | (recv[3] & 0xFF);
 	result <<= 2;
 	LOG_DEBUG("Readback: 0x%08x", result);
 	return result;
--- a/Software/VNA_embedded/Application/Firmware.cpp
+++ b/Software/VNA_embedded/Application/Firmware.cpp
@ -42,6 +42,7 @@ Firmware::Info Firmware::GetFlashContentInfo(Flash *f) {
 		}
 		f->read(h.FPGA_start + checked_size, read_size, buf);
 		crc = Protocol::CRC32(crc, buf, read_size);
+		checked_size += read_size;
 	}
 	if (crc != h.crc) {
 		LOG_ERR("CRC mismatch, invalid FPGA bitstream/CPU firmware");
@ -54,12 +55,13 @@ Firmware::Info Firmware::GetFlashContentInfo(Flash *f) {
 		if (h.CPU_size - checked_size < read_size) {
 			read_size = h.CPU_size - checked_size;
 		}
-		f->read(h.FPGA_start + checked_size, read_size, buf);
+		f->read(h.CPU_start + checked_size, read_size, buf);
 		if(memcmp(buf, (void*)(0x8000000+checked_size), read_size)) {
 			LOG_WARN("Difference to CPU firmware in external FLASH detected, update required");
 			ret.CPU_need_update = true;
 			break;
 		}
+		checked_size += read_size;
 	}
 	ret.valid = true;
 	ret.FPGA_bitstream_address = h.FPGA_start;
@ -100,9 +102,12 @@ static void copy_flash(uint32_t size, SPI_TypeDef *spi) {
 	 * content into the internal MCU flash */
 	uint32_t written = 0;

+	// Enable FIFO notifications for 8 bit
+	SET_BIT(spi->CR2, SPI_RXFIFO_THRESHOLD);
+
 	/* Enable FLASH write */
 	FLASH->CR |= FLASH_CR_PG;
-	uint32_t to = 0x80000000;
+	uint32_t *to = (uint32_t*) 0x8000000;
 	while (written < size) {
 		uint8_t buf[8];
 		// Get 64bit from external flash
@ -110,14 +115,15 @@ static void copy_flash(uint32_t size, SPI_TypeDef *spi) {
 			// wait for SPI ready to transmit dummy data
 			while(!(spi->SR & SPI_FLAG_TXE));
 			// send dummy byte
-			*(__IO uint8_t *)spi->DR = 0x00;
+			*(__IO uint8_t *)&spi->DR = 0x00;
 			// wait for received byte to be ready
 			while(!(spi->SR & SPI_FLAG_RXNE));
 			// get received byte
-			buf[i] = *(__IO uint8_t *)spi->DR;
+			buf[i] = *(__IO uint8_t *)&spi->DR;
 		}
 		// program received data into flash
 		*(__IO uint32_t*) to++ = *(uint32_t*)&buf[0];
+		__ISB();
 		*(__IO uint32_t*) to++ = *(uint32_t*)&buf[4];
 		/* Wait for it to finish */
 		while (FLASH->SR & FLASH_SR_BSY)
@ -152,8 +158,7 @@ static void copy_flash(uint32_t size, SPI_TypeDef *spi) {
 	}
 }

-void Firmware::PerformUpdate(Flash *f) {
-	auto info = GetFlashContentInfo(f);
+void Firmware::PerformUpdate(Flash *f, Info info) {
 	if(!info.valid) {
 		LOG_ERR("Invalid firmware data, not performing update");
 		return;
--- a/Software/VNA_embedded/Application/Firmware.hpp
+++ b/Software/VNA_embedded/Application/Firmware.hpp
@ -22,7 +22,7 @@ using Info = struct info {
 };

 Info GetFlashContentInfo(Flash *f);
-void PerformUpdate(Flash *f);
+void PerformUpdate(Flash *f, Info info);

 }

--- a/Software/VNA_embedded/Application/Led.cpp
+++ b/Software/VNA_embedded/Application/Led.cpp
@ -0,0 +1,131 @@
+#include "Led.hpp"
+
+#include "stm.hpp"
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if HW_REVISION == 'B'
+
+#define LED_TASK_STACK		128
+
+extern TIM_HandleTypeDef htim2;
+
+enum class Mode {
+	Off,
+	On,
+	Blink,
+	Pulsating,
+	Error,
+};
+
+static Mode mode;
+static uint8_t led_statecnt;
+static int8_t led_ncnt;
+static xTaskHandle task;
+static StaticTask_t xTask;
+static StackType_t xStack[LED_TASK_STACK];
+static uint8_t err_cnt;
+
+static void led_set_percentage(uint8_t val) {
+	uint16_t compare = val * val / 100;
+	TIM2->CCR1 = compare;
+}
+
+static void led_task(void* unused) {
+	UNUSED(unused);
+	while (1) {
+		if (led_statecnt < 199) {
+			led_statecnt++;
+		} else {
+			led_statecnt = 0;
+		}
+		switch (mode) {
+		case Mode::Off:
+			led_set_percentage(0);
+			vTaskSuspend(NULL);
+			break;
+		case Mode::On:
+			led_set_percentage(100);
+			vTaskSuspend(NULL);
+			break;
+		case Mode::Error:
+			if (led_statecnt == 0) {
+				err_cnt++;
+				if (err_cnt > led_ncnt) {
+					// reached number of blinks + 1
+					err_cnt = 0;
+				}
+			}
+			if (err_cnt >= led_ncnt) {
+				break;
+			}
+			// fall through
+			/* no break */
+		case Mode::Blink:
+			if(led_statecnt < 100) {
+				led_set_percentage(100);
+			} else {
+				led_set_percentage(0);
+			}
+			break;
+		case Mode::Pulsating:
+			if (led_statecnt < 100) {
+				led_set_percentage(led_statecnt);
+			} else {
+				led_set_percentage(200 - led_statecnt);
+			}
+			break;
+		}
+		vTaskDelay(5);
+	}
+}
+#endif
+
+void LED::Init() {
+#if HW_REVISION == 'B'
+	led_ncnt = 0;
+	mode = Mode::Off;
+	HAL_TIM_Base_Start(&htim2);
+	HAL_TIM_PWM_Start(&htim2, TIM_CHANNEL_1);
+
+	task = xTaskCreateStatic(led_task, "LED",
+	LED_TASK_STACK, NULL, 6, xStack, &xTask);
+	vTaskSuspend(task);
+#endif
+}
+
+void LED::Pulsating() {
+#if HW_REVISION == 'B'
+	if(led_ncnt) {
+		return;
+	}
+	vTaskSuspend(task);
+	mode = Mode::Pulsating;
+	vTaskResume(task);
+#endif
+}
+
+void LED::Off() {
+#if HW_REVISION == 'B'
+	if(led_ncnt) {
+		return;
+	}
+	vTaskSuspend(task);
+	mode = Mode::Off;
+	vTaskResume(task);
+#endif
+}
+
+void LED::Error(uint8_t code) {
+#if HW_REVISION == 'B'
+	if(led_ncnt) {
+		return;
+	}
+	vTaskSuspend(task);
+	mode = Mode::Error;
+	led_statecnt = 0;
+	err_cnt = 0;
+	led_ncnt = code;
+	vTaskResume(task);
+#endif
+}
--- a/Software/VNA_embedded/Application/Led.hpp
+++ b/Software/VNA_embedded/Application/Led.hpp
@ -0,0 +1,12 @@
+#pragma once
+
+#include <cstdint>
+
+namespace LED {
+
+void Init();
+void Pulsating();
+void Off();
+void Error(uint8_t code);
+
+}
--- a/Software/VNA_embedded/Application/VNA.cpp
+++ b/Software/VNA_embedded/Application/VNA.cpp
@ -568,3 +568,16 @@ bool VNA::ConfigureGenerator(Protocol::GeneratorSettings g) {
 	m.attenuator = attval;
 	return ConfigureManual(m, nullptr);
 }
+
+void VNA::SetIdle() {
+	FPGA::AbortSweep();
+	FPGA::SetMode(FPGA::Mode::FPGA);
+	FPGA::Enable(FPGA::Periphery::SourceChip, false);
+	FPGA::Enable(FPGA::Periphery::SourceRF, false);
+	FPGA::Enable(FPGA::Periphery::LO1Chip, false);
+	FPGA::Enable(FPGA::Periphery::LO1RF, false);
+	FPGA::Enable(FPGA::Periphery::Amplifier, false);
+	FPGA::Enable(FPGA::Periphery::Port1Mixer, false);
+	FPGA::Enable(FPGA::Periphery::Port2Mixer, false);
+	FPGA::Enable(FPGA::Periphery::RefMixer, false);
+}
--- a/Software/VNA_embedded/Application/VNA.hpp
+++ b/Software/VNA_embedded/Application/VNA.hpp
@ -13,6 +13,7 @@ bool Init();
 bool ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb);
 bool ConfigureManual(Protocol::ManualControl m, StatusCallback cb);
 bool ConfigureGenerator(Protocol::GeneratorSettings g);
+void SetIdle();

 // Only call the following function when the sweep is inactive
 bool GetTemps(uint8_t *source, uint8_t *lo);
--- a/Software/VNA_embedded/Application/VNA_HAL.hpp
+++ b/Software/VNA_embedded/Application/VNA_HAL.hpp
@ -11,8 +11,8 @@ extern SPI_HandleTypeDef hspi1;
 namespace VNAHAL {

 static Si5351C Si5351 = Si5351C(&hi2c2, 26000000);
-static MAX2871 Source = MAX2871(&hspi1, FPGA_CS_GPIO_Port, FPGA_CS_Pin, nullptr, 0, nullptr, 0, nullptr, 0, GPIOB, GPIO_PIN_4);
-static MAX2871 LO1 = MAX2871(&hspi1, FPGA_CS_GPIO_Port, FPGA_CS_Pin, nullptr, 0, nullptr, 0, nullptr, 0, GPIOB, GPIO_PIN_4);
+static MAX2871 Source = MAX2871(&hspi1, FPGA_CS_GPIO_Port, FPGA_CS_Pin, nullptr, 0, nullptr, 0, nullptr, 0, GPIOA, GPIO_PIN_6);
+static MAX2871 LO1 = MAX2871(&hspi1, FPGA_CS_GPIO_Port, FPGA_CS_Pin, nullptr, 0, nullptr, 0, nullptr, 0, GPIOA, GPIO_PIN_6);

 // Mapping of the Si5351 channels to PLLs/Mixers
 namespace SiChannel {
@ -22,7 +22,7 @@ namespace SiChannel {
 		Port2LO2 = 4,
 		RefLO2 = 1,
 		Port1LO2 = 2,
-		LowbandSource = 1,
+		LowbandSource = 0,
 		ReferenceOut = 6,
 		FPGA = 7,
 	};
--- a/Software/VNA_embedded/Inc/FreeRTOSConfig.h
+++ b/Software/VNA_embedded/Inc/FreeRTOSConfig.h
@ -61,7 +61,7 @@
 #define configTICK_RATE_HZ                       ((TickType_t)1000)
 #define configMAX_PRIORITIES                     ( 7 )
 #define configMINIMAL_STACK_SIZE                 ((uint16_t)128)
-#define configTOTAL_HEAP_SIZE                    ((size_t)4096)
+#define configTOTAL_HEAP_SIZE                    ((size_t)2048)
 #define configMAX_TASK_NAME_LEN                  ( 16 )
 #define configUSE_16_BIT_TICKS                   0
 #define configUSE_MUTEXES                        1
@ -78,7 +78,7 @@ to exclude the API function. */
 #define INCLUDE_uxTaskPriorityGet           0
 #define INCLUDE_vTaskDelete                 0
 #define INCLUDE_vTaskCleanUpResources       0
-#define INCLUDE_vTaskSuspend                0
+#define INCLUDE_vTaskSuspend                1
 #define INCLUDE_vTaskDelayUntil             0
 #define INCLUDE_vTaskDelay                  1
 #define INCLUDE_xTaskGetSchedulerState      1
--- a/Software/VNA_embedded/Inc/main.h
+++ b/Software/VNA_embedded/Inc/main.h
@ -61,6 +61,8 @@ extern "C" {

 /* USER CODE END EM */

+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+
 /* Exported functions prototypes ---------------------------------------------*/
 void Error_Handler(void);

@ -73,10 +75,10 @@ void Error_Handler(void);
 #define FPGA_INIT_B_GPIO_Port GPIOF
 #define FPGA_AUX1_Pin GPIO_PIN_1
 #define FPGA_AUX1_GPIO_Port GPIOA
-#define FPGA_AUX2_Pin GPIO_PIN_2
-#define FPGA_AUX2_GPIO_Port GPIOA
-#define FPGA_AUX3_Pin GPIO_PIN_3
+#define FPGA_AUX3_Pin GPIO_PIN_2
 #define FPGA_AUX3_GPIO_Port GPIOA
+#define FPGA_AUX2_Pin GPIO_PIN_3
+#define FPGA_AUX2_GPIO_Port GPIOA
 #define FPGA_CS_Pin GPIO_PIN_4
 #define FPGA_CS_GPIO_Port GPIOA
 #define FLASH_CS_Pin GPIO_PIN_0
@ -87,8 +89,6 @@ void Error_Handler(void);
 #define FPGA_PROGRAM_B_GPIO_Port GPIOB
 #define EN_6V_Pin GPIO_PIN_12
 #define EN_6V_GPIO_Port GPIOB
-#define LED1_Pin GPIO_PIN_15
-#define LED1_GPIO_Port GPIOA
 #define FPGA_RESET_Pin GPIO_PIN_5
 #define FPGA_RESET_GPIO_Port GPIOB
 #define FPGA_DONE_Pin GPIO_PIN_9
--- a/Software/VNA_embedded/Inc/stm32g4xx_it.h
+++ b/Software/VNA_embedded/Inc/stm32g4xx_it.h
@ -55,6 +55,8 @@ void UsageFault_Handler(void);
 void DebugMon_Handler(void);
 void DMA1_Channel1_IRQHandler(void);
 void DMA1_Channel2_IRQHandler(void);
+void DMA1_Channel3_IRQHandler(void);
+void DMA1_Channel4_IRQHandler(void);
 void USB_HP_IRQHandler(void);
 void USB_LP_IRQHandler(void);
 void TIM1_TRG_COM_TIM17_IRQHandler(void);
--- a/Software/VNA_embedded/Inc/usbpd_devices_conf.h
+++ b/Software/VNA_embedded/Inc/usbpd_devices_conf.h
@ -90,10 +90,10 @@
      Definitions for timer service feature
 -------------------------------------------------------------------------------*/

-#define TIMX                           TIM2
-#define TIMX_CLK_ENABLE                LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2)
-#define TIMX_CLK_DISABLE               LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM2)
-#define TIMX_IRQ                       TIM2_IRQn
+#define TIMX                           TIM3
+#define TIMX_CLK_ENABLE                LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM3)
+#define TIMX_CLK_DISABLE               LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_TIM3)
+#define TIMX_IRQ                       TIM3_IRQn
 #define TIMX_CHANNEL_CH1               LL_TIM_CHANNEL_CH1
 #define TIMX_CHANNEL_CH2               LL_TIM_CHANNEL_CH2
 #define TIMX_CHANNEL_CH3               LL_TIM_CHANNEL_CH3
--- a/Software/VNA_embedded/New_configuration.cfg
+++ b/Software/VNA_embedded/New_configuration.cfg
@ -9,7 +9,7 @@ set WORKAREASIZE 0x8000

 transport select "hla_swd"

-set CHIPNAME STM32L432KCUx
+set CHIPNAME STM32G432CBUx
 set BOARDNAME VNA_embedded

 # CHIPNAMES state
@ -33,4 +33,4 @@ set CONNECT_UNDER_RESET 1



-source [find target/stm32l4x.cfg]
+source [find target/stm32g4x.cfg]
--- a/Software/VNA_embedded/Src/main.c
+++ b/Software/VNA_embedded/Src/main.c
@ -48,15 +48,18 @@ I2C_HandleTypeDef hi2c2;

 SPI_HandleTypeDef hspi1;
 SPI_HandleTypeDef hspi2;
+DMA_HandleTypeDef hdma_spi1_rx;
+DMA_HandleTypeDef hdma_spi1_tx;

 TIM_HandleTypeDef htim1;
+TIM_HandleTypeDef htim2;

 UART_HandleTypeDef huart3;

 PCD_HandleTypeDef hpcd_USB_FS;

 osThreadId defaultTaskHandle;
-uint32_t defaultTaskBuffer[ 4096 ];
+uint32_t defaultTaskBuffer[ 1024 ];
 osStaticThreadDef_t defaultTaskControlBlock;
 /* USER CODE BEGIN PV */

@ -73,6 +76,7 @@ static void MX_UCPD1_Init(void);
 static void MX_USART3_UART_Init(void);
 static void MX_USB_PCD_Init(void);
 static void MX_TIM1_Init(void);
+static void MX_TIM2_Init(void);
 void StartDefaultTask(void const * argument);

 /* USER CODE BEGIN PFP */
@ -121,6 +125,7 @@ int main(void)
  MX_USART3_UART_Init();
  MX_USB_PCD_Init();
  MX_TIM1_Init();
+  MX_TIM2_Init();
  /* USER CODE BEGIN 2 */

  /* USER CODE END 2 */
@ -145,7 +150,7 @@ int main(void)

  /* Create the thread(s) */
  /* definition and creation of defaultTask */
-  osThreadStaticDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 4096, defaultTaskBuffer, &defaultTaskControlBlock);
+  osThreadStaticDef(defaultTask, StartDefaultTask, osPriorityNormal, 0, 1024, defaultTaskBuffer, &defaultTaskControlBlock);
  defaultTaskHandle = osThreadCreate(osThread(defaultTask), NULL);

  /* USER CODE BEGIN RTOS_THREADS */
@ -221,7 +226,6 @@ void SystemClock_Config(void)
  {
    Error_Handler();
  }
-  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1);
 }

 /**
@ -289,11 +293,11 @@ static void MX_SPI1_Init(void)
  hspi1.Instance = SPI1;
  hspi1.Init.Mode = SPI_MODE_MASTER;
  hspi1.Init.Direction = SPI_DIRECTION_2LINES;
-  hspi1.Init.DataSize = SPI_DATASIZE_4BIT;
+  hspi1.Init.DataSize = SPI_DATASIZE_8BIT;
  hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
  hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
  hspi1.Init.NSS = SPI_NSS_SOFT;
-  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
+  hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
  hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
  hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
  hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@ -329,11 +333,11 @@ static void MX_SPI2_Init(void)
  hspi2.Instance = SPI2;
  hspi2.Init.Mode = SPI_MODE_MASTER;
  hspi2.Init.Direction = SPI_DIRECTION_2LINES;
-  hspi2.Init.DataSize = SPI_DATASIZE_4BIT;
+  hspi2.Init.DataSize = SPI_DATASIZE_8BIT;
  hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
  hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
  hspi2.Init.NSS = SPI_NSS_SOFT;
-  hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_64;
+  hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16;
  hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
  hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
  hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@ -404,6 +408,65 @@ static void MX_TIM1_Init(void)

 }

+/**
+  * @brief TIM2 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_OC_InitTypeDef sConfigOC = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 143;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 99;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigOC.OCMode = TIM_OCMODE_PWM2;
+  sConfigOC.Pulse = 0;
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+  if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+  HAL_TIM_MspPostInit(&htim2);
+
+}
+
 /**
  * @brief UCPD1 Initialization Function
  * @param None
@ -485,7 +548,7 @@ static void MX_USART3_UART_Init(void)
  /* USER CODE END USART3_Init 1 */
  huart3.Instance = USART3;
  huart3.Init.BaudRate = 115200;
-  huart3.Init.WordLength = UART_WORDLENGTH_7B;
+  huart3.Init.WordLength = UART_WORDLENGTH_8B;
  huart3.Init.StopBits = UART_STOPBITS_1;
  huart3.Init.Parity = UART_PARITY_NONE;
  huart3.Init.Mode = UART_MODE_TX_RX;
@ -494,7 +557,7 @@ static void MX_USART3_UART_Init(void)
  huart3.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
  huart3.Init.ClockPrescaler = UART_PRESCALER_DIV1;
  huart3.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
-  if (HAL_HalfDuplex_Init(&huart3) != HAL_OK)
+  if (HAL_UART_Init(&huart3) != HAL_OK)
  {
    Error_Handler();
  }
@ -565,6 +628,12 @@ static void MX_DMA_Init(void)
  /* DMA1_Channel2_IRQn interrupt configuration */
  NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
  NVIC_EnableIRQ(DMA1_Channel2_IRQn);
+  /* DMA1_Channel3_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
+  /* DMA1_Channel4_IRQn interrupt configuration */
+  HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 5, 0);
+  HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);

 }

@ -579,40 +648,30 @@ static void MX_GPIO_Init(void)

  /* GPIO Ports Clock Enable */
  __HAL_RCC_GPIOF_CLK_ENABLE();
-  __HAL_RCC_GPIOG_CLK_ENABLE();
  __HAL_RCC_GPIOA_CLK_ENABLE();
  __HAL_RCC_GPIOC_CLK_ENABLE();
  __HAL_RCC_GPIOB_CLK_ENABLE();

  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(FPGA_INIT_B_GPIO_Port, FPGA_INIT_B_Pin, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(GPIOA, FPGA_AUX1_Pin|FPGA_AUX3_Pin|FPGA_AUX2_Pin, GPIO_PIN_RESET);

  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOA, FPGA_AUX1_Pin|FPGA_AUX2_Pin|FPGA_AUX3_Pin|FPGA_CS_Pin 
-                          |LED1_Pin, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(FPGA_CS_GPIO_Port, FPGA_CS_Pin, GPIO_PIN_SET);

  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOB, FLASH_CS_Pin|FPGA_PROGRAM_B_Pin|EN_6V_Pin|FPGA_RESET_Pin, GPIO_PIN_RESET);
+  HAL_GPIO_WritePin(FLASH_CS_GPIO_Port, FLASH_CS_Pin, GPIO_PIN_SET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOB, FPGA_PROGRAM_B_Pin|EN_6V_Pin|FPGA_RESET_Pin, GPIO_PIN_RESET);

  /*Configure GPIO pin : FPGA_INIT_B_Pin */
  GPIO_InitStruct.Pin = FPGA_INIT_B_Pin;
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+  GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
  HAL_GPIO_Init(FPGA_INIT_B_GPIO_Port, &GPIO_InitStruct);

-  /*Configure GPIO pin : PG10 */
-  GPIO_InitStruct.Pin = GPIO_PIN_10;
-  GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
-  HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
-
-  /*Configure GPIO pins : FPGA_AUX1_Pin FPGA_AUX2_Pin FPGA_AUX3_Pin FPGA_CS_Pin 
-                           LED1_Pin */
-  GPIO_InitStruct.Pin = FPGA_AUX1_Pin|FPGA_AUX2_Pin|FPGA_AUX3_Pin|FPGA_CS_Pin 
-                          |LED1_Pin;
+  /*Configure GPIO pins : FPGA_AUX1_Pin FPGA_AUX3_Pin FPGA_AUX2_Pin FPGA_CS_Pin */
+  GPIO_InitStruct.Pin = FPGA_AUX1_Pin|FPGA_AUX3_Pin|FPGA_AUX2_Pin|FPGA_CS_Pin;
  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
  GPIO_InitStruct.Pull = GPIO_NOPULL;
  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
--- a/Software/VNA_embedded/Src/stm32g4xx_hal_msp.c
+++ b/Software/VNA_embedded/Src/stm32g4xx_hal_msp.c
@ -24,6 +24,9 @@
 /* USER CODE BEGIN Includes */

 /* USER CODE END Includes */
+extern DMA_HandleTypeDef hdma_spi1_rx;
+
+extern DMA_HandleTypeDef hdma_spi1_tx;

 /* Private typedef -----------------------------------------------------------*/
 /* USER CODE BEGIN TD */
@ -58,7 +61,9 @@
 /* USER CODE BEGIN 0 */

 /* USER CODE END 0 */
-/**
+                        
+void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
+                    /**
  * Initializes the Global MSP.
  */
 void HAL_MspInit(void)
@ -184,6 +189,41 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
    GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);

+    /* SPI1 DMA Init */
+    /* SPI1_RX Init */
+    hdma_spi1_rx.Instance = DMA1_Channel3;
+    hdma_spi1_rx.Init.Request = DMA_REQUEST_SPI1_RX;
+    hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+    hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_rx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_rx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hspi,hdmarx,hdma_spi1_rx);
+
+    /* SPI1_TX Init */
+    hdma_spi1_tx.Instance = DMA1_Channel4;
+    hdma_spi1_tx.Init.Request = DMA_REQUEST_SPI1_TX;
+    hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+    hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+    hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE;
+    hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
+    hdma_spi1_tx.Init.Mode = DMA_NORMAL;
+    hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW;
+    if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    __HAL_LINKDMA(hspi,hdmatx,hdma_spi1_tx);
+
  /* USER CODE BEGIN SPI1_MspInit 1 */

  /* USER CODE END SPI1_MspInit 1 */
@ -238,6 +278,9 @@ void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi)
    */
    HAL_GPIO_DeInit(GPIOA, GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7);

+    /* SPI1 DMA DeInit */
+    HAL_DMA_DeInit(hspi->hdmarx);
+    HAL_DMA_DeInit(hspi->hdmatx);
  /* USER CODE BEGIN SPI1_MspDeInit 1 */

  /* USER CODE END SPI1_MspDeInit 1 */
@ -285,9 +328,46 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)

  /* USER CODE END TIM1_MspInit 1 */
  }
+  else if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }

 }

+void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(htim->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspPostInit 0 */
+
+  /* USER CODE END TIM2_MspPostInit 0 */
+  
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM2 GPIO Configuration    
+    PA15     ------> TIM2_CH1 
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_15;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+  /* USER CODE BEGIN TIM2_MspPostInit 1 */
+
+  /* USER CODE END TIM2_MspPostInit 1 */
+  }
+
+}
 /**
 * @brief TIM_Base MSP De-Initialization
 * This function freeze the hardware resources used in this example
@ -310,6 +390,17 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)

  /* USER CODE END TIM1_MspDeInit 1 */
  }
+  else if(htim_base->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }

 }

@ -330,12 +421,21 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
    /* Peripheral clock enable */
    __HAL_RCC_USART3_CLK_ENABLE();
  
+    __HAL_RCC_GPIOB_CLK_ENABLE();
    __HAL_RCC_GPIOC_CLK_ENABLE();
    /**USART3 GPIO Configuration    
+    PB11     ------> USART3_RX
    PC10     ------> USART3_TX 
    */
+    GPIO_InitStruct.Pin = GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
    GPIO_InitStruct.Pin = GPIO_PIN_10;
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
    GPIO_InitStruct.Pull = GPIO_NOPULL;
    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
    GPIO_InitStruct.Alternate = GPIO_AF7_USART3;
@ -365,8 +465,11 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
    __HAL_RCC_USART3_CLK_DISABLE();
  
    /**USART3 GPIO Configuration    
+    PB11     ------> USART3_RX
    PC10     ------> USART3_TX 
    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_11);
+
    HAL_GPIO_DeInit(GPIOC, GPIO_PIN_10);

  /* USER CODE BEGIN USART3_MspDeInit 1 */
--- a/Software/VNA_embedded/Src/stm32g4xx_it.c
+++ b/Software/VNA_embedded/Src/stm32g4xx_it.c
@ -57,6 +57,8 @@
 /* USER CODE END 0 */

 /* External variables --------------------------------------------------------*/
+extern DMA_HandleTypeDef hdma_spi1_rx;
+extern DMA_HandleTypeDef hdma_spi1_tx;
 extern TIM_HandleTypeDef htim1;
 extern PCD_HandleTypeDef hpcd_USB_FS;
 extern TIM_HandleTypeDef htim17;
@ -189,6 +191,34 @@ void DMA1_Channel2_IRQHandler(void)
  /* USER CODE END DMA1_Channel2_IRQn 1 */
 }

+/**
+  * @brief This function handles DMA1 channel3 global interrupt.
+  */
+void DMA1_Channel3_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel3_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel3_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi1_rx);
+  /* USER CODE BEGIN DMA1_Channel3_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel3_IRQn 1 */
+}
+
+/**
+  * @brief This function handles DMA1 channel4 global interrupt.
+  */
+void DMA1_Channel4_IRQHandler(void)
+{
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 0 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 0 */
+  HAL_DMA_IRQHandler(&hdma_spi1_tx);
+  /* USER CODE BEGIN DMA1_Channel4_IRQn 1 */
+
+  /* USER CODE END DMA1_Channel4_IRQn 1 */
+}
+
 /**
  * @brief This function handles USB high priority interrupt remap.
  */
--- a/Software/VNA_embedded/VNA_embedded.ioc
+++ b/Software/VNA_embedded/VNA_embedded.ioc
@ -1,7 +1,43 @@
 #MicroXplorer Configuration settings - do not modify
 Dma.Request0=UCPD1_RX
 Dma.Request1=UCPD1_TX
-Dma.RequestsNb=2
+Dma.Request2=SPI1_RX
+Dma.Request3=SPI1_TX
+Dma.RequestsNb=4
+Dma.SPI1_RX.2.Direction=DMA_PERIPH_TO_MEMORY
+Dma.SPI1_RX.2.EventEnable=DISABLE
+Dma.SPI1_RX.2.Instance=DMA1_Channel3
+Dma.SPI1_RX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_RX.2.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_RX.2.Mode=DMA_NORMAL
+Dma.SPI1_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_RX.2.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_RX.2.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_RX.2.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_RX.2.RequestNumber=1
+Dma.SPI1_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_RX.2.SignalID=NONE
+Dma.SPI1_RX.2.SyncEnable=DISABLE
+Dma.SPI1_RX.2.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_RX.2.SyncRequestNumber=1
+Dma.SPI1_RX.2.SyncSignalID=NONE
+Dma.SPI1_TX.3.Direction=DMA_MEMORY_TO_PERIPH
+Dma.SPI1_TX.3.EventEnable=DISABLE
+Dma.SPI1_TX.3.Instance=DMA1_Channel4
+Dma.SPI1_TX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
+Dma.SPI1_TX.3.MemInc=DMA_MINC_ENABLE
+Dma.SPI1_TX.3.Mode=DMA_NORMAL
+Dma.SPI1_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
+Dma.SPI1_TX.3.PeriphInc=DMA_PINC_DISABLE
+Dma.SPI1_TX.3.Polarity=HAL_DMAMUX_REQ_GEN_RISING
+Dma.SPI1_TX.3.Priority=DMA_PRIORITY_LOW
+Dma.SPI1_TX.3.RequestNumber=1
+Dma.SPI1_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
+Dma.SPI1_TX.3.SignalID=NONE
+Dma.SPI1_TX.3.SyncEnable=DISABLE
+Dma.SPI1_TX.3.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT
+Dma.SPI1_TX.3.SyncRequestNumber=1
+Dma.SPI1_TX.3.SyncSignalID=NONE
 Dma.UCPD1_RX.0.Direction=DMA_PERIPH_TO_MEMORY
 Dma.UCPD1_RX.0.EventEnable=DISABLE
 Dma.UCPD1_RX.0.Instance=DMA1_Channel1
@ -40,13 +76,13 @@ FREERTOS.FootprintOK=true
 FREERTOS.INCLUDE_uxTaskPriorityGet=0
 FREERTOS.INCLUDE_vTaskDelete=0
 FREERTOS.INCLUDE_vTaskPrioritySet=0
-FREERTOS.INCLUDE_vTaskSuspend=0
+FREERTOS.INCLUDE_vTaskSuspend=1
 FREERTOS.INCLUDE_xTaskResumeFromISR=0
 FREERTOS.IPParameters=Tasks01,INCLUDE_vTaskDelete,INCLUDE_vTaskPrioritySet,INCLUDE_uxTaskPriorityGet,INCLUDE_xTaskResumeFromISR,INCLUDE_vTaskSuspend,MEMORY_ALLOCATION,configTOTAL_HEAP_SIZE,configENABLE_BACKWARD_COMPATIBILITY,configUSE_MUTEXES,FootprintOK
 FREERTOS.MEMORY_ALLOCATION=2
-FREERTOS.Tasks01=defaultTask,0,4096,StartDefaultTask,Default,NULL,Static,defaultTaskBuffer,defaultTaskControlBlock
+FREERTOS.Tasks01=defaultTask,0,1024,StartDefaultTask,Default,NULL,Static,defaultTaskBuffer,defaultTaskControlBlock
 FREERTOS.configENABLE_BACKWARD_COMPATIBILITY=1
-FREERTOS.configTOTAL_HEAP_SIZE=4096
+FREERTOS.configTOTAL_HEAP_SIZE=2048
 FREERTOS.configUSE_MUTEXES=1
 File.Version=6
 I2C2.IPParameters=Timing
@ -55,9 +91,10 @@ KeepUserPlacement=false
 Mcu.Family=STM32G4
 Mcu.IP0=DMA
 Mcu.IP1=FREERTOS
-Mcu.IP10=USART3
-Mcu.IP11=USB
-Mcu.IP12=USBPD
+Mcu.IP10=UCPD1
+Mcu.IP11=USART3
+Mcu.IP12=USB
+Mcu.IP13=USBPD
 Mcu.IP2=I2C2
 Mcu.IP3=NVIC
 Mcu.IP4=RCC
@ -65,15 +102,15 @@ Mcu.IP5=SPI1
 Mcu.IP6=SPI2
 Mcu.IP7=SYS
 Mcu.IP8=TIM1
-Mcu.IP9=UCPD1
-Mcu.IPNb=13
+Mcu.IP9=TIM2
+Mcu.IPNb=14
 Mcu.Name=STM32G431C(6-8-B)Ux
 Mcu.Package=UFQFPN48
 Mcu.Pin0=PF1-OSC_OUT
-Mcu.Pin1=PG10-NRST
-Mcu.Pin10=PB0
-Mcu.Pin11=PB1
-Mcu.Pin12=PB2
+Mcu.Pin1=PA1
+Mcu.Pin10=PB1
+Mcu.Pin11=PB2
+Mcu.Pin12=PB11
 Mcu.Pin13=PB12
 Mcu.Pin14=PB13
 Mcu.Pin15=PB15
@ -81,7 +118,7 @@ Mcu.Pin16=PA8
 Mcu.Pin17=PA9
 Mcu.Pin18=PA10
 Mcu.Pin19=PA11
-Mcu.Pin2=PA1
+Mcu.Pin2=PA2
 Mcu.Pin20=PA12
 Mcu.Pin21=PA13
 Mcu.Pin22=PA14
@ -92,18 +129,19 @@ Mcu.Pin26=PB5
 Mcu.Pin27=PB6
 Mcu.Pin28=PB9
 Mcu.Pin29=VP_FREERTOS_VS_CMSIS_V1
-Mcu.Pin3=PA2
+Mcu.Pin3=PA3
 Mcu.Pin30=VP_SYS_VS_tim17
 Mcu.Pin31=VP_TIM1_VS_ClockSourceINT
-Mcu.Pin32=VP_USBPD_VS_USBPD1
-Mcu.Pin33=VP_USBPD_VS_usbpd_tim2
-Mcu.Pin4=PA3
-Mcu.Pin5=PA4
-Mcu.Pin6=PA5
-Mcu.Pin7=PA6
-Mcu.Pin8=PA7
-Mcu.Pin9=PC4
-Mcu.PinsNb=34
+Mcu.Pin32=VP_TIM2_VS_ClockSourceINT
+Mcu.Pin33=VP_USBPD_VS_USBPD1
+Mcu.Pin34=VP_USBPD_VS_usbpd_tim3
+Mcu.Pin4=PA4
+Mcu.Pin5=PA5
+Mcu.Pin6=PA6
+Mcu.Pin7=PA7
+Mcu.Pin8=PC4
+Mcu.Pin9=PB0
+Mcu.PinsNb=35
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32G431CBUx
@ -112,6 +150,8 @@ MxDb.Version=DB.5.0.21
 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.DMA1_Channel1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
 NVIC.DMA1_Channel2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
+NVIC.DMA1_Channel3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
+NVIC.DMA1_Channel4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
 NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
@ -146,21 +186,20 @@ PA13.Signal=SYS_JTMS-SWDIO
 PA14.Locked=true
 PA14.Mode=Serial_Wire
 PA14.Signal=SYS_JTCK-SWCLK
-PA15.GPIOParameters=GPIO_Label
-PA15.GPIO_Label=LED1
 PA15.Locked=true
-PA15.Signal=GPIO_Output
+PA15.Signal=S_TIM2_CH1
 PA2.GPIOParameters=GPIO_Label
-PA2.GPIO_Label=FPGA_AUX2
+PA2.GPIO_Label=FPGA_AUX3
 PA2.Locked=true
 PA2.Signal=GPIO_Output
 PA3.GPIOParameters=GPIO_Label
-PA3.GPIO_Label=FPGA_AUX3
+PA3.GPIO_Label=FPGA_AUX2
 PA3.Locked=true
 PA3.Signal=GPIO_Output
-PA4.GPIOParameters=GPIO_Label
+PA4.GPIOParameters=PinState,GPIO_Label
 PA4.GPIO_Label=FPGA_CS
 PA4.Locked=true
+PA4.PinState=GPIO_PIN_SET
 PA4.Signal=GPIO_Output
 PA5.Locked=true
 PA5.Mode=Full_Duplex_Master
@ -177,14 +216,17 @@ PA8.Signal=I2C2_SDA
 PA9.Locked=true
 PA9.Mode=EnableDeadBattery
 PA9.Signal=UCPD1_DBCC1
-PB0.GPIOParameters=GPIO_Label
+PB0.GPIOParameters=PinState,GPIO_Label
 PB0.GPIO_Label=FLASH_CS
 PB0.Locked=true
+PB0.PinState=GPIO_PIN_SET
 PB0.Signal=GPIO_Output
 PB1.GPIOParameters=GPIO_Label
 PB1.GPIO_Label=FPGA_INTR
 PB1.Locked=true
 PB1.Signal=GPXTI1
+PB11.Mode=Asynchronous
+PB11.Signal=USART3_RX
 PB12.GPIOParameters=GPIO_Label
 PB12.GPIO_Label=EN_6V
 PB12.Locked=true
@ -214,7 +256,7 @@ PB9.GPIO_Label=FPGA_DONE
 PB9.Locked=true
 PB9.Signal=GPIO_Input
 PC10.Locked=true
-PC10.Mode=Half_duplex(single_wire_mode)
+PC10.Mode=Asynchronous
 PC10.Signal=USART3_TX
 PC4.Locked=true
 PC4.Mode=I2C
@ -227,14 +269,10 @@ PCC.Seq0=0
 PCC.Series=STM32G4
 PCC.Temperature=25
 PCC.Vdd=3.0
-PF1-OSC_OUT.GPIOParameters=GPIO_Label,GPIO_ModeDefaultOutputPP
+PF1-OSC_OUT.GPIOParameters=GPIO_Label
 PF1-OSC_OUT.GPIO_Label=FPGA_INIT_B
-PF1-OSC_OUT.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
 PF1-OSC_OUT.Locked=true
-PF1-OSC_OUT.Signal=GPIO_Output
-PG10-NRST.Locked=true
-PG10-NRST.Mode=Clock-out
-PG10-NRST.Signal=RCC_MCO
+PF1-OSC_OUT.Signal=GPIO_Input
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
 ProjectManager.BackupPrevious=false
@ -262,7 +300,7 @@ ProjectManager.StackSize=0x400
 ProjectManager.TargetToolchain=SW4STM32
 ProjectManager.ToolChainLocation=
 ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_I2C2_Init-I2C2-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_UCPD1_Init-UCPD1-false-LL-true,8-MX_USART3_UART_Init-USART3-false-HAL-true,9-MX_USB_PCD_Init-USB-false-HAL-true,10-MX_USBPD_Init-USBPD-false-HAL-true
+ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_I2C2_Init-I2C2-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_UCPD1_Init-UCPD1-false-LL-true,8-MX_USART3_UART_Init-USART3-false-HAL-true,9-MX_USB_PCD_Init-USB-false-HAL-true,10-MX_USBPD_Init-USBPD-false-HAL-true,11-MX_TIM1_Init-TIM1-false-HAL-true,12-MX_TIM2_Init-TIM2-false-HAL-true
 RCC.ADC12Freq_Value=144000000
 RCC.AHBFreq_Value=144000000
 RCC.APB1Freq_Value=144000000
@ -310,31 +348,43 @@ RCC.VCOInputFreq_Value=8000000
 RCC.VCOOutputFreq_Value=288000000
 SH.GPXTI1.0=GPIO_EXTI1
 SH.GPXTI1.ConfNb=1
-SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_64
-SPI1.CalculateBaudRate=2.25 MBits/s
+SH.S_TIM2_CH1.0=TIM2_CH1,PWM Generation1 CH1
+SH.S_TIM2_CH1.ConfNb=1
+SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
+SPI1.CalculateBaudRate=9.0 MBits/s
+SPI1.DataSize=SPI_DATASIZE_8BIT
 SPI1.Direction=SPI_DIRECTION_2LINES
-SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
+SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize
 SPI1.Mode=SPI_MODE_MASTER
 SPI1.VirtualType=VM_MASTER
-SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_64
-SPI2.CalculateBaudRate=2.25 MBits/s
+SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16
+SPI2.CalculateBaudRate=9.0 MBits/s
+SPI2.DataSize=SPI_DATASIZE_8BIT
 SPI2.Direction=SPI_DIRECTION_2LINES
-SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler
+SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize
 SPI2.Mode=SPI_MODE_MASTER
 SPI2.VirtualType=VM_MASTER
 TIM1.IPParameters=Prescaler,PeriodNoDither
 TIM1.PeriodNoDither=65535
 TIM1.Prescaler=143
-USART3.IPParameters=VirtualMode-Half_duplex(single_wire_mode)
-USART3.VirtualMode-Half_duplex(single_wire_mode)=VM_ASYNC
+TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
+TIM2.IPParameters=Channel-PWM Generation1 CH1,Prescaler,PeriodNoDither,OCMode_PWM-PWM Generation1 CH1
+TIM2.OCMode_PWM-PWM\ Generation1\ CH1=TIM_OCMODE_PWM2
+TIM2.PeriodNoDither=99
+TIM2.Prescaler=143
+USART3.IPParameters=WordLength,VirtualMode-Asynchronous
+USART3.VirtualMode-Asynchronous=VM_ASYNC
+USART3.WordLength=WORDLENGTH_8B
 VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
 VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1
 VP_SYS_VS_tim17.Mode=TIM17
 VP_SYS_VS_tim17.Signal=SYS_VS_tim17
 VP_TIM1_VS_ClockSourceINT.Mode=Internal
 VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
+VP_TIM2_VS_ClockSourceINT.Mode=Internal
+VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
 VP_USBPD_VS_USBPD1.Mode=USBPD_P0
 VP_USBPD_VS_USBPD1.Signal=USBPD_VS_USBPD1
-VP_USBPD_VS_usbpd_tim2.Mode=TIM2
-VP_USBPD_VS_usbpd_tim2.Signal=USBPD_VS_usbpd_tim2
+VP_USBPD_VS_usbpd_tim3.Mode=TIM3
+VP_USBPD_VS_usbpd_tim3.Signal=USBPD_VS_usbpd_tim3
 board=custom