diff --git a/Documentation/DeveloperInfo/FPGA_protocol.pdf b/Documentation/DeveloperInfo/FPGA_protocol.pdf index e95fab7..d2a9522 100644 Binary files a/Documentation/DeveloperInfo/FPGA_protocol.pdf and b/Documentation/DeveloperInfo/FPGA_protocol.pdf differ diff --git a/Documentation/DeveloperInfo/FPGA_protocol.tex b/Documentation/DeveloperInfo/FPGA_protocol.tex index 76e55b2..3db4964 100644 --- a/Documentation/DeveloperInfo/FPGA_protocol.tex +++ b/Documentation/DeveloperInfo/FPGA_protocol.tex @@ -65,12 +65,17 @@ MOSI & in & MOSI for SPI communication/MOSI for PLL communication\\ MISO & out & MISO for SPI communication/MUX for PLL communication\\ NSS & in & Chip Select for SPI communication/LE for PLL communication\\ INTR & out & Active high interrupt indicator\\ -RESET & in & FPGA reset\\ +RESET\footnotemark & in & FPGA reset\\ AUX1 & in & Selector for direct communication with Source PLL\\ AUX2 & in & Selector for direct communication with LO PLL\\ AUX3 & in & Active low sweep enable. Has to be high when changing settings\\ +Trigger In\footnotemark & in & Trigger input for synchronization across devices\\ +Trigger Out\footnotemark & Out & Trigger output for synchronization across devices\\ \end{tabular} \end{center} +\footnotetext[1]{Reset is named "MCU\_FPGA\_UNUSED1" in the schematic as this is a later software addition} +\footnotetext[2]{Trigger In is named "MCU\_FPGA\_UNUSED2" in the schematic as this is a later software addition} +\footnotetext[3]{Trigger Out is named "MCU\_FPGA\_UNUSED3" in the schematic as this is a later software addition} Depending on the voltage on AUX1/AUX2 the SPI port controls either the FPGA or one of the MAX2871 PLLs: \begin{center} \begin{tabular}{ c|c|c } @@ -415,7 +420,7 @@ Each point in the sweep is done in stages. Each stage consists of (optionally) r \begin{tikzpicture} \bitrect{16}{16-\bit} \rwbits{0}{3}{Stages} -\rwbits{3}{1}{IH} +\rwbits{3}{1}{SYNC} \robits{4}{6}{reserved} \rwbits{10}{3}{Port 1 stage} \rwbits{13}{3}{Port 2 stage} @@ -423,7 +428,7 @@ Each point in the sweep is done in stages. Each stage consists of (optionally) r \end{center} \begin{itemize} \item \textbf{Stages} Number of stages per point - 1. Normally the number of stages is equal to the number of ports but it can also be less (e.g. if only S11 is measured). -\item \textbf{IH:} Individual halt: Sets the behavior of the "halt sweep" bit (see section~\ref{sweepconfig}). If 1, the sampling is halted before each stage. If 0, the sampling is only halted before the point and all stages are executed without additional halts inbetween. +\item \textbf{SYNC:} Enables synchronization mode (see section~\ref{synchronization}). \item \textbf{Port 1 stage} Number of stage during which the source signal is routed to port 1. Must not have the same value as Port 2 stage. \item \textbf{Port 2 stage} Number of stage during which the source signal is routed to port 2. Must not have the same value as Port 1 stage. \end{itemize} @@ -715,4 +720,37 @@ Each point in the sweep generates a sampling results for each stage (see section \end{tikzpicture} \end{center} +\section{Synchronization} +\label{synchronization} +The FPGA supports synchronization of the sweep across multiple devices. This feature can be enabled by setting the SYNC bit in the sweep setup register (see section~\ref{reg:sweepsetup}). When enabled, the following conditions must be met: +\begin{itemize} +\item All participating devices must be connected in a loop via the trigger input and output pins. The order of the devices is not important. +\item All devices must use the same sweep settings with the exception of the "Port 1 stage" and "Port 2 stage" settings in the sweep setup register. +\item The port stages must be configured in such a way, that for each stage exactly one port is active in one device. +\end{itemize} + +The synchronization works by delaying sampling until the stimulus signal is present, even when generated by another device. For each sampling stage, performs the following steps: +\begin{itemize} +\item When the device generates the stimulus signal in the current phase: +\begin{itemize} +\item Set up source and 1.LO PLLs +\item If applicable: wait for the "resume sweep" command +\item Set the trigger output to high +\item Wait for high level on trigger input +\item Sample ADCs +\item Set the trigger output to low +\item Wait for low level on trigger input +\end{itemize} +\item When the device does not generate the stimulus signal in the current phase: +\begin{itemize} +\item Set 1.LO PLL +\item If applicable: wait for the "resume sweep" command +\item Wait for high level on trigger input +\item Set trigger output to high +\item Sample ADCs +\item Wait for low level on trigger input +\item Set the trigger output to low +\end{itemize} +\end{itemize} + \end{document} \ No newline at end of file diff --git a/FPGA/AMAttenuationCalculator.py b/FPGA/AMAttenuationCalculator.py new file mode 100644 index 0000000..b97047e --- /dev/null +++ b/FPGA/AMAttenuationCalculator.py @@ -0,0 +1,45 @@ +#!/usr/bin/env python3 + +import math + +# Adapt these constants to the step attenuator +BITS_OF_ATTENUATION = 7 +LSB_ATTENUATOR_DB = 0.25 +NUMBER_LINEAR_ATTENUATION_STEPS = 128 + +file = open("AMdepth.dat", "w") + +def bindigits(n, bits): + s = bin(n & int("1"*bits, 2))[2:] + return ("{0:0>%s}" % (bits)).format(s) + +for i in range(NUMBER_LINEAR_ATTENUATION_STEPS): + # calculate percentage of attenuation + percent = float(i) / (NUMBER_LINEAR_ATTENUATION_STEPS - 1) + # calculate attenuation in dB + if percent < 1: + required_dB = -20*math.log10(1 - percent) + else: + required_dB = 999 + # round to attenuator steps + attenuator_dB = round(required_dB / LSB_ATTENUATOR_DB) * LSB_ATTENUATOR_DB + # convert to digital attenuator value + attenuator_step = int(attenuator_dB / LSB_ATTENUATOR_DB) + # constrain + if attenuator_step < 0: + attenuator_step = 0 + elif attenuator_step >= pow(2, BITS_OF_ATTENUATION): + attenuator_step = pow(2, BITS_OF_ATTENUATION) - 1 + output = bindigits(attenuator_step, BITS_OF_ATTENUATION) + file.write(output+"\n") + + # Calculate actual attenuation + actual_dB = attenuator_step * LSB_ATTENUATOR_DB + actual_percent = 1 - pow(10, -actual_dB/20) + + percent_desired = round(percent*100, 2) + percent_actual = round(actual_percent*100, 2) + + print(f'Target modulation: {percent_desired:.2f}, target dB: {required_dB:.2f}, attenuator setting: {attenuator_step}, achieved dB: {actual_dB}, achieved modulation: {percent_actual:.2f}') + +file.close() diff --git a/FPGA/Generator/ipcore_dir/AMMult.gise b/FPGA/Generator/ipcore_dir/AMMult.gise new file mode 100644 index 0000000..f5c03b0 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/AMMult.gise @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/AMMult.vhd b/FPGA/Generator/ipcore_dir/AMMult.vhd new file mode 100644 index 0000000..4354992 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/AMMult.vhd @@ -0,0 +1,102 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2022 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file AMMult.vhd when simulating +-- the core, AMMult. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY AMMult IS + PORT ( + clk : IN STD_LOGIC; + a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + ce : IN STD_LOGIC; + p : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) + ); +END AMMult; + +ARCHITECTURE AMMult_a OF AMMult IS +-- synthesis translate_off +COMPONENT wrapped_AMMult + PORT ( + clk : IN STD_LOGIC; + a : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(6 DOWNTO 0); + ce : IN STD_LOGIC; + p : OUT STD_LOGIC_VECTOR(14 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_AMMult USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral) + GENERIC MAP ( + c_a_type => 1, + c_a_width => 8, + c_b_type => 1, + c_b_value => "10000001", + c_b_width => 7, + c_ccm_imp => 0, + c_ce_overrides_sclr => 0, + c_has_ce => 1, + c_has_sclr => 0, + c_has_zero_detect => 0, + c_latency => 1, + c_model_type => 0, + c_mult_type => 1, + c_optimize_goal => 1, + c_out_high => 14, + c_out_low => 0, + c_round_output => 0, + c_round_pt => 0, + c_verbosity => 0, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_AMMult + PORT MAP ( + clk => clk, + a => a, + b => b, + ce => ce, + p => p + ); +-- synthesis translate_on + +END AMMult_a; diff --git a/FPGA/Generator/ipcore_dir/DFT_CLK.gise b/FPGA/Generator/ipcore_dir/DFT_CLK.gise new file mode 100644 index 0000000..6042a80 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DFT_CLK.gise @@ -0,0 +1,31 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/DFT_CLK.ucf b/FPGA/Generator/ipcore_dir/DFT_CLK.ucf new file mode 100755 index 0000000..f3c5cec --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DFT_CLK.ucf @@ -0,0 +1,59 @@ +# file: DFT_CLK.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps; + + +# FALSE PATH constraints +PIN "RESET" TIG; + diff --git a/FPGA/Generator/ipcore_dir/DFT_CLK.vhd b/FPGA/Generator/ipcore_dir/DFT_CLK.vhd new file mode 100755 index 0000000..0f40de0 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DFT_CLK.vhd @@ -0,0 +1,169 @@ +-- file: DFT_CLK.vhd +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------ +-- User entered comments +------------------------------------------------------------------------------ +-- None +-- +------------------------------------------------------------------------------ +-- "Output Output Phase Duty Pk-to-Pk Phase" +-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +------------------------------------------------------------------------------ +-- CLK_OUT1___160.000______0.000______50.0______336.927____150.000 +-- +------------------------------------------------------------------------------ +-- "Input Clock Freq (MHz) Input Jitter (UI)" +------------------------------------------------------------------------------ +-- __primary______________16____________0.010 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +entity DFT_CLK is +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Clock out ports + CLK_OUT1 : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end DFT_CLK; + +architecture xilinx of DFT_CLK is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of xilinx : architecture is "DFT_CLK,clk_wiz_v3_6,{component_name=DFT_CLK,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=62.5,clkin2_period=62.5,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; + -- Input clock buffering / unused connectors + signal clkin1 : std_logic; + -- Output clock buffering + signal clkfb : std_logic; + signal clk0 : std_logic; + signal clkfx : std_logic; + signal clkfbout : std_logic; + signal locked_internal : std_logic; + signal status_internal : std_logic_vector(7 downto 0); +begin + + + -- Input buffering + -------------------------------------- + clkin1 <= CLK_IN1; + + + -- Clocking primitive + -------------------------------------- + + -- Instantiation of the DCM primitive + -- * Unused inputs are tied off + -- * Unused outputs are labeled unused + dcm_sp_inst: DCM_SP + generic map + (CLKDV_DIVIDE => 2.000, + CLKFX_DIVIDE => 1, + CLKFX_MULTIPLY => 10, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 62.5, + CLKOUT_PHASE_SHIFT => "NONE", + CLK_FEEDBACK => "1X", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map + -- Input clock + (CLKIN => clkin1, + CLKFB => clkfb, + -- Output clocks + CLK0 => clk0, + CLK90 => open, + CLK180 => open, + CLK270 => open, + CLK2X => open, + CLK2X180 => open, + CLKFX => clkfx, + CLKFX180 => open, + CLKDV => open, + -- Ports for dynamic phase shift + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => open, + -- Other control and status signals + LOCKED => locked_internal, + STATUS => status_internal, + RST => RESET, + -- Unused pin, tie low + DSSEN => '0'); + + LOCKED <= locked_internal; + + + + -- Output buffering + ------------------------------------- + clkf_buf : BUFG + port map + (O => clkfb, + I => clk0); + + + clkout1_buf : BUFG + port map + (O => CLK_OUT1, + I => clkfx); + + + +end xilinx; diff --git a/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.ucf b/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.ucf new file mode 100755 index 0000000..bacff37 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.ucf @@ -0,0 +1,60 @@ +# file: DFT_CLK_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps; + + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; +PIN "RESET" TIG; + diff --git a/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.vhd b/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.vhd new file mode 100755 index 0000000..ed2c2d6 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DFT_CLK/example_design/DFT_CLK_exdes.vhd @@ -0,0 +1,192 @@ +-- file: DFT_CLK_exdes.vhd +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + +------------------------------------------------------------------------------ +-- Clocking wizard example design +------------------------------------------------------------------------------ +-- This example design instantiates the created clocking network, where each +-- output clock drives a counter. The high bit of each counter is ported. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +entity DFT_CLK_exdes is +generic ( + TCQ : in time := 100 ps); +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Reset that only drives logic in example design + COUNTER_RESET : in std_logic; + CLK_OUT : out std_logic_vector(1 downto 1) ; + -- High bits of counters driven by clocks + COUNT : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end DFT_CLK_exdes; + +architecture xilinx of DFT_CLK_exdes is + + -- Parameters for the counters + --------------------------------- + -- Counter width + constant C_W : integer := 16; + + + -- When the clock goes out of lock, reset the counters + signal locked_int : std_logic; + signal reset_int : std_logic := '0'; + + -- Declare the clocks and counter + signal clk : std_logic; + signal clk_int : std_logic; + signal clk_n : std_logic; + signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0'); + + -- Need to buffer input clocks that aren't already buffered + signal clk_in1_buf : std_logic; + signal rst_sync : std_logic; + signal rst_sync_int : std_logic; + signal rst_sync_int1 : std_logic; + signal rst_sync_int2 : std_logic; + + +component DFT_CLK is +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Clock out ports + CLK_OUT1 : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end component; + +begin + -- Alias output to internally used signal + LOCKED <= locked_int; + + -- When the clock goes out of lock, reset the counters + reset_int <= (not locked_int) or RESET or COUNTER_RESET; + + + process (clk, reset_int) begin + if (reset_int = '1') then + rst_sync <= '1'; + rst_sync_int <= '1'; + rst_sync_int1 <= '1'; + rst_sync_int2 <= '1'; + elsif (clk 'event and clk='1') then + rst_sync <= '0'; + rst_sync_int <= rst_sync; + rst_sync_int1 <= rst_sync_int; + rst_sync_int2 <= rst_sync_int1; + end if; + end process; + + + -- Insert BUFGs on all input clocks that don't already have them + ---------------------------------------------------------------- + clkin1_buf : BUFG + port map + (O => clk_in1_buf, + I => CLK_IN1); + + -- Instantiation of the clocking network + ---------------------------------------- + clknetwork : DFT_CLK + port map + (-- Clock in ports + CLK_IN1 => clk_in1_buf, + -- Clock out ports + CLK_OUT1 => clk_int, + -- Status and control signals + RESET => RESET, + LOCKED => locked_int); + + clk_n <= not clk; + clkout_oddr : ODDR2 + port map + (Q => CLK_OUT(1), + C0 => clk, + C1 => clk_n, + CE => '1', + D0 => '1', + D1 => '0', + R => '0', + S => '0'); + + -- Connect the output clocks to the design + ------------------------------------------- + clk <= clk_int; + + -- Output clock sampling + ------------------------------------- + process (clk, rst_sync_int2) begin + if (rst_sync_int2 = '1') then + counter <= (others => '0') after TCQ; + elsif (rising_edge(clk)) then + counter <= counter + 1 after TCQ; + end if; + end process; + -- alias the high bit to the output + COUNT <= counter(C_W-1); + + +end xilinx; diff --git a/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/DFT_CLK_tb.vhd b/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/DFT_CLK_tb.vhd new file mode 100755 index 0000000..d425375 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/DFT_CLK_tb.vhd @@ -0,0 +1,197 @@ +-- file: DFT_CLK_tb.vhd +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + +------------------------------------------------------------------------------ +-- Clocking wizard demonstration testbench +------------------------------------------------------------------------------ +-- This demonstration testbench instantiates the example design for the +-- clocking wizard. Input clocks are toggled, which cause the clocking +-- network to lock and the counters to increment. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; + +library std; +use std.textio.all; + +library work; +use work.all; + +entity DFT_CLK_tb is +end DFT_CLK_tb; + +architecture test of DFT_CLK_tb is + + -- Clock to Q delay of 100 ps + constant TCQ : time := 100 ps; + -- timescale is 1ps + constant ONE_NS : time := 1 ns; + -- how many cycles to run + constant COUNT_PHASE : integer := 1024 + 1; + + + -- we'll be using the period in many locations + constant PER1 : time := 62.5 ns; + + + -- Declare the input clock signals + signal CLK_IN1 : std_logic := '1'; + -- The high bit of the sampling counter + signal COUNT : std_logic; + -- Status and control signals + signal RESET : std_logic := '0'; + signal LOCKED : std_logic; + signal COUNTER_RESET : std_logic := '0'; +-- signal defined to stop mti simulation without severity failure in the report + signal end_of_sim : std_logic := '0'; + signal CLK_OUT : std_logic_vector(1 downto 1); +--Freq Check using the M & D values setting and actual Frequency generated + +component DFT_CLK_exdes +generic ( + TCQ : in time := 100 ps); +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Reset that only drives logic in example design + COUNTER_RESET : in std_logic; + CLK_OUT : out std_logic_vector(1 downto 1) ; + -- High bits of counters driven by clocks + COUNT : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end component; + +begin + + -- Input clock generation + -------------------------------------- + process begin + CLK_IN1 <= not CLK_IN1; wait for (PER1/2); + end process; + + -- Test sequence + process + + procedure simtimeprint is + variable outline : line; + begin + write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); + write(outline, NOW/PER1); + write(outline, string'(" ns")); + writeline(output,outline); + end simtimeprint; + + procedure simfreqprint (period : time; clk_num : integer) is + variable outputline : LINE; + variable str1 : string(1 to 16); + variable str2 : integer; + variable str3 : string(1 to 2); + variable str4 : integer; + variable str5 : string(1 to 4); + begin + str1 := "Freq of CLK_OUT("; + str2 := clk_num; + str3 := ") "; + str4 := 1000000 ps/period ; + str5 := " MHz" ; + write(outputline, str1 ); + write(outputline, str2); + write(outputline, str3); + write(outputline, str4); + write(outputline, str5); + writeline(output, outputline); + end simfreqprint; + + begin + RESET <= '1'; + wait for (PER1*6); + RESET <= '0'; + wait until LOCKED = '1'; + COUNTER_RESET <= '1'; + wait for (PER1*20); + COUNTER_RESET <= '0'; + wait for (PER1*COUNT_PHASE); + + + simtimeprint; + end_of_sim <= '1'; + wait for 1 ps; + report "Simulation Stopped." severity failure; + wait; + end process; + + -- Instantiation of the example design containing the clock + -- network and sampling counters + ----------------------------------------------------------- + dut : DFT_CLK_exdes + generic map ( + TCQ => TCQ) + port map + (-- Clock in ports + CLK_IN1 => CLK_IN1, + -- Reset for logic in example design + COUNTER_RESET => COUNTER_RESET, + CLK_OUT => CLK_OUT, + -- High bits of the counters + COUNT => COUNT, + -- Status and control signals + RESET => RESET, + LOCKED => LOCKED); + +-- Freq Check + +end test; diff --git a/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/timing/DFT_CLK_tb.vhd b/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/timing/DFT_CLK_tb.vhd new file mode 100755 index 0000000..7d7055c --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DFT_CLK/simulation/timing/DFT_CLK_tb.vhd @@ -0,0 +1,220 @@ +-- file: DFT_CLK_tb.vhd +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + +------------------------------------------------------------------------------ +-- Clocking wizard demonstration testbench +------------------------------------------------------------------------------ +-- This demonstration testbench instantiates the example design for the +-- clocking wizard. Input clocks are toggled, which cause the clocking +-- network to lock and the counters to increment. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; + +library std; +use std.textio.all; + +library work; +use work.all; + +entity DFT_CLK_tb is +end DFT_CLK_tb; + +architecture test of DFT_CLK_tb is + + -- Clock to Q delay of 100 ps + constant TCQ : time := 100 ps; + -- timescale is 1ps + constant ONE_NS : time := 1 ns; + -- how many cycles to run + constant COUNT_PHASE : integer := 1024 + 1; + + + -- we'll be using the period in many locations + constant PER1 : time := 62.5 ns; + + + -- Declare the input clock signals + signal CLK_IN1 : std_logic := '1'; + -- The high bit of the sampling counter + signal COUNT : std_logic; + -- Status and control signals + signal RESET : std_logic := '0'; + signal LOCKED : std_logic; + signal COUNTER_RESET : std_logic := '0'; + signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0'); +-- signal defined to stop mti simulation without severity failure in the report + signal end_of_sim : std_logic := '0'; + signal CLK_OUT : std_logic_vector(1 downto 1); +--Freq Check using the M & D values setting and actual Frequency generated + +component DFT_CLK_exdes +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Reset that only drives logic in example design + COUNTER_RESET : in std_logic; + CLK_OUT : out std_logic_vector(1 downto 1) ; + -- High bits of counters driven by clocks + COUNT : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end component; + +begin + + -- Input clock generation + -------------------------------------- + process begin + CLK_IN1 <= not CLK_IN1; wait for (PER1/2); + end process; + + -- Test sequence + process + + procedure simtimeprint is + variable outline : line; + begin + write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); + write(outline, NOW/PER1); + write(outline, string'(" ns")); + writeline(output,outline); + end simtimeprint; + + procedure simfreqprint (period : time; clk_num : integer) is + variable outputline : LINE; + variable str1 : string(1 to 16); + variable str2 : integer; + variable str3 : string(1 to 2); + variable str4 : integer; + variable str5 : string(1 to 4); + begin + str1 := "Freq of CLK_OUT("; + str2 := clk_num; + str3 := ") "; + str4 := 1000000 ps/period ; + str5 := " MHz" ; + write(outputline, str1 ); + write(outputline, str2); + write(outputline, str3); + write(outputline, str4); + write(outputline, str5); + writeline(output, outputline); + end simfreqprint; + + begin + report "Timing checks are not valid" severity note; + RESET <= '1'; + wait for (PER1*6); + RESET <= '0'; + wait until LOCKED = '1'; + wait for (PER1*20); + COUNTER_RESET <= '1'; + wait for (PER1*19.5); + COUNTER_RESET <= '0'; + wait for (PER1*1); + report "Timing checks are valid" severity note; + wait for (PER1*COUNT_PHASE); + + + simtimeprint; + end_of_sim <= '1'; + wait for 1 ps; + report "Simulation Stopped." severity failure; + wait; + end process; + + process (CLK_IN1) + procedure simtimeprint is + variable outline : line; + begin + write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); + write(outline, NOW/PER1); + write(outline, string'(" ns")); + writeline(output,outline); + end simtimeprint; + begin + if (CLK_IN1'event and CLK_IN1='1') then + timeout_counter <= timeout_counter + '1'; + if (timeout_counter = "10000000000000") then + if (LOCKED /= '1') then + simtimeprint; + report "NO LOCK signal" severity failure; + end if; + end if; + end if; + end process; + + + -- Instantiation of the example design containing the clock + -- network and sampling counters + ----------------------------------------------------------- + dut : DFT_CLK_exdes + port map + (-- Clock in ports + CLK_IN1 => CLK_IN1, + -- Reset for logic in example design + COUNTER_RESET => COUNTER_RESET, + CLK_OUT => CLK_OUT, + -- High bits of the counters + COUNT => COUNT, + -- Status and control signals + RESET => RESET, + LOCKED => LOCKED); + +-- Freq Check + +end test; diff --git a/FPGA/Generator/ipcore_dir/DSP48.gise b/FPGA/Generator/ipcore_dir/DSP48.gise new file mode 100644 index 0000000..93248ea --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DSP48.gise @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/DSP48.vhd b/FPGA/Generator/ipcore_dir/DSP48.vhd new file mode 100644 index 0000000..5895fe1 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DSP48.vhd @@ -0,0 +1,139 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2020 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file DSP48.vhd when simulating +-- the core, DSP48. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY DSP48 IS + PORT ( + clk : IN STD_LOGIC; + ce : IN STD_LOGIC; + sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + a : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + c : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); +END DSP48; + +ARCHITECTURE DSP48_a OF DSP48 IS +-- synthesis translate_off +COMPONENT wrapped_DSP48 + PORT ( + clk : IN STD_LOGIC; + ce : IN STD_LOGIC; + sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + a : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + c : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_DSP48 USE ENTITY XilinxCoreLib.xbip_dsp48_macro_v2_1(behavioral) + GENERIC MAP ( + c_a_width => 18, + c_b_width => 18, + c_c_width => 48, + c_concat_width => 48, + c_constant_1 => 1, + c_d_width => 18, + c_has_a => 1, + c_has_acin => 0, + c_has_acout => 0, + c_has_b => 1, + c_has_bcin => 0, + c_has_bcout => 0, + c_has_c => 1, + c_has_carrycascin => 0, + c_has_carrycascout => 0, + c_has_carryin => 0, + c_has_carryout => 0, + c_has_ce => 1, + c_has_cea => 0, + c_has_ceb => 0, + c_has_cec => 0, + c_has_ceconcat => 0, + c_has_ced => 0, + c_has_cem => 0, + c_has_cep => 0, + c_has_cesel => 0, + c_has_concat => 0, + c_has_d => 0, + c_has_indep_ce => 0, + c_has_indep_sclr => 0, + c_has_pcin => 0, + c_has_pcout => 0, + c_has_sclr => 0, + c_has_sclra => 0, + c_has_sclrb => 0, + c_has_sclrc => 0, + c_has_sclrconcat => 0, + c_has_sclrd => 0, + c_has_sclrm => 0, + c_has_sclrp => 0, + c_has_sclrsel => 0, + c_latency => -1, + c_model_type => 0, + c_opmodes => "0000000000010000000,0000001100010000000", + c_p_lsb => 0, + c_p_msb => 47, + c_reg_config => "00000000000011100111100111100100", + c_sel_width => 1, + c_test_core => 0, + c_verbosity => 0, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_DSP48 + PORT MAP ( + clk => clk, + ce => ce, + sel => sel, + a => a, + b => b, + c => c, + p => p + ); +-- synthesis translate_on + +END DSP48_a; diff --git a/FPGA/Generator/ipcore_dir/DSP_SLICE.gise b/FPGA/Generator/ipcore_dir/DSP_SLICE.gise new file mode 100644 index 0000000..edc3d0f --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DSP_SLICE.gise @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/DSP_SLICE.vhd b/FPGA/Generator/ipcore_dir/DSP_SLICE.vhd new file mode 100644 index 0000000..c378c8c --- /dev/null +++ b/FPGA/Generator/ipcore_dir/DSP_SLICE.vhd @@ -0,0 +1,139 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2020 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file DSP_SLICE.vhd when simulating +-- the core, DSP_SLICE. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY DSP_SLICE IS + PORT ( + clk : IN STD_LOGIC; + ce : IN STD_LOGIC; + sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + a : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + c : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); +END DSP_SLICE; + +ARCHITECTURE DSP_SLICE_a OF DSP_SLICE IS +-- synthesis translate_off +COMPONENT wrapped_DSP_SLICE + PORT ( + clk : IN STD_LOGIC; + ce : IN STD_LOGIC; + sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + a : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(17 DOWNTO 0); + c : IN STD_LOGIC_VECTOR(47 DOWNTO 0); + p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_DSP_SLICE USE ENTITY XilinxCoreLib.xbip_dsp48_macro_v2_1(behavioral) + GENERIC MAP ( + c_a_width => 18, + c_b_width => 18, + c_c_width => 48, + c_concat_width => 48, + c_constant_1 => 1, + c_d_width => 18, + c_has_a => 1, + c_has_acin => 0, + c_has_acout => 0, + c_has_b => 1, + c_has_bcin => 0, + c_has_bcout => 0, + c_has_c => 1, + c_has_carrycascin => 0, + c_has_carrycascout => 0, + c_has_carryin => 0, + c_has_carryout => 0, + c_has_ce => 1, + c_has_cea => 0, + c_has_ceb => 0, + c_has_cec => 0, + c_has_ceconcat => 0, + c_has_ced => 0, + c_has_cem => 0, + c_has_cep => 0, + c_has_cesel => 0, + c_has_concat => 0, + c_has_d => 0, + c_has_indep_ce => 0, + c_has_indep_sclr => 0, + c_has_pcin => 0, + c_has_pcout => 0, + c_has_sclr => 0, + c_has_sclra => 0, + c_has_sclrb => 0, + c_has_sclrc => 0, + c_has_sclrconcat => 0, + c_has_sclrd => 0, + c_has_sclrm => 0, + c_has_sclrp => 0, + c_has_sclrsel => 0, + c_latency => -1, + c_model_type => 0, + c_opmodes => "0000000000010000000,0000001100010000000", + c_p_lsb => 0, + c_p_msb => 47, + c_reg_config => "00000000000011100111100111100100", + c_sel_width => 1, + c_test_core => 0, + c_verbosity => 0, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_DSP_SLICE + PORT MAP ( + clk => clk, + ce => ce, + sel => sel, + a => a, + b => b, + c => c, + p => p + ); +-- synthesis translate_on + +END DSP_SLICE_a; diff --git a/FPGA/Generator/ipcore_dir/ModulationMemory.gise b/FPGA/Generator/ipcore_dir/ModulationMemory.gise new file mode 100644 index 0000000..f652c16 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/ModulationMemory.gise @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/ModulationMemory.vhd b/FPGA/Generator/ipcore_dir/ModulationMemory.vhd new file mode 100644 index 0000000..0c4ec46 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/ModulationMemory.vhd @@ -0,0 +1,149 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2022 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file ModulationMemory.vhd when simulating +-- the core, ModulationMemory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY ModulationMemory IS + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(143 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(143 DOWNTO 0) + ); +END ModulationMemory; + +ARCHITECTURE ModulationMemory_a OF ModulationMemory IS +-- synthesis translate_off +COMPONENT wrapped_ModulationMemory + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(143 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(143 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_ModulationMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) + GENERIC MAP ( + c_addra_width => 8, + c_addrb_width => 8, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan6", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file => "BlankString", + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 1, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 256, + c_read_depth_b => 256, + c_read_width_a => 144, + c_read_width_b => 144, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_bram_block => 0, + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 256, + c_write_depth_b => 256, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 144, + c_write_width_b => 144, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_ModulationMemory + PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + addrb => addrb, + doutb => doutb + ); +-- synthesis translate_on + +END ModulationMemory_a; diff --git a/FPGA/Generator/ipcore_dir/PLL.gise b/FPGA/Generator/ipcore_dir/PLL.gise new file mode 100644 index 0000000..2143394 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/PLL.gise @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/PLL.ucf b/FPGA/Generator/ipcore_dir/PLL.ucf new file mode 100755 index 0000000..609adfb --- /dev/null +++ b/FPGA/Generator/ipcore_dir/PLL.ucf @@ -0,0 +1,59 @@ +# file: PLL.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps; + + +# FALSE PATH constraints +PIN "RESET" TIG; + diff --git a/FPGA/Generator/ipcore_dir/PLL.vhd b/FPGA/Generator/ipcore_dir/PLL.vhd new file mode 100755 index 0000000..5b1fe31 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/PLL.vhd @@ -0,0 +1,172 @@ +-- file: PLL.vhd +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +------------------------------------------------------------------------------ +-- User entered comments +------------------------------------------------------------------------------ +-- None +-- +------------------------------------------------------------------------------ +-- "Output Output Phase Duty Pk-to-Pk Phase" +-- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" +------------------------------------------------------------------------------ +-- CLK_OUT1___102.400______0.000______50.0_____1274.405____150.000 +-- +------------------------------------------------------------------------------ +-- "Input Clock Freq (MHz) Input Jitter (UI)" +------------------------------------------------------------------------------ +-- __primary______________16____________0.010 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +entity PLL is +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Clock out ports + CLK_OUT1 : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end PLL; + +architecture xilinx of PLL is + attribute CORE_GENERATION_INFO : string; + attribute CORE_GENERATION_INFO of xilinx : architecture is "PLL,clk_wiz_v3_6,{component_name=PLL,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=62.5,clkin2_period=62.5,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; + -- Input clock buffering / unused connectors + signal clkin1 : std_logic; + -- Output clock buffering + signal clkfb : std_logic; + signal clk0 : std_logic; + signal clkfx : std_logic; + signal clkfbout : std_logic; + signal locked_internal : std_logic; + signal status_internal : std_logic_vector(7 downto 0); +begin + + + -- Input buffering + -------------------------------------- + clkin1_buf : IBUFG + port map + (O => clkin1, + I => CLK_IN1); + + + -- Clocking primitive + -------------------------------------- + + -- Instantiation of the DCM primitive + -- * Unused inputs are tied off + -- * Unused outputs are labeled unused + dcm_sp_inst: DCM_SP + generic map + (CLKDV_DIVIDE => 2.000, + CLKFX_DIVIDE => 5, + CLKFX_MULTIPLY => 32, + CLKIN_DIVIDE_BY_2 => FALSE, + CLKIN_PERIOD => 62.5, + CLKOUT_PHASE_SHIFT => "NONE", + CLK_FEEDBACK => "1X", + DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", + PHASE_SHIFT => 0, + STARTUP_WAIT => FALSE) + port map + -- Input clock + (CLKIN => clkin1, + CLKFB => clkfb, + -- Output clocks + CLK0 => clk0, + CLK90 => open, + CLK180 => open, + CLK270 => open, + CLK2X => open, + CLK2X180 => open, + CLKFX => clkfx, + CLKFX180 => open, + CLKDV => open, + -- Ports for dynamic phase shift + PSCLK => '0', + PSEN => '0', + PSINCDEC => '0', + PSDONE => open, + -- Other control and status signals + LOCKED => locked_internal, + STATUS => status_internal, + RST => RESET, + -- Unused pin, tie low + DSSEN => '0'); + + LOCKED <= locked_internal; + + + + -- Output buffering + ------------------------------------- + clkf_buf : BUFG + port map + (O => clkfb, + I => clk0); + + + clkout1_buf : BUFG + port map + (O => CLK_OUT1, + I => clkfx); + + + +end xilinx; diff --git a/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.ucf b/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.ucf new file mode 100755 index 0000000..7b69c75 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.ucf @@ -0,0 +1,60 @@ +# file: PLL_exdes.ucf +# +# (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# + +# Input clock periods. These duplicate the values entered for the +# input clocks. You can use these to time your system +#---------------------------------------------------------------- +NET "CLK_IN1" TNM_NET = "CLK_IN1"; +TIMESPEC "TS_CLK_IN1" = PERIOD "CLK_IN1" 62.5 ns HIGH 50% INPUT_JITTER 625.0ps; + + +# FALSE PATH constraints +PIN "COUNTER_RESET" TIG; +PIN "RESET" TIG; + diff --git a/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.vhd b/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.vhd new file mode 100755 index 0000000..7feb2bc --- /dev/null +++ b/FPGA/Generator/ipcore_dir/PLL/example_design/PLL_exdes.vhd @@ -0,0 +1,182 @@ +-- file: PLL_exdes.vhd +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + +------------------------------------------------------------------------------ +-- Clocking wizard example design +------------------------------------------------------------------------------ +-- This example design instantiates the created clocking network, where each +-- output clock drives a counter. The high bit of each counter is ported. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; + +library unisim; +use unisim.vcomponents.all; + +entity PLL_exdes is +generic ( + TCQ : in time := 100 ps); +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Reset that only drives logic in example design + COUNTER_RESET : in std_logic; + CLK_OUT : out std_logic_vector(1 downto 1) ; + -- High bits of counters driven by clocks + COUNT : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end PLL_exdes; + +architecture xilinx of PLL_exdes is + + -- Parameters for the counters + --------------------------------- + -- Counter width + constant C_W : integer := 16; + + + -- When the clock goes out of lock, reset the counters + signal locked_int : std_logic; + signal reset_int : std_logic := '0'; + + -- Declare the clocks and counter + signal clk : std_logic; + signal clk_int : std_logic; + signal clk_n : std_logic; + signal counter : std_logic_vector(C_W-1 downto 0) := (others => '0'); + signal rst_sync : std_logic; + signal rst_sync_int : std_logic; + signal rst_sync_int1 : std_logic; + signal rst_sync_int2 : std_logic; + + +component PLL is +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Clock out ports + CLK_OUT1 : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end component; + +begin + -- Alias output to internally used signal + LOCKED <= locked_int; + + -- When the clock goes out of lock, reset the counters + reset_int <= (not locked_int) or RESET or COUNTER_RESET; + + + process (clk, reset_int) begin + if (reset_int = '1') then + rst_sync <= '1'; + rst_sync_int <= '1'; + rst_sync_int1 <= '1'; + rst_sync_int2 <= '1'; + elsif (clk 'event and clk='1') then + rst_sync <= '0'; + rst_sync_int <= rst_sync; + rst_sync_int1 <= rst_sync_int; + rst_sync_int2 <= rst_sync_int1; + end if; + end process; + + + -- Instantiation of the clocking network + ---------------------------------------- + clknetwork : PLL + port map + (-- Clock in ports + CLK_IN1 => CLK_IN1, + -- Clock out ports + CLK_OUT1 => clk_int, + -- Status and control signals + RESET => RESET, + LOCKED => locked_int); + + clk_n <= not clk; + clkout_oddr : ODDR2 + port map + (Q => CLK_OUT(1), + C0 => clk, + C1 => clk_n, + CE => '1', + D0 => '1', + D1 => '0', + R => '0', + S => '0'); + + -- Connect the output clocks to the design + ------------------------------------------- + clk <= clk_int; + + -- Output clock sampling + ------------------------------------- + process (clk, rst_sync_int2) begin + if (rst_sync_int2 = '1') then + counter <= (others => '0') after TCQ; + elsif (rising_edge(clk)) then + counter <= counter + 1 after TCQ; + end if; + end process; + -- alias the high bit to the output + COUNT <= counter(C_W-1); + + +end xilinx; diff --git a/FPGA/Generator/ipcore_dir/PLL/simulation/PLL_tb.vhd b/FPGA/Generator/ipcore_dir/PLL/simulation/PLL_tb.vhd new file mode 100755 index 0000000..3448143 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/PLL/simulation/PLL_tb.vhd @@ -0,0 +1,197 @@ +-- file: PLL_tb.vhd +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + +------------------------------------------------------------------------------ +-- Clocking wizard demonstration testbench +------------------------------------------------------------------------------ +-- This demonstration testbench instantiates the example design for the +-- clocking wizard. Input clocks are toggled, which cause the clocking +-- network to lock and the counters to increment. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; + +library std; +use std.textio.all; + +library work; +use work.all; + +entity PLL_tb is +end PLL_tb; + +architecture test of PLL_tb is + + -- Clock to Q delay of 100 ps + constant TCQ : time := 100 ps; + -- timescale is 1ps + constant ONE_NS : time := 1 ns; + -- how many cycles to run + constant COUNT_PHASE : integer := 1024 + 1; + + + -- we'll be using the period in many locations + constant PER1 : time := 62.5 ns; + + + -- Declare the input clock signals + signal CLK_IN1 : std_logic := '1'; + -- The high bit of the sampling counter + signal COUNT : std_logic; + -- Status and control signals + signal RESET : std_logic := '0'; + signal LOCKED : std_logic; + signal COUNTER_RESET : std_logic := '0'; +-- signal defined to stop mti simulation without severity failure in the report + signal end_of_sim : std_logic := '0'; + signal CLK_OUT : std_logic_vector(1 downto 1); +--Freq Check using the M & D values setting and actual Frequency generated + +component PLL_exdes +generic ( + TCQ : in time := 100 ps); +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Reset that only drives logic in example design + COUNTER_RESET : in std_logic; + CLK_OUT : out std_logic_vector(1 downto 1) ; + -- High bits of counters driven by clocks + COUNT : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end component; + +begin + + -- Input clock generation + -------------------------------------- + process begin + CLK_IN1 <= not CLK_IN1; wait for (PER1/2); + end process; + + -- Test sequence + process + + procedure simtimeprint is + variable outline : line; + begin + write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); + write(outline, NOW/PER1); + write(outline, string'(" ns")); + writeline(output,outline); + end simtimeprint; + + procedure simfreqprint (period : time; clk_num : integer) is + variable outputline : LINE; + variable str1 : string(1 to 16); + variable str2 : integer; + variable str3 : string(1 to 2); + variable str4 : integer; + variable str5 : string(1 to 4); + begin + str1 := "Freq of CLK_OUT("; + str2 := clk_num; + str3 := ") "; + str4 := 1000000 ps/period ; + str5 := " MHz" ; + write(outputline, str1 ); + write(outputline, str2); + write(outputline, str3); + write(outputline, str4); + write(outputline, str5); + writeline(output, outputline); + end simfreqprint; + + begin + RESET <= '1'; + wait for (PER1*6); + RESET <= '0'; + wait until LOCKED = '1'; + COUNTER_RESET <= '1'; + wait for (PER1*20); + COUNTER_RESET <= '0'; + wait for (PER1*COUNT_PHASE); + + + simtimeprint; + end_of_sim <= '1'; + wait for 1 ps; + report "Simulation Stopped." severity failure; + wait; + end process; + + -- Instantiation of the example design containing the clock + -- network and sampling counters + ----------------------------------------------------------- + dut : PLL_exdes + generic map ( + TCQ => TCQ) + port map + (-- Clock in ports + CLK_IN1 => CLK_IN1, + -- Reset for logic in example design + COUNTER_RESET => COUNTER_RESET, + CLK_OUT => CLK_OUT, + -- High bits of the counters + COUNT => COUNT, + -- Status and control signals + RESET => RESET, + LOCKED => LOCKED); + +-- Freq Check + +end test; diff --git a/FPGA/Generator/ipcore_dir/PLL/simulation/timing/PLL_tb.vhd b/FPGA/Generator/ipcore_dir/PLL/simulation/timing/PLL_tb.vhd new file mode 100755 index 0000000..e04f5b6 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/PLL/simulation/timing/PLL_tb.vhd @@ -0,0 +1,220 @@ +-- file: PLL_tb.vhd +-- +-- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- + +------------------------------------------------------------------------------ +-- Clocking wizard demonstration testbench +------------------------------------------------------------------------------ +-- This demonstration testbench instantiates the example design for the +-- clocking wizard. Input clocks are toggled, which cause the clocking +-- network to lock and the counters to increment. +------------------------------------------------------------------------------ + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.std_logic_arith.all; +use ieee.numeric_std.all; +use ieee.std_logic_textio.all; + +library std; +use std.textio.all; + +library work; +use work.all; + +entity PLL_tb is +end PLL_tb; + +architecture test of PLL_tb is + + -- Clock to Q delay of 100 ps + constant TCQ : time := 100 ps; + -- timescale is 1ps + constant ONE_NS : time := 1 ns; + -- how many cycles to run + constant COUNT_PHASE : integer := 1024 + 1; + + + -- we'll be using the period in many locations + constant PER1 : time := 62.5 ns; + + + -- Declare the input clock signals + signal CLK_IN1 : std_logic := '1'; + -- The high bit of the sampling counter + signal COUNT : std_logic; + -- Status and control signals + signal RESET : std_logic := '0'; + signal LOCKED : std_logic; + signal COUNTER_RESET : std_logic := '0'; + signal timeout_counter : std_logic_vector (13 downto 0) := (others => '0'); +-- signal defined to stop mti simulation without severity failure in the report + signal end_of_sim : std_logic := '0'; + signal CLK_OUT : std_logic_vector(1 downto 1); +--Freq Check using the M & D values setting and actual Frequency generated + +component PLL_exdes +port + (-- Clock in ports + CLK_IN1 : in std_logic; + -- Reset that only drives logic in example design + COUNTER_RESET : in std_logic; + CLK_OUT : out std_logic_vector(1 downto 1) ; + -- High bits of counters driven by clocks + COUNT : out std_logic; + -- Status and control signals + RESET : in std_logic; + LOCKED : out std_logic + ); +end component; + +begin + + -- Input clock generation + -------------------------------------- + process begin + CLK_IN1 <= not CLK_IN1; wait for (PER1/2); + end process; + + -- Test sequence + process + + procedure simtimeprint is + variable outline : line; + begin + write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); + write(outline, NOW/PER1); + write(outline, string'(" ns")); + writeline(output,outline); + end simtimeprint; + + procedure simfreqprint (period : time; clk_num : integer) is + variable outputline : LINE; + variable str1 : string(1 to 16); + variable str2 : integer; + variable str3 : string(1 to 2); + variable str4 : integer; + variable str5 : string(1 to 4); + begin + str1 := "Freq of CLK_OUT("; + str2 := clk_num; + str3 := ") "; + str4 := 1000000 ps/period ; + str5 := " MHz" ; + write(outputline, str1 ); + write(outputline, str2); + write(outputline, str3); + write(outputline, str4); + write(outputline, str5); + writeline(output, outputline); + end simfreqprint; + + begin + report "Timing checks are not valid" severity note; + RESET <= '1'; + wait for (PER1*6); + RESET <= '0'; + wait until LOCKED = '1'; + wait for (PER1*20); + COUNTER_RESET <= '1'; + wait for (PER1*19.5); + COUNTER_RESET <= '0'; + wait for (PER1*1); + report "Timing checks are valid" severity note; + wait for (PER1*COUNT_PHASE); + + + simtimeprint; + end_of_sim <= '1'; + wait for 1 ps; + report "Simulation Stopped." severity failure; + wait; + end process; + + process (CLK_IN1) + procedure simtimeprint is + variable outline : line; + begin + write(outline, string'("## SYSTEM_CYCLE_COUNTER ")); + write(outline, NOW/PER1); + write(outline, string'(" ns")); + writeline(output,outline); + end simtimeprint; + begin + if (CLK_IN1'event and CLK_IN1='1') then + timeout_counter <= timeout_counter + '1'; + if (timeout_counter = "10000000000000") then + if (LOCKED /= '1') then + simtimeprint; + report "NO LOCK signal" severity failure; + end if; + end if; + end if; + end process; + + + -- Instantiation of the example design containing the clock + -- network and sampling counters + ----------------------------------------------------------- + dut : PLL_exdes + port map + (-- Clock in ports + CLK_IN1 => CLK_IN1, + -- Reset for logic in example design + COUNTER_RESET => COUNTER_RESET, + CLK_OUT => CLK_OUT, + -- High bits of the counters + COUNT => COUNT, + -- Status and control signals + RESET => RESET, + LOCKED => LOCKED); + +-- Freq Check + +end test; diff --git a/FPGA/Generator/ipcore_dir/SampleMemory.gise b/FPGA/Generator/ipcore_dir/SampleMemory.gise new file mode 100644 index 0000000..1b9c9e1 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SampleMemory.gise @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/SampleMemory.vhd b/FPGA/Generator/ipcore_dir/SampleMemory.vhd new file mode 100644 index 0000000..8f6e7e1 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SampleMemory.vhd @@ -0,0 +1,149 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2022 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file SampleMemory.vhd when simulating +-- the core, SampleMemory. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY SampleMemory IS + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END SampleMemory; + +ARCHITECTURE SampleMemory_a OF SampleMemory IS +-- synthesis translate_off +COMPONENT wrapped_SampleMemory + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(10 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_SampleMemory USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) + GENERIC MAP ( + c_addra_width => 11, + c_addrb_width => 11, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan6", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file => "BlankString", + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 1, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 2048, + c_read_depth_b => 2048, + c_read_width_a => 8, + c_read_width_b => 8, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_bram_block => 0, + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 2048, + c_write_depth_b => 2048, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 8, + c_write_width_b => 8, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_SampleMemory + PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + addrb => addrb, + doutb => doutb + ); +-- synthesis translate_on + +END SampleMemory_a; diff --git a/FPGA/Generator/ipcore_dir/SinCos.gise b/FPGA/Generator/ipcore_dir/SinCos.gise new file mode 100644 index 0000000..f561140 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SinCos.gise @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/SinCos.vhd b/FPGA/Generator/ipcore_dir/SinCos.vhd new file mode 100644 index 0000000..77f6c2b --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SinCos.vhd @@ -0,0 +1,106 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2020 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file SinCos.vhd when simulating +-- the core, SinCos. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY SinCos IS + PORT ( + clk : IN STD_LOGIC; + phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END SinCos; + +ARCHITECTURE SinCos_a OF SinCos IS +-- synthesis translate_off +COMPONENT wrapped_SinCos + PORT ( + clk : IN STD_LOGIC; + phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0); + cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); + sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_SinCos USE ENTITY XilinxCoreLib.dds_compiler_v4_0(behavioral) + GENERIC MAP ( + c_accumulator_width => 12, + c_amplitude => 0, + c_channels => 1, + c_has_ce => 0, + c_has_channel_index => 0, + c_has_phase_out => 0, + c_has_phasegen => 0, + c_has_rdy => 0, + c_has_rfd => 0, + c_has_sclr => 0, + c_has_sincos => 1, + c_latency => -1, + c_mem_type => 1, + c_negative_cosine => 0, + c_negative_sine => 0, + c_noise_shaping => 0, + c_optimise_goal => 0, + c_output_width => 16, + c_outputs_required => 2, + c_phase_angle_width => 12, + c_phase_increment => 2, + c_phase_increment_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", + c_phase_offset => 0, + c_phase_offset_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0", + c_por_mode => 0, + c_use_dsp48 => 0, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_SinCos + PORT MAP ( + clk => clk, + phase_in => phase_in, + cosine => cosine, + sine => sine + ); +-- synthesis translate_on + +END SinCos_a; diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem.gise b/FPGA/Generator/ipcore_dir/SweepConfigMem.gise new file mode 100644 index 0000000..faea9f1 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem.gise @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem.vhd new file mode 100644 index 0000000..78c5afa --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem.vhd @@ -0,0 +1,152 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2020 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file SweepConfigMem.vhd when simulating +-- the core, SweepConfigMem. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY SweepConfigMem IS + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0) + ); +END SweepConfigMem; + +ARCHITECTURE SweepConfigMem_a OF SweepConfigMem IS +-- synthesis translate_off +COMPONENT wrapped_SweepConfigMem + PORT ( + clka : IN STD_LOGIC; + ena : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(95 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_SweepConfigMem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) + GENERIC MAP ( + c_addra_width => 13, + c_addrb_width => 13, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan6", + c_has_axi_id => 0, + c_has_ena => 1, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file => "BlankString", + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 1, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 4501, + c_read_depth_b => 4501, + c_read_width_a => 96, + c_read_width_b => 96, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_bram_block => 0, + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 4501, + c_write_depth_b => 4501, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 96, + c_write_width_b => 96, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_SweepConfigMem + PORT MAP ( + clka => clka, + ena => ena, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + addrb => addrb, + doutb => doutb + ); +-- synthesis translate_on + +END SweepConfigMem_a; diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.ucf b/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.ucf new file mode 100755 index 0000000..3762632 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.ucf @@ -0,0 +1,61 @@ +################################################################################ +# +# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLKA" TNM_NET = "CLKA"; + +NET "CLKB" TNM_NET = "CLKB"; + +TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; + +TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ; + +################################################################################ diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.vhd new file mode 100755 index 0000000..e9cbba1 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_exdes.vhd @@ -0,0 +1,182 @@ + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: SweepConfigMem_exdes.vhd +-- +-- Description: +-- This is the actual BMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY SweepConfigMem_exdes IS + PORT ( + --Inputs - Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + + CLKA : IN STD_LOGIC; + + + --Inputs - Port B + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + CLKB : IN STD_LOGIC + + ); + +END SweepConfigMem_exdes; + + +ARCHITECTURE xilinx OF SweepConfigMem_exdes IS + + COMPONENT BUFG IS + PORT ( + I : IN STD_ULOGIC; + O : OUT STD_ULOGIC + ); + END COMPONENT; + + COMPONENT SweepConfigMem IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + CLKB : IN STD_LOGIC + + + ); + END COMPONENT; + + SIGNAL CLKA_buf : STD_LOGIC; + SIGNAL CLKB_buf : STD_LOGIC; + SIGNAL S_ACLK_buf : STD_LOGIC; + +BEGIN + + bufg_A : BUFG + PORT MAP ( + I => CLKA, + O => CLKA_buf + ); + + bufg_B : BUFG + PORT MAP ( + I => CLKB, + O => CLKB_buf + ); + + + bmg0 : SweepConfigMem + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA_buf, + + + --Port B + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB_buf + + ); + +END xilinx; diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_prod.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_prod.vhd new file mode 100755 index 0000000..246b568 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/example_design/SweepConfigMem_prod.vhd @@ -0,0 +1,277 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- Filename: SweepConfigMem_prod.vhd +-- +-- Description: +-- This is the top-level BMG wrapper (over BMG core). +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-- Configured Core Parameter Values: +-- (Refer to the SIM Parameters table in the datasheet for more information on +-- the these parameters.) +-- C_FAMILY : spartan6 +-- C_XDEVICEFAMILY : spartan6 +-- C_INTERFACE_TYPE : 0 +-- C_ENABLE_32BIT_ADDRESS : 0 +-- C_AXI_TYPE : 1 +-- C_AXI_SLAVE_TYPE : 0 +-- C_AXI_ID_WIDTH : 4 +-- C_MEM_TYPE : 1 +-- C_BYTE_SIZE : 9 +-- C_ALGORITHM : 1 +-- C_PRIM_TYPE : 1 +-- C_LOAD_INIT_FILE : 0 +-- C_INIT_FILE_NAME : no_coe_file_loaded +-- C_USE_DEFAULT_DATA : 0 +-- C_DEFAULT_DATA : 0 +-- C_RST_TYPE : SYNC +-- C_HAS_RSTA : 0 +-- C_RST_PRIORITY_A : CE +-- C_RSTRAM_A : 0 +-- C_INITA_VAL : 0 +-- C_HAS_ENA : 1 +-- C_HAS_REGCEA : 0 +-- C_USE_BYTE_WEA : 0 +-- C_WEA_WIDTH : 1 +-- C_WRITE_MODE_A : WRITE_FIRST +-- C_WRITE_WIDTH_A : 96 +-- C_READ_WIDTH_A : 96 +-- C_WRITE_DEPTH_A : 4501 +-- C_READ_DEPTH_A : 4501 +-- C_ADDRA_WIDTH : 13 +-- C_HAS_RSTB : 0 +-- C_RST_PRIORITY_B : CE +-- C_RSTRAM_B : 0 +-- C_INITB_VAL : 0 +-- C_HAS_ENB : 0 +-- C_HAS_REGCEB : 0 +-- C_USE_BYTE_WEB : 0 +-- C_WEB_WIDTH : 1 +-- C_WRITE_MODE_B : WRITE_FIRST +-- C_WRITE_WIDTH_B : 96 +-- C_READ_WIDTH_B : 96 +-- C_WRITE_DEPTH_B : 4501 +-- C_READ_DEPTH_B : 4501 +-- C_ADDRB_WIDTH : 13 +-- C_HAS_MEM_OUTPUT_REGS_A : 0 +-- C_HAS_MEM_OUTPUT_REGS_B : 0 +-- C_HAS_MUX_OUTPUT_REGS_A : 0 +-- C_HAS_MUX_OUTPUT_REGS_B : 0 +-- C_HAS_SOFTECC_INPUT_REGS_A : 0 +-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 +-- C_MUX_PIPELINE_STAGES : 0 +-- C_USE_ECC : 0 +-- C_USE_SOFTECC : 0 +-- C_HAS_INJECTERR : 0 +-- C_SIM_COLLISION_CHECK : ALL +-- C_COMMON_CLK : 0 +-- C_DISABLE_WARN_BHV_COLL : 0 +-- C_DISABLE_WARN_BHV_RANGE : 0 + +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY SweepConfigMem_prod IS + PORT ( + --Port A + CLKA : IN STD_LOGIC; + RSTA : IN STD_LOGIC; --opt port + ENA : IN STD_LOGIC; --optional port + REGCEA : IN STD_LOGIC; --optional port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + + --Port B + CLKB : IN STD_LOGIC; + RSTB : IN STD_LOGIC; --opt port + ENB : IN STD_LOGIC; --optional port + REGCEB : IN STD_LOGIC; --optional port + WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DINB : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + + --ECC + INJECTSBITERR : IN STD_LOGIC; --optional port + INJECTDBITERR : IN STD_LOGIC; --optional port + SBITERR : OUT STD_LOGIC; --optional port + DBITERR : OUT STD_LOGIC; --optional port + RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); --optional port + -- AXI BMG Input and Output Port Declarations + + -- AXI Global Signals + S_ACLK : IN STD_LOGIC; + S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + + -- AXI Full/Lite Slave Read (Write side) + S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + + -- AXI Full/Lite Sideband Signals + S_AXI_INJECTSBITERR : IN STD_LOGIC; + S_AXI_INJECTDBITERR : IN STD_LOGIC; + S_AXI_SBITERR : OUT STD_LOGIC; + S_AXI_DBITERR : OUT STD_LOGIC; + S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(12 DOWNTO 0); + S_ARESETN : IN STD_LOGIC + + + ); + +END SweepConfigMem_prod; + + +ARCHITECTURE xilinx OF SweepConfigMem_prod IS + + COMPONENT SweepConfigMem_exdes IS + PORT ( + --Port A + ENA : IN STD_LOGIC; --opt port + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + CLKB : IN STD_LOGIC + + + + ); + END COMPONENT; + +BEGIN + + bmg0 : SweepConfigMem_exdes + PORT MAP ( + --Port A + ENA => ENA, + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA, + + --Port B + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB + + + + ); +END xilinx; diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_synth.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_synth.vhd new file mode 100755 index 0000000..9404e23 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_synth.vhd @@ -0,0 +1,329 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Synthesizable Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: SweepConfigMem_synth.vhd +-- +-- Description: +-- Synthesizable Testbench +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +--LIBRARY unisim; +--USE unisim.vcomponents.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + +ENTITY SweepConfigMem_synth IS +PORT( + CLK_IN : IN STD_LOGIC; + CLKB_IN : IN STD_LOGIC; + RESET_IN : IN STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA + ); +END ENTITY; + +ARCHITECTURE SweepConfigMem_synth_ARCH OF SweepConfigMem_synth IS + + +COMPONENT SweepConfigMem_exdes + PORT ( + --Inputs - Port A + ENA : IN STD_LOGIC; --opt port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(95 DOWNTO 0); + CLKA : IN STD_LOGIC; + + --Inputs - Port B + ADDRB : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(95 DOWNTO 0); + CLKB : IN STD_LOGIC + + ); + +END COMPONENT; + + + SIGNAL CLKA: STD_LOGIC := '0'; + SIGNAL RSTA: STD_LOGIC := '0'; + SIGNAL ENA: STD_LOGIC := '0'; + SIGNAL ENA_R: STD_LOGIC := '0'; + SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA: STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_R: STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0'); + SIGNAL CLKB: STD_LOGIC := '0'; + SIGNAL RSTB: STD_LOGIC := '0'; + SIGNAL ADDRB: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRB_R: STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DOUTB: STD_LOGIC_VECTOR(95 DOWNTO 0); + SIGNAL CHECKER_EN : STD_LOGIC:='0'; + SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; + SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); + SIGNAL clk_in_i: STD_LOGIC; + + SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; + + SIGNAL clkb_in_i: STD_LOGIC; + SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; + SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; + SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; + SIGNAL ITER_R0 : STD_LOGIC := '0'; + SIGNAL ITER_R1 : STD_LOGIC := '0'; + SIGNAL ITER_R2 : STD_LOGIC := '0'; + + SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + + BEGIN + +-- clk_buf: bufg +-- PORT map( +-- i => CLK_IN, +-- o => clk_in_i +-- ); + clk_in_i <= CLK_IN; + CLKA <= clk_in_i; + +-- clkb_buf: bufg +-- PORT map( +-- i => CLKB_IN, +-- o => clkb_in_i +-- ); + clkb_in_i <= CLKB_IN; + CLKB <= clkb_in_i; + RSTA <= RESET_SYNC_R3 AFTER 50 ns; + + + PROCESS(clk_in_i) + BEGIN + IF(RISING_EDGE(clk_in_i)) THEN + RESET_SYNC_R1 <= RESET_IN; + RESET_SYNC_R2 <= RESET_SYNC_R1; + RESET_SYNC_R3 <= RESET_SYNC_R2; + END IF; + END PROCESS; + + RSTB <= RESETB_SYNC_R3 AFTER 50 ns; + + PROCESS(clkb_in_i) + BEGIN + IF(RISING_EDGE(clkb_in_i)) THEN + RESETB_SYNC_R1 <= RESET_IN; + RESETB_SYNC_R2 <= RESETB_SYNC_R1; + RESETB_SYNC_R3 <= RESETB_SYNC_R2; + END IF; + END PROCESS; + +PROCESS(CLKA) +BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ISSUE_FLAG_STATUS<= (OTHERS => '0'); + ELSE + ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; + END IF; + END IF; +END PROCESS; + +STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; + + + + + BMG_DATA_CHECKER_INST: ENTITY work.CHECKER + GENERIC MAP ( + WRITE_WIDTH => 96, + READ_WIDTH => 96 ) + PORT MAP ( + CLK => clkb_in_i, + RST => RSTB, + EN => CHECKER_EN_R, + DATA_IN => DOUTB, + STATUS => ISSUE_FLAG(0) + ); + + PROCESS(clkb_in_i) + BEGIN + IF(RISING_EDGE(clkb_in_i)) THEN + IF(RSTB='1') THEN + CHECKER_EN_R <= '0'; + ELSE + CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN + PORT MAP( + CLKA => clk_in_i, + CLKB => clkb_in_i, + TB_RST => RSTA, + ADDRA => ADDRA, + DINA => DINA, + ENA => ENA, + WEA => WEA, + ADDRB => ADDRB, + CHECK_DATA => CHECKER_EN + ); + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STATUS(8) <= '0'; + iter_r2 <= '0'; + iter_r1 <= '0'; + iter_r0 <= '0'; + ELSE + STATUS(8) <= iter_r2; + iter_r2 <= iter_r1; + iter_r1 <= iter_r0; + iter_r0 <= STIMULUS_FLOW(8); + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STIMULUS_FLOW <= (OTHERS => '0'); + ELSIF(WEA(0)='1') THEN + STIMULUS_FLOW <= STIMULUS_FLOW+1; + END IF; + END IF; + END PROCESS; + + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ENA_R <= '0' AFTER 50 ns; + WEA_R <= (OTHERS=>'0') AFTER 50 ns; + DINA_R <= (OTHERS=>'0') AFTER 50 ns; + + + ELSE + ENA_R <= ENA AFTER 50 ns; + WEA_R <= WEA AFTER 50 ns; + DINA_R <= DINA AFTER 50 ns; + + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; + ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; + ELSE + ADDRA_R <= ADDRA AFTER 50 ns; + ADDRB_R <= ADDRB AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_PORT: SweepConfigMem_exdes PORT MAP ( + --Port A + ENA => ENA_R, + WEA => WEA_R, + ADDRA => ADDRA_R, + DINA => DINA_R, + CLKA => CLKA, + --Port B + ADDRB => ADDRB_R, + DOUTB => DOUTB, + CLKB => CLKB + + ); +END ARCHITECTURE; diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_tb.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_tb.vhd new file mode 100755 index 0000000..2b09608 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/SweepConfigMem_tb.vhd @@ -0,0 +1,142 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- Filename: SweepConfigMem_tb.vhd +-- Description: +-- Testbench Top +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY SweepConfigMem_tb IS +END ENTITY; + + +ARCHITECTURE SweepConfigMem_tb_ARCH OF SweepConfigMem_tb IS + SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL CLK : STD_LOGIC := '1'; + SIGNAL CLKB : STD_LOGIC := '1'; + SIGNAL RESET : STD_LOGIC; + + BEGIN + + + CLK_GEN: PROCESS BEGIN + CLK <= NOT CLK; + WAIT FOR 100 NS; + CLK <= NOT CLK; + WAIT FOR 100 NS; + END PROCESS; + CLKB_GEN: PROCESS BEGIN + CLKB <= NOT CLKB; + WAIT FOR 100 NS; + CLKB <= NOT CLKB; + WAIT FOR 100 NS; + END PROCESS; + + RST_GEN: PROCESS BEGIN + RESET <= '1'; + WAIT FOR 1000 NS; + RESET <= '0'; + WAIT; + END PROCESS; + + +--STOP_SIM: PROCESS BEGIN +-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS +-- ASSERT FALSE +-- REPORT "END SIMULATION TIME REACHED" +-- SEVERITY FAILURE; +--END PROCESS; +-- +PROCESS BEGIN + WAIT UNTIL STATUS(8)='1'; + IF( STATUS(7 downto 0)/="0") THEN + ASSERT false + REPORT "Test Completed Successfully" + SEVERITY NOTE; + REPORT "Simulation Failed" + SEVERITY FAILURE; + ELSE + ASSERT false + REPORT "TEST PASS" + SEVERITY NOTE; + REPORT "Test Completed Successfully" + SEVERITY FAILURE; + END IF; + +END PROCESS; + + SweepConfigMem_synth_inst:ENTITY work.SweepConfigMem_synth + PORT MAP( + CLK_IN => CLK, + CLKB_IN => CLK, + RESET_IN => RESET, + STATUS => STATUS + ); + +END ARCHITECTURE; diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/addr_gen.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/addr_gen.vhd new file mode 100755 index 0000000..62706ca --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/addr_gen.vhd @@ -0,0 +1,117 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Address Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: addr_gen.vhd +-- +-- Description: +-- Address Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY ADDR_GEN IS + GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ; + RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0'); + RST_INC : INTEGER := 0); + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + LOAD :IN STD_LOGIC; + LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0'); + ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR + ); +END ADDR_GEN; + +ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS + SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0'); +BEGIN + ADDR_OUT <= ADDR_TEMP; + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + IF(EN='1') THEN + IF(LOAD='1') THEN + ADDR_TEMP <=LOAD_VALUE; + ELSE + IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + ADDR_TEMP <= ADDR_TEMP + '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE; diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_stim_gen.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_stim_gen.vhd new file mode 100755 index 0000000..461f496 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_stim_gen.vhd @@ -0,0 +1,436 @@ + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_stim_gen.vhd +-- +-- Description: +-- Stimulus Generation For SDP Configuration +-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the +-- simulation ends +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + + LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY REGISTER_LOGIC IS + PORT( + Q : OUT STD_LOGIC; + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + D : IN STD_LOGIC + ); +END REGISTER_LOGIC; + +ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS +SIGNAL Q_O : STD_LOGIC :='0'; +BEGIN + Q <= Q_O; + FF_BEH: PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST ='1') THEN + Q_O <= '0'; + ELSE + Q_O <= D; + END IF; + END IF; + END PROCESS; +END REGISTER_ARCH; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY BMG_STIM_GEN IS + PORT ( + CLKA : IN STD_LOGIC; + CLKB : IN STD_LOGIC; + TB_RST : IN STD_LOGIC; + ADDRA: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0'); + DINA : OUT STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0'); + ENA : OUT STD_LOGIC :='0'; + WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0'); + ADDRB: OUT STD_LOGIC_VECTOR(12 DOWNTO 0) := (OTHERS => '0'); + CHECK_DATA: OUT STD_LOGIC:='0' + ); +END BMG_STIM_GEN; + + +ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS + +CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL DINA_INT : STD_LOGIC_VECTOR(95 DOWNTO 0) := (OTHERS => '0'); +SIGNAL DO_WRITE : STD_LOGIC := '0'; +SIGNAL DO_READ : STD_LOGIC := '0'; +SIGNAL DO_READ_R : STD_LOGIC := '0'; +SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0'); +SIGNAL PORTA_WR : STD_LOGIC:='0'; +SIGNAL COUNT : INTEGER :=0; +SIGNAL INCR_WR_CNT : STD_LOGIC:='0'; +SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0'; +SIGNAL PORTB_RD : STD_LOGIC:='0'; +SIGNAL COUNT_RD : INTEGER :=0; +SIGNAL INCR_RD_CNT : STD_LOGIC:='0'; +SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0'; +SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0'; +SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0'; +SIGNAL PORTA_WR_L1 :STD_LOGIC := '0'; +SIGNAL PORTA_WR_L2 :STD_LOGIC := '0'; +SIGNAL PORTB_RD_R2 :STD_LOGIC := '0'; +SIGNAL PORTB_RD_R1 :STD_LOGIC := '0'; +SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0'; +SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0'; +SIGNAL PORTB_RD_L1 : STD_LOGIC := '0'; +SIGNAL PORTB_RD_L2 : STD_LOGIC := '0'; +SIGNAL PORTA_WR_R2 : STD_LOGIC := '0'; +SIGNAL PORTA_WR_R1 : STD_LOGIC := '0'; + +CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8; +CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((13 <= 13),WR_RD_DEEP_COUNT, + ((96/96)*WR_RD_DEEP_COUNT)); +CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((13 <= 13),WR_RD_DEEP_COUNT, + ((96/96)*WR_RD_DEEP_COUNT)); + +BEGIN + + ADDRA <= WRITE_ADDR(12 DOWNTO 0) ; + DINA <= DINA_INT ; + ADDRB <= READ_ADDR(12 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0'); + CHECK_DATA <= DO_READ; + + RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 4501 , + RST_INC => 1 ) + PORT MAP( + CLK => CLKB, + RST => TB_RST, + EN => DO_READ, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => READ_ADDR + ); + + WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 4501, + RST_INC => 1 ) + PORT MAP( + CLK => CLKA, + RST => TB_RST, + EN => DO_WRITE, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => WRITE_ADDR + ); + + WR_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( + DATA_GEN_WIDTH => 96, + DOUT_WIDTH => 96 , + DATA_PART_CNT => 1, + SEED => 2) + PORT MAP ( + CLK => CLKA, + RST => TB_RST, + EN => DO_WRITE, + DATA_OUT => DINA_INT + ); + + + PORTA_WR_PROCESS: PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + PORTA_WR<='1'; + ELSE + PORTA_WR<=PORTB_RD_COMPLETE; + END IF; + END IF; + END PROCESS; + + PORTB_RD_PROCESS: PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + PORTB_RD<='0'; + ELSE + PORTB_RD<=PORTA_WR_L2; + END IF; + END IF; + END PROCESS; + + PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + LATCH_PORTB_RD_COMPLETE<='0'; + ELSIF(PORTB_RD_COMPLETE='1') THEN + LATCH_PORTB_RD_COMPLETE <='1'; + ELSIF(PORTA_WR_HAPPENED='1') THEN + LATCH_PORTB_RD_COMPLETE<='0'; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + PORTB_RD_L1 <='0'; + PORTB_RD_L2 <='0'; + ELSE + PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE; + PORTB_RD_L2 <= PORTB_RD_L1; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + PORTA_WR_R1 <='0'; + PORTA_WR_R2 <='0'; + ELSE + PORTA_WR_R1 <= PORTA_WR; + PORTA_WR_R2 <= PORTA_WR_R1; + END IF; + END IF; + END PROCESS; + + PORTA_WR_HAPPENED <= PORTA_WR_R2; + + PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + LATCH_PORTA_WR_COMPLETE<='0'; + ELSIF(PORTA_WR_COMPLETE='1') THEN + LATCH_PORTA_WR_COMPLETE <='1'; + --ELSIF(PORTB_RD_HAPPENED='1') THEN + ELSE + LATCH_PORTA_WR_COMPLETE<='0'; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + PORTA_WR_L1 <='0'; + PORTA_WR_L2 <='0'; + ELSE + PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE; + PORTA_WR_L2 <= PORTA_WR_L1; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + PORTB_RD_R1 <='0'; + PORTB_RD_R2 <='0'; + ELSE + PORTB_RD_R1 <= PORTB_RD; + PORTB_RD_R2 <= PORTB_RD_R1; + END IF; + END IF; + END PROCESS; + + PORTB_RD_HAPPENED <= PORTB_RD_R2; + + PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0'; + + start_rd_counter: process(clkb) + begin + if(rising_edge(clkb)) then + if(tb_rst='1') then + incr_rd_cnt <= '0'; + elsif(portb_rd ='1') then + incr_rd_cnt <='1'; + elsif(portb_rd_complete='1') then + incr_rd_cnt <='0'; + end if; + end if; + end process; + + RD_COUNTER: process(clkb) + begin + if(rising_edge(clkb)) then + if(tb_rst='1') then + count_rd <= 0; + elsif(incr_rd_cnt='1') then + count_rd<=count_rd+1; + end if; + --if(count_rd=(wr_rd_deep_count)) then + if(count_rd=(RD_DEEP_COUNT)) then + count_rd<=0; + end if; + end if; + end process; + + DO_READ<='1' when (count_rd DO_READ_REG(0), + CLK => CLKB, + RST => TB_RST, + D => DO_READ + ); + END GENERATE DFF_RIGHT; + + DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE + BEGIN + SHIFT_INST: ENTITY work.REGISTER_LOGIC + PORT MAP( + Q => DO_READ_REG(I), + CLK =>CLKB, + RST =>TB_RST, + D =>DO_READ_REG(I-1) + ); + END GENERATE DFF_OTHERS; + END GENERATE BEGIN_SHIFT_REG; + + REGCE_PROCESS: PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + DO_READ_R <= '0'; + ELSE + DO_READ_R <= DO_READ; + END IF; + END IF; + END PROCESS; + + + ENA <= DO_WRITE ; + + WEA(0) <= DO_WRITE ; + + +END ARCHITECTURE; + + + + + diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_tb_pkg.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_tb_pkg.vhd new file mode 100755 index 0000000..4928909 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/bmg_tb_pkg.vhd @@ -0,0 +1,200 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Testbench Package +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_tb_pkg.vhd +-- +-- Description: +-- BMG Testbench Package files +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE :STRING) + RETURN STRING; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE :STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER; + +END BMG_TB_PKG; + +PACKAGE BODY BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER IS + VARIABLE DIV : INTEGER; + BEGIN + DIV := DATA_VALUE/DIVISOR; + IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN + DIV := DIV+1; + END IF; + RETURN DIV; + END DIVROUNDUP; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE : STD_LOGIC) + RETURN STD_LOGIC IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER IS + VARIABLE RETVAL : INTEGER := 0; + BEGIN + IF CONDITION=FALSE THEN + RETVAL:=FALSE_CASE; + ELSE + RETVAL:=TRUE_CASE; + END IF; + RETURN RETVAL; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE : STRING) + RETURN STRING IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + ------------------------------- + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER IS + VARIABLE WIDTH : INTEGER := 0; + VARIABLE CNT : INTEGER := 1; + BEGIN + IF (DATA_VALUE <= 1) THEN + WIDTH := 1; + ELSE + WHILE (CNT < DATA_VALUE) LOOP + WIDTH := WIDTH + 1; + CNT := CNT *2; + END LOOP; + END IF; + RETURN WIDTH; + END LOG2ROUNDUP; + +END BMG_TB_PKG; diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/checker.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/checker.vhd new file mode 100755 index 0000000..15a2753 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/checker.vhd @@ -0,0 +1,161 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Checker +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: checker.vhd +-- +-- Description: +-- Checker +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY CHECKER IS + GENERIC ( WRITE_WIDTH : INTEGER :=32; + READ_WIDTH : INTEGER :=32 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR + STATUS : OUT STD_LOGIC:= '0' + ); +END CHECKER; + +ARCHITECTURE CHECKER_ARCH OF CHECKER IS + SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL EN_R : STD_LOGIC := '0'; + SIGNAL EN_2R : STD_LOGIC := '0'; +--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT +--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) +--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) + CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); + CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); + SIGNAL ERR_HOLD : STD_LOGIC :='0'; + SIGNAL ERR_DET : STD_LOGIC :='0'; +BEGIN + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST= '1') THEN + EN_R <= '0'; + EN_2R <= '0'; + DATA_IN_R <= (OTHERS=>'0'); + ELSE + EN_R <= EN; + EN_2R <= EN_R; + DATA_IN_R <= DATA_IN; + END IF; + END IF; + END PROCESS; + + EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, + DOUT_WIDTH => READ_WIDTH, + DATA_PART_CNT => DATA_PART_CNT, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => EN_2R, + DATA_OUT => EXPECTED_DATA + ); + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(EN_2R='1') THEN + IF(EXPECTED_DATA = DATA_IN_R) THEN + ERR_DET<='0'; + ELSE + ERR_DET<= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(CLK,RST) + BEGIN + IF(RST='1') THEN + ERR_HOLD <= '0'; + ELSIF(RISING_EDGE(CLK)) THEN + ERR_HOLD <= ERR_HOLD OR ERR_DET ; + END IF; + END PROCESS; + + STATUS <= ERR_HOLD; + +END ARCHITECTURE; + + + diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/data_gen.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/data_gen.vhd new file mode 100755 index 0000000..fe3dca7 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/data_gen.vhd @@ -0,0 +1,140 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Data Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: data_gen.vhd +-- +-- Description: +-- Data Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY DATA_GEN IS + GENERIC ( DATA_GEN_WIDTH : INTEGER := 32; + DOUT_WIDTH : INTEGER := 32; + DATA_PART_CNT : INTEGER := 1; + SEED : INTEGER := 2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END DATA_GEN; + +ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS + CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8); + SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0); + SIGNAL LOCAL_CNT : INTEGER :=1; + SIGNAL DATA_GEN_I : STD_LOGIC :='0'; +BEGIN + + LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0); + DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH)); + DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN; + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE (CLK)) THEN + IF(EN ='1' AND (DATA_PART_CNT =1)) THEN + LOCAL_CNT <=1; + ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN + IF(LOCAL_CNT = 1) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSE + LOCAL_CNT <= 1; + END IF; + ELSE + LOCAL_CNT <= 1; + END IF; + END IF; + END PROCESS; + + RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + RAND_GEN_INST:ENTITY work.RANDOM + GENERIC MAP( + WIDTH => 8, + SEED => (SEED+N) + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DATA_GEN_I, + RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N) + ); + END GENERATE RAND_GEN; + +END ARCHITECTURE; + diff --git a/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/random.vhd b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/random.vhd new file mode 100755 index 0000000..b0d417c --- /dev/null +++ b/FPGA/Generator/ipcore_dir/SweepConfigMem/simulation/random.vhd @@ -0,0 +1,112 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Random Number Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: random.vhd +-- +-- Description: +-- Random Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + + +ENTITY RANDOM IS + GENERIC ( WIDTH : INTEGER := 32; + SEED : INTEGER :=2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END RANDOM; + +ARCHITECTURE BEHAVIORAL OF RANDOM IS +BEGIN + PROCESS(CLK) + VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + VARIABLE TEMP : STD_LOGIC := '0'; + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + ELSE + IF(EN = '1') THEN + TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2); + RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0); + RAND_TEMP(0) := TEMP; + END IF; + END IF; + END IF; + RANDOM_NUM <= RAND_TEMP; + END PROCESS; +END ARCHITECTURE; diff --git a/FPGA/Generator/ipcore_dir/VCO_Mem.gise b/FPGA/Generator/ipcore_dir/VCO_Mem.gise new file mode 100644 index 0000000..f48f6b8 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/VCO_Mem.gise @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/VCO_Mem.vhd b/FPGA/Generator/ipcore_dir/VCO_Mem.vhd new file mode 100644 index 0000000..007952b --- /dev/null +++ b/FPGA/Generator/ipcore_dir/VCO_Mem.vhd @@ -0,0 +1,149 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2022 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file VCO_Mem.vhd when simulating +-- the core, VCO_Mem. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY VCO_Mem IS + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END VCO_Mem; + +ARCHITECTURE VCO_Mem_a OF VCO_Mem IS +-- synthesis translate_off +COMPONENT wrapped_VCO_Mem + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_VCO_Mem USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) + GENERIC MAP ( + c_addra_width => 6, + c_addrb_width => 6, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan6", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file => "BlankString", + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 1, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 64, + c_read_depth_b => 64, + c_read_width_a => 16, + c_read_width_b => 16, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_bram_block => 0, + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 64, + c_write_depth_b => 64, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 16, + c_write_width_b => 16, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_VCO_Mem + PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + addrb => addrb, + doutb => doutb + ); +-- synthesis translate_on + +END VCO_Mem_a; diff --git a/FPGA/Generator/ipcore_dir/result_bram.gise b/FPGA/Generator/ipcore_dir/result_bram.gise new file mode 100644 index 0000000..68f663b --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram.gise @@ -0,0 +1,32 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/result_bram.vhd b/FPGA/Generator/ipcore_dir/result_bram.vhd new file mode 100644 index 0000000..1aa01e9 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram.vhd @@ -0,0 +1,149 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2020 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file result_bram.vhd when simulating +-- the core, result_bram. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY result_bram IS + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0) + ); +END result_bram; + +ARCHITECTURE result_bram_a OF result_bram IS +-- synthesis translate_off +COMPONENT wrapped_result_bram + PORT ( + clka : IN STD_LOGIC; + wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0); + clkb : IN STD_LOGIC; + addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_result_bram USE ENTITY XilinxCoreLib.blk_mem_gen_v7_3(behavioral) + GENERIC MAP ( + c_addra_width => 8, + c_addrb_width => 8, + c_algorithm => 1, + c_axi_id_width => 4, + c_axi_slave_type => 0, + c_axi_type => 1, + c_byte_size => 9, + c_common_clk => 0, + c_default_data => "0", + c_disable_warn_bhv_coll => 0, + c_disable_warn_bhv_range => 0, + c_enable_32bit_address => 0, + c_family => "spartan6", + c_has_axi_id => 0, + c_has_ena => 0, + c_has_enb => 0, + c_has_injecterr => 0, + c_has_mem_output_regs_a => 0, + c_has_mem_output_regs_b => 0, + c_has_mux_output_regs_a => 0, + c_has_mux_output_regs_b => 0, + c_has_regcea => 0, + c_has_regceb => 0, + c_has_rsta => 0, + c_has_rstb => 0, + c_has_softecc_input_regs_a => 0, + c_has_softecc_output_regs_b => 0, + c_init_file => "BlankString", + c_init_file_name => "no_coe_file_loaded", + c_inita_val => "0", + c_initb_val => "0", + c_interface_type => 0, + c_load_init_file => 0, + c_mem_type => 1, + c_mux_pipeline_stages => 0, + c_prim_type => 1, + c_read_depth_a => 256, + c_read_depth_b => 256, + c_read_width_a => 192, + c_read_width_b => 192, + c_rst_priority_a => "CE", + c_rst_priority_b => "CE", + c_rst_type => "SYNC", + c_rstram_a => 0, + c_rstram_b => 0, + c_sim_collision_check => "ALL", + c_use_bram_block => 0, + c_use_byte_wea => 0, + c_use_byte_web => 0, + c_use_default_data => 0, + c_use_ecc => 0, + c_use_softecc => 0, + c_wea_width => 1, + c_web_width => 1, + c_write_depth_a => 256, + c_write_depth_b => 256, + c_write_mode_a => "WRITE_FIRST", + c_write_mode_b => "WRITE_FIRST", + c_write_width_a => 192, + c_write_width_b => 192, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_result_bram + PORT MAP ( + clka => clka, + wea => wea, + addra => addra, + dina => dina, + clkb => clkb, + addrb => addrb, + doutb => doutb + ); +-- synthesis translate_on + +END result_bram_a; diff --git a/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.ucf b/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.ucf new file mode 100755 index 0000000..3762632 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.ucf @@ -0,0 +1,61 @@ +################################################################################ +# +# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved. +# +# This file contains confidential and proprietary information +# of Xilinx, Inc. and is protected under U.S. and +# international copyright and other intellectual property +# laws. +# +# DISCLAIMER +# This disclaimer is not a license and does not grant any +# rights to the materials distributed herewith. Except as +# otherwise provided in a valid license issued to you by +# Xilinx, and to the maximum extent permitted by applicable +# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +# (2) Xilinx shall not be liable (whether in contract or tort, +# including negligence, or under any other theory of +# liability) for any loss or damage of any kind or nature +# related to, arising under or in connection with these +# materials, including for any direct, or any indirect, +# special, incidental, or consequential loss or damage +# (including loss of data, profits, goodwill, or any type of +# loss or damage suffered as a result of any action brought +# by a third party) even if such damage or loss was +# reasonably foreseeable or Xilinx had been advised of the +# possibility of the same. +# +# CRITICAL APPLICATIONS +# Xilinx products are not designed or intended to be fail- +# safe, or for use in any application requiring fail-safe +# performance, such as life-support or safety devices or +# systems, Class III medical devices, nuclear facilities, +# applications related to the deployment of airbags, or any +# other applications that could lead to death, personal +# injury, or severe property or environmental damage +# (individually and collectively, "Critical +# Applications"). Customer assumes the sole risk and +# liability of any use of Xilinx products in Critical +# Applications, subject only to applicable laws and +# regulations governing limitations on product liability. +# +# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +# PART OF THIS FILE AT ALL TIMES. +# +################################################################################ + +# Tx Core Period Constraint. This constraint can be modified, and is +# valid as long as it is met after place and route. +NET "CLKA" TNM_NET = "CLKA"; + +NET "CLKB" TNM_NET = "CLKB"; + +TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ; + +TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ; + +################################################################################ diff --git a/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.vhd b/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.vhd new file mode 100755 index 0000000..8e416e0 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_exdes.vhd @@ -0,0 +1,179 @@ + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level core wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: result_bram_exdes.vhd +-- +-- Description: +-- This is the actual BMG core wrapper. +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY result_bram_exdes IS + PORT ( + --Inputs - Port A + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0); + + CLKA : IN STD_LOGIC; + + + --Inputs - Port B + ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0); + CLKB : IN STD_LOGIC + + ); + +END result_bram_exdes; + + +ARCHITECTURE xilinx OF result_bram_exdes IS + + COMPONENT BUFG IS + PORT ( + I : IN STD_ULOGIC; + O : OUT STD_ULOGIC + ); + END COMPONENT; + + COMPONENT result_bram IS + PORT ( + --Port A + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0); + CLKB : IN STD_LOGIC + + + ); + END COMPONENT; + + SIGNAL CLKA_buf : STD_LOGIC; + SIGNAL CLKB_buf : STD_LOGIC; + SIGNAL S_ACLK_buf : STD_LOGIC; + +BEGIN + + bufg_A : BUFG + PORT MAP ( + I => CLKA, + O => CLKA_buf + ); + + bufg_B : BUFG + PORT MAP ( + I => CLKB, + O => CLKB_buf + ); + + + bmg0 : result_bram + PORT MAP ( + --Port A + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA_buf, + + + --Port B + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB_buf + + ); + +END xilinx; diff --git a/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_prod.vhd b/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_prod.vhd new file mode 100755 index 0000000..6728031 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/example_design/result_bram_prod.vhd @@ -0,0 +1,275 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7.1 Core - Top-level wrapper +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. +-- +-------------------------------------------------------------------------------- +-- +-- Filename: result_bram_prod.vhd +-- +-- Description: +-- This is the top-level BMG wrapper (over BMG core). +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: August 31, 2005 - First Release +-------------------------------------------------------------------------------- +-- +-- Configured Core Parameter Values: +-- (Refer to the SIM Parameters table in the datasheet for more information on +-- the these parameters.) +-- C_FAMILY : spartan6 +-- C_XDEVICEFAMILY : spartan6 +-- C_INTERFACE_TYPE : 0 +-- C_ENABLE_32BIT_ADDRESS : 0 +-- C_AXI_TYPE : 1 +-- C_AXI_SLAVE_TYPE : 0 +-- C_AXI_ID_WIDTH : 4 +-- C_MEM_TYPE : 1 +-- C_BYTE_SIZE : 9 +-- C_ALGORITHM : 1 +-- C_PRIM_TYPE : 1 +-- C_LOAD_INIT_FILE : 0 +-- C_INIT_FILE_NAME : no_coe_file_loaded +-- C_USE_DEFAULT_DATA : 0 +-- C_DEFAULT_DATA : 0 +-- C_RST_TYPE : SYNC +-- C_HAS_RSTA : 0 +-- C_RST_PRIORITY_A : CE +-- C_RSTRAM_A : 0 +-- C_INITA_VAL : 0 +-- C_HAS_ENA : 0 +-- C_HAS_REGCEA : 0 +-- C_USE_BYTE_WEA : 0 +-- C_WEA_WIDTH : 1 +-- C_WRITE_MODE_A : WRITE_FIRST +-- C_WRITE_WIDTH_A : 192 +-- C_READ_WIDTH_A : 192 +-- C_WRITE_DEPTH_A : 256 +-- C_READ_DEPTH_A : 256 +-- C_ADDRA_WIDTH : 8 +-- C_HAS_RSTB : 0 +-- C_RST_PRIORITY_B : CE +-- C_RSTRAM_B : 0 +-- C_INITB_VAL : 0 +-- C_HAS_ENB : 0 +-- C_HAS_REGCEB : 0 +-- C_USE_BYTE_WEB : 0 +-- C_WEB_WIDTH : 1 +-- C_WRITE_MODE_B : WRITE_FIRST +-- C_WRITE_WIDTH_B : 192 +-- C_READ_WIDTH_B : 192 +-- C_WRITE_DEPTH_B : 256 +-- C_READ_DEPTH_B : 256 +-- C_ADDRB_WIDTH : 8 +-- C_HAS_MEM_OUTPUT_REGS_A : 0 +-- C_HAS_MEM_OUTPUT_REGS_B : 0 +-- C_HAS_MUX_OUTPUT_REGS_A : 0 +-- C_HAS_MUX_OUTPUT_REGS_B : 0 +-- C_HAS_SOFTECC_INPUT_REGS_A : 0 +-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0 +-- C_MUX_PIPELINE_STAGES : 0 +-- C_USE_ECC : 0 +-- C_USE_SOFTECC : 0 +-- C_HAS_INJECTERR : 0 +-- C_SIM_COLLISION_CHECK : ALL +-- C_COMMON_CLK : 0 +-- C_DISABLE_WARN_BHV_COLL : 0 +-- C_DISABLE_WARN_BHV_RANGE : 0 + +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY UNISIM; +USE UNISIM.VCOMPONENTS.ALL; + +-------------------------------------------------------------------------------- +-- Entity Declaration +-------------------------------------------------------------------------------- +ENTITY result_bram_prod IS + PORT ( + --Port A + CLKA : IN STD_LOGIC; + RSTA : IN STD_LOGIC; --opt port + ENA : IN STD_LOGIC; --optional port + REGCEA : IN STD_LOGIC; --optional port + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0); + DOUTA : OUT STD_LOGIC_VECTOR(191 DOWNTO 0); + + --Port B + CLKB : IN STD_LOGIC; + RSTB : IN STD_LOGIC; --opt port + ENB : IN STD_LOGIC; --optional port + REGCEB : IN STD_LOGIC; --optional port + WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DINB : IN STD_LOGIC_VECTOR(191 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0); + + --ECC + INJECTSBITERR : IN STD_LOGIC; --optional port + INJECTDBITERR : IN STD_LOGIC; --optional port + SBITERR : OUT STD_LOGIC; --optional port + DBITERR : OUT STD_LOGIC; --optional port + RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --optional port + -- AXI BMG Input and Output Port Declarations + + -- AXI Global Signals + S_ACLK : IN STD_LOGIC; + S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_AWVALID : IN STD_LOGIC; + S_AXI_AWREADY : OUT STD_LOGIC; + S_AXI_WDATA : IN STD_LOGIC_VECTOR(191 DOWNTO 0); + S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + S_AXI_WLAST : IN STD_LOGIC; + S_AXI_WVALID : IN STD_LOGIC; + S_AXI_WREADY : OUT STD_LOGIC; + S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_BVALID : OUT STD_LOGIC; + S_AXI_BREADY : IN STD_LOGIC; + + -- AXI Full/Lite Slave Read (Write side) + S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0); + S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0); + S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0); + S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_ARVALID : IN STD_LOGIC; + S_AXI_ARREADY : OUT STD_LOGIC; + S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0'); + S_AXI_RDATA : OUT STD_LOGIC_VECTOR(191 DOWNTO 0); + S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); + S_AXI_RLAST : OUT STD_LOGIC; + S_AXI_RVALID : OUT STD_LOGIC; + S_AXI_RREADY : IN STD_LOGIC; + + -- AXI Full/Lite Sideband Signals + S_AXI_INJECTSBITERR : IN STD_LOGIC; + S_AXI_INJECTDBITERR : IN STD_LOGIC; + S_AXI_SBITERR : OUT STD_LOGIC; + S_AXI_DBITERR : OUT STD_LOGIC; + S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); + S_ARESETN : IN STD_LOGIC + + + ); + +END result_bram_prod; + + +ARCHITECTURE xilinx OF result_bram_prod IS + + COMPONENT result_bram_exdes IS + PORT ( + --Port A + + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + + DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0); + + + CLKA : IN STD_LOGIC; + + + --Port B + ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0); + CLKB : IN STD_LOGIC + + + + ); + END COMPONENT; + +BEGIN + + bmg0 : result_bram_exdes + PORT MAP ( + --Port A + + WEA => WEA, + ADDRA => ADDRA, + + DINA => DINA, + + CLKA => CLKA, + + --Port B + ADDRB => ADDRB, + DOUTB => DOUTB, + CLKB => CLKB + + + + ); +END xilinx; diff --git a/FPGA/Generator/ipcore_dir/result_bram/simulation/addr_gen.vhd b/FPGA/Generator/ipcore_dir/result_bram/simulation/addr_gen.vhd new file mode 100755 index 0000000..62706ca --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/simulation/addr_gen.vhd @@ -0,0 +1,117 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Address Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: addr_gen.vhd +-- +-- Description: +-- Address Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY ADDR_GEN IS + GENERIC ( C_MAX_DEPTH : INTEGER := 1024 ; + RST_VALUE : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS=> '0'); + RST_INC : INTEGER := 0); + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + LOAD :IN STD_LOGIC; + LOAD_VALUE : IN STD_LOGIC_VECTOR (31 DOWNTO 0) := (OTHERS => '0'); + ADDR_OUT : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) --OUTPUT VECTOR + ); +END ADDR_GEN; + +ARCHITECTURE BEHAVIORAL OF ADDR_GEN IS + SIGNAL ADDR_TEMP : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS =>'0'); +BEGIN + ADDR_OUT <= ADDR_TEMP; + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + IF(EN='1') THEN + IF(LOAD='1') THEN + ADDR_TEMP <=LOAD_VALUE; + ELSE + IF(ADDR_TEMP = C_MAX_DEPTH-1) THEN + ADDR_TEMP<= RST_VALUE + conv_std_logic_vector(RST_INC,32 ); + ELSE + ADDR_TEMP <= ADDR_TEMP + '1'; + END IF; + END IF; + END IF; + END IF; + END IF; + END PROCESS; +END ARCHITECTURE; diff --git a/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_stim_gen.vhd b/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_stim_gen.vhd new file mode 100755 index 0000000..6fe0a18 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_stim_gen.vhd @@ -0,0 +1,434 @@ + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Stimulus Generator For Simple Dual Port RAM +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_stim_gen.vhd +-- +-- Description: +-- Stimulus Generation For SDP Configuration +-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the +-- simulation ends +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + + LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY REGISTER_LOGIC IS + PORT( + Q : OUT STD_LOGIC; + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + D : IN STD_LOGIC + ); +END REGISTER_LOGIC; + +ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC IS +SIGNAL Q_O : STD_LOGIC :='0'; +BEGIN + Q <= Q_O; + FF_BEH: PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST ='1') THEN + Q_O <= '0'; + ELSE + Q_O <= D; + END IF; + END IF; + END PROCESS; +END REGISTER_ARCH; + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + + +ENTITY BMG_STIM_GEN IS + PORT ( + CLKA : IN STD_LOGIC; + CLKB : IN STD_LOGIC; + TB_RST : IN STD_LOGIC; + ADDRA: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + DINA : OUT STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0'); + WEA : OUT STD_LOGIC_VECTOR (0 DOWNTO 0) := (OTHERS => '0'); + ADDRB: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + CHECK_DATA: OUT STD_LOGIC:='0' + ); +END BMG_STIM_GEN; + + +ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS + +CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL WRITE_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL READ_ADDR : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); +SIGNAL DINA_INT : STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0'); +SIGNAL DO_WRITE : STD_LOGIC := '0'; +SIGNAL DO_READ : STD_LOGIC := '0'; +SIGNAL DO_READ_R : STD_LOGIC := '0'; +SIGNAL DO_READ_REG : STD_LOGIC_VECTOR(5 DOWNTO 0) :=(OTHERS => '0'); +SIGNAL PORTA_WR : STD_LOGIC:='0'; +SIGNAL COUNT : INTEGER :=0; +SIGNAL INCR_WR_CNT : STD_LOGIC:='0'; +SIGNAL PORTA_WR_COMPLETE : STD_LOGIC :='0'; +SIGNAL PORTB_RD : STD_LOGIC:='0'; +SIGNAL COUNT_RD : INTEGER :=0; +SIGNAL INCR_RD_CNT : STD_LOGIC:='0'; +SIGNAL PORTB_RD_COMPLETE : STD_LOGIC :='0'; +SIGNAL LATCH_PORTA_WR_COMPLETE : STD_LOGIC :='0'; +SIGNAL PORTB_RD_HAPPENED : STD_LOGIC := '0'; +SIGNAL PORTA_WR_L1 :STD_LOGIC := '0'; +SIGNAL PORTA_WR_L2 :STD_LOGIC := '0'; +SIGNAL PORTB_RD_R2 :STD_LOGIC := '0'; +SIGNAL PORTB_RD_R1 :STD_LOGIC := '0'; +SIGNAL LATCH_PORTB_RD_COMPLETE : STD_LOGIC :='0'; +SIGNAL PORTA_WR_HAPPENED : STD_LOGIC := '0'; +SIGNAL PORTB_RD_L1 : STD_LOGIC := '0'; +SIGNAL PORTB_RD_L2 : STD_LOGIC := '0'; +SIGNAL PORTA_WR_R2 : STD_LOGIC := '0'; +SIGNAL PORTA_WR_R1 : STD_LOGIC := '0'; + +CONSTANT WR_RD_DEEP_COUNT :INTEGER :=8; +CONSTANT WR_DEEP_COUNT : INTEGER := if_then_else((8 <= 8),WR_RD_DEEP_COUNT, + ((192/192)*WR_RD_DEEP_COUNT)); +CONSTANT RD_DEEP_COUNT : INTEGER := if_then_else((8 <= 8),WR_RD_DEEP_COUNT, + ((192/192)*WR_RD_DEEP_COUNT)); + +BEGIN + + ADDRA <= WRITE_ADDR(7 DOWNTO 0) ; + DINA <= DINA_INT ; + ADDRB <= READ_ADDR(7 DOWNTO 0) when (DO_READ='1') else (OTHERS=>'0'); + CHECK_DATA <= DO_READ; + + RD_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 256 , + RST_INC => 1 ) + PORT MAP( + CLK => CLKB, + RST => TB_RST, + EN => DO_READ, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => READ_ADDR + ); + + WR_ADDR_GEN_INST:ENTITY work.ADDR_GEN + GENERIC MAP( + C_MAX_DEPTH => 256, + RST_INC => 1 ) + PORT MAP( + CLK => CLKA, + RST => TB_RST, + EN => DO_WRITE, + LOAD => '0', + LOAD_VALUE => ZERO, + ADDR_OUT => WRITE_ADDR + ); + + WR_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( + DATA_GEN_WIDTH => 192, + DOUT_WIDTH => 192 , + DATA_PART_CNT => 1, + SEED => 2) + PORT MAP ( + CLK => CLKA, + RST => TB_RST, + EN => DO_WRITE, + DATA_OUT => DINA_INT + ); + + + PORTA_WR_PROCESS: PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + PORTA_WR<='1'; + ELSE + PORTA_WR<=PORTB_RD_COMPLETE; + END IF; + END IF; + END PROCESS; + + PORTB_RD_PROCESS: PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + PORTB_RD<='0'; + ELSE + PORTB_RD<=PORTA_WR_L2; + END IF; + END IF; + END PROCESS; + + PORTB_RD_COMPLETE_LATCH: PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + LATCH_PORTB_RD_COMPLETE<='0'; + ELSIF(PORTB_RD_COMPLETE='1') THEN + LATCH_PORTB_RD_COMPLETE <='1'; + ELSIF(PORTA_WR_HAPPENED='1') THEN + LATCH_PORTB_RD_COMPLETE<='0'; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + PORTB_RD_L1 <='0'; + PORTB_RD_L2 <='0'; + ELSE + PORTB_RD_L1 <= LATCH_PORTB_RD_COMPLETE; + PORTB_RD_L2 <= PORTB_RD_L1; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + PORTA_WR_R1 <='0'; + PORTA_WR_R2 <='0'; + ELSE + PORTA_WR_R1 <= PORTA_WR; + PORTA_WR_R2 <= PORTA_WR_R1; + END IF; + END IF; + END PROCESS; + + PORTA_WR_HAPPENED <= PORTA_WR_R2; + + PORTA_WR_COMPLETE_LATCH: PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + LATCH_PORTA_WR_COMPLETE<='0'; + ELSIF(PORTA_WR_COMPLETE='1') THEN + LATCH_PORTA_WR_COMPLETE <='1'; + --ELSIF(PORTB_RD_HAPPENED='1') THEN + ELSE + LATCH_PORTA_WR_COMPLETE<='0'; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + PORTA_WR_L1 <='0'; + PORTA_WR_L2 <='0'; + ELSE + PORTA_WR_L1 <= LATCH_PORTA_WR_COMPLETE; + PORTA_WR_L2 <= PORTA_WR_L1; + END IF; + END IF; + END PROCESS; + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(TB_RST='1') THEN + PORTB_RD_R1 <='0'; + PORTB_RD_R2 <='0'; + ELSE + PORTB_RD_R1 <= PORTB_RD; + PORTB_RD_R2 <= PORTB_RD_R1; + END IF; + END IF; + END PROCESS; + + PORTB_RD_HAPPENED <= PORTB_RD_R2; + + PORTB_RD_COMPLETE <= '1' when (count_rd=RD_DEEP_COUNT) else '0'; + + start_rd_counter: process(clkb) + begin + if(rising_edge(clkb)) then + if(tb_rst='1') then + incr_rd_cnt <= '0'; + elsif(portb_rd ='1') then + incr_rd_cnt <='1'; + elsif(portb_rd_complete='1') then + incr_rd_cnt <='0'; + end if; + end if; + end process; + + RD_COUNTER: process(clkb) + begin + if(rising_edge(clkb)) then + if(tb_rst='1') then + count_rd <= 0; + elsif(incr_rd_cnt='1') then + count_rd<=count_rd+1; + end if; + --if(count_rd=(wr_rd_deep_count)) then + if(count_rd=(RD_DEEP_COUNT)) then + count_rd<=0; + end if; + end if; + end process; + + DO_READ<='1' when (count_rd DO_READ_REG(0), + CLK => CLKB, + RST => TB_RST, + D => DO_READ + ); + END GENERATE DFF_RIGHT; + + DFF_OTHERS: IF ((I>0) AND (I<=5)) GENERATE + BEGIN + SHIFT_INST: ENTITY work.REGISTER_LOGIC + PORT MAP( + Q => DO_READ_REG(I), + CLK =>CLKB, + RST =>TB_RST, + D =>DO_READ_REG(I-1) + ); + END GENERATE DFF_OTHERS; + END GENERATE BEGIN_SHIFT_REG; + + REGCE_PROCESS: PROCESS(CLKB) + BEGIN + IF(RISING_EDGE(CLKB)) THEN + IF(TB_RST='1') THEN + DO_READ_R <= '0'; + ELSE + DO_READ_R <= DO_READ; + END IF; + END IF; + END PROCESS; + + + + WEA(0) <= DO_WRITE ; + + +END ARCHITECTURE; + + + + + diff --git a/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_tb_pkg.vhd b/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_tb_pkg.vhd new file mode 100755 index 0000000..4928909 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/simulation/bmg_tb_pkg.vhd @@ -0,0 +1,200 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Testbench Package +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: bmg_tb_pkg.vhd +-- +-- Description: +-- BMG Testbench Package files +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +PACKAGE BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE :STRING) + RETURN STRING; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE :STD_LOGIC) + RETURN STD_LOGIC; + ------------------------ + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER; + ------------------------ + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER; + +END BMG_TB_PKG; + +PACKAGE BODY BMG_TB_PKG IS + + FUNCTION DIVROUNDUP ( + DATA_VALUE : INTEGER; + DIVISOR : INTEGER) + RETURN INTEGER IS + VARIABLE DIV : INTEGER; + BEGIN + DIV := DATA_VALUE/DIVISOR; + IF ( (DATA_VALUE MOD DIVISOR) /= 0) THEN + DIV := DIV+1; + END IF; + RETURN DIV; + END DIVROUNDUP; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC_VECTOR; + FALSE_CASE : STD_LOGIC_VECTOR) + RETURN STD_LOGIC_VECTOR IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STD_LOGIC; + FALSE_CASE : STD_LOGIC) + RETURN STD_LOGIC IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : INTEGER; + FALSE_CASE : INTEGER) + RETURN INTEGER IS + VARIABLE RETVAL : INTEGER := 0; + BEGIN + IF CONDITION=FALSE THEN + RETVAL:=FALSE_CASE; + ELSE + RETVAL:=TRUE_CASE; + END IF; + RETURN RETVAL; + END IF_THEN_ELSE; + --------------------------------- + FUNCTION IF_THEN_ELSE ( + CONDITION : BOOLEAN; + TRUE_CASE : STRING; + FALSE_CASE : STRING) + RETURN STRING IS + BEGIN + IF NOT CONDITION THEN + RETURN FALSE_CASE; + ELSE + RETURN TRUE_CASE; + END IF; + END IF_THEN_ELSE; + ------------------------------- + FUNCTION LOG2ROUNDUP ( + DATA_VALUE : INTEGER) + RETURN INTEGER IS + VARIABLE WIDTH : INTEGER := 0; + VARIABLE CNT : INTEGER := 1; + BEGIN + IF (DATA_VALUE <= 1) THEN + WIDTH := 1; + ELSE + WHILE (CNT < DATA_VALUE) LOOP + WIDTH := WIDTH + 1; + CNT := CNT *2; + END LOOP; + END IF; + RETURN WIDTH; + END LOG2ROUNDUP; + +END BMG_TB_PKG; diff --git a/FPGA/Generator/ipcore_dir/result_bram/simulation/checker.vhd b/FPGA/Generator/ipcore_dir/result_bram/simulation/checker.vhd new file mode 100755 index 0000000..15a2753 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/simulation/checker.vhd @@ -0,0 +1,161 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Checker +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: checker.vhd +-- +-- Description: +-- Checker +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY CHECKER IS + GENERIC ( WRITE_WIDTH : INTEGER :=32; + READ_WIDTH : INTEGER :=32 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_IN : IN STD_LOGIC_VECTOR (READ_WIDTH-1 DOWNTO 0); --OUTPUT VECTOR + STATUS : OUT STD_LOGIC:= '0' + ); +END CHECKER; + +ARCHITECTURE CHECKER_ARCH OF CHECKER IS + SIGNAL EXPECTED_DATA : STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL DATA_IN_R: STD_LOGIC_VECTOR(READ_WIDTH-1 DOWNTO 0); + SIGNAL EN_R : STD_LOGIC := '0'; + SIGNAL EN_2R : STD_LOGIC := '0'; +--DATA PART CNT DEFINES THE ASPECT RATIO AND GIVES THE INFO TO THE DATA GENERATOR TO PROVIDE THE DATA EITHER IN PARTS OR COMPLETE DATA IN ONE SHOT +--IF READ_WIDTH > WRITE_WIDTH DIVROUNDUP RESULTS IN '1' AND DATA GENERATOR GIVES THE DATAOUT EQUALS TO MAX OF (WRITE_WIDTH, READ_WIDTH) +--IF READ_WIDTH < WRITE-WIDTH DIVROUNDUP RESULTS IN > '1' AND DATA GENERATOR GIVES THE DATAOUT IN TERMS OF PARTS(EG 4 PARTS WHEN WRITE_WIDTH 32 AND READ WIDTH 8) + CONSTANT DATA_PART_CNT: INTEGER:= DIVROUNDUP(WRITE_WIDTH,READ_WIDTH); + CONSTANT MAX_WIDTH: INTEGER:= IF_THEN_ELSE((WRITE_WIDTH>READ_WIDTH),WRITE_WIDTH,READ_WIDTH); + SIGNAL ERR_HOLD : STD_LOGIC :='0'; + SIGNAL ERR_DET : STD_LOGIC :='0'; +BEGIN + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST= '1') THEN + EN_R <= '0'; + EN_2R <= '0'; + DATA_IN_R <= (OTHERS=>'0'); + ELSE + EN_R <= EN; + EN_2R <= EN_R; + DATA_IN_R <= DATA_IN; + END IF; + END IF; + END PROCESS; + + EXPECTED_DATA_GEN_INST:ENTITY work.DATA_GEN + GENERIC MAP ( DATA_GEN_WIDTH =>MAX_WIDTH, + DOUT_WIDTH => READ_WIDTH, + DATA_PART_CNT => DATA_PART_CNT, + SEED => 2 + ) + PORT MAP ( + CLK => CLK, + RST => RST, + EN => EN_2R, + DATA_OUT => EXPECTED_DATA + ); + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(EN_2R='1') THEN + IF(EXPECTED_DATA = DATA_IN_R) THEN + ERR_DET<='0'; + ELSE + ERR_DET<= '1'; + END IF; + END IF; + END IF; + END PROCESS; + + PROCESS(CLK,RST) + BEGIN + IF(RST='1') THEN + ERR_HOLD <= '0'; + ELSIF(RISING_EDGE(CLK)) THEN + ERR_HOLD <= ERR_HOLD OR ERR_DET ; + END IF; + END PROCESS; + + STATUS <= ERR_HOLD; + +END ARCHITECTURE; + + + diff --git a/FPGA/Generator/ipcore_dir/result_bram/simulation/data_gen.vhd b/FPGA/Generator/ipcore_dir/result_bram/simulation/data_gen.vhd new file mode 100755 index 0000000..fe3dca7 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/simulation/data_gen.vhd @@ -0,0 +1,140 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Data Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: data_gen.vhd +-- +-- Description: +-- Data Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.BMG_TB_PKG.ALL; + +ENTITY DATA_GEN IS + GENERIC ( DATA_GEN_WIDTH : INTEGER := 32; + DOUT_WIDTH : INTEGER := 32; + DATA_PART_CNT : INTEGER := 1; + SEED : INTEGER := 2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + DATA_OUT : OUT STD_LOGIC_VECTOR (DOUT_WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END DATA_GEN; + +ARCHITECTURE DATA_GEN_ARCH OF DATA_GEN IS + CONSTANT LOOP_COUNT : INTEGER := DIVROUNDUP(DATA_GEN_WIDTH,8); + SIGNAL RAND_DATA : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0); + SIGNAL LOCAL_DATA_OUT : STD_LOGIC_VECTOR(DATA_GEN_WIDTH-1 DOWNTO 0); + SIGNAL LOCAL_CNT : INTEGER :=1; + SIGNAL DATA_GEN_I : STD_LOGIC :='0'; +BEGIN + + LOCAL_DATA_OUT <= RAND_DATA(DATA_GEN_WIDTH-1 DOWNTO 0); + DATA_OUT <= LOCAL_DATA_OUT(((DOUT_WIDTH*LOCAL_CNT)-1) DOWNTO ((DOUT_WIDTH*LOCAL_CNT)-DOUT_WIDTH)); + DATA_GEN_I <= '0' WHEN (LOCAL_CNT < DATA_PART_CNT) ELSE EN; + + PROCESS(CLK) + BEGIN + IF(RISING_EDGE (CLK)) THEN + IF(EN ='1' AND (DATA_PART_CNT =1)) THEN + LOCAL_CNT <=1; + ELSIF(EN='1' AND (DATA_PART_CNT>1)) THEN + IF(LOCAL_CNT = 1) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSIF(LOCAL_CNT < DATA_PART_CNT) THEN + LOCAL_CNT <= LOCAL_CNT+1; + ELSE + LOCAL_CNT <= 1; + END IF; + ELSE + LOCAL_CNT <= 1; + END IF; + END IF; + END PROCESS; + + RAND_GEN:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE + RAND_GEN_INST:ENTITY work.RANDOM + GENERIC MAP( + WIDTH => 8, + SEED => (SEED+N) + ) + PORT MAP( + CLK => CLK, + RST => RST, + EN => DATA_GEN_I, + RANDOM_NUM => RAND_DATA(8*(N+1)-1 DOWNTO 8*N) + ); + END GENERATE RAND_GEN; + +END ARCHITECTURE; + diff --git a/FPGA/Generator/ipcore_dir/result_bram/simulation/random.vhd b/FPGA/Generator/ipcore_dir/result_bram/simulation/random.vhd new file mode 100755 index 0000000..b0d417c --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/simulation/random.vhd @@ -0,0 +1,112 @@ + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Random Number Generator +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: random.vhd +-- +-- Description: +-- Random Generator +-- +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + + + + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + + +ENTITY RANDOM IS + GENERIC ( WIDTH : INTEGER := 32; + SEED : INTEGER :=2 + ); + + PORT ( + CLK : IN STD_LOGIC; + RST : IN STD_LOGIC; + EN : IN STD_LOGIC; + RANDOM_NUM : OUT STD_LOGIC_VECTOR (WIDTH-1 DOWNTO 0) --OUTPUT VECTOR + ); +END RANDOM; + +ARCHITECTURE BEHAVIORAL OF RANDOM IS +BEGIN + PROCESS(CLK) + VARIABLE RAND_TEMP : STD_LOGIC_VECTOR(WIDTH-1 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + VARIABLE TEMP : STD_LOGIC := '0'; + BEGIN + IF(RISING_EDGE(CLK)) THEN + IF(RST='1') THEN + RAND_TEMP := CONV_STD_LOGIC_VECTOR(SEED,WIDTH); + ELSE + IF(EN = '1') THEN + TEMP := RAND_TEMP(WIDTH-1) XOR RAND_TEMP(WIDTH-2); + RAND_TEMP(WIDTH-1 DOWNTO 1) := RAND_TEMP(WIDTH-2 DOWNTO 0); + RAND_TEMP(0) := TEMP; + END IF; + END IF; + END IF; + RANDOM_NUM <= RAND_TEMP; + END PROCESS; +END ARCHITECTURE; diff --git a/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_synth.vhd b/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_synth.vhd new file mode 100755 index 0000000..b19a76a --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_synth.vhd @@ -0,0 +1,322 @@ + + + + + + + + +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Synthesizable Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- +-- Filename: result_bram_synth.vhd +-- +-- Description: +-- Synthesizable Testbench +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.NUMERIC_STD.ALL; +USE IEEE.STD_LOGIC_MISC.ALL; + +LIBRARY STD; +USE STD.TEXTIO.ALL; + +--LIBRARY unisim; +--USE unisim.vcomponents.ALL; + +LIBRARY work; +USE work.ALL; +USE work.BMG_TB_PKG.ALL; + +ENTITY result_bram_synth IS +PORT( + CLK_IN : IN STD_LOGIC; + CLKB_IN : IN STD_LOGIC; + RESET_IN : IN STD_LOGIC; + STATUS : OUT STD_LOGIC_VECTOR(8 DOWNTO 0) := (OTHERS => '0') --ERROR STATUS OUT OF FPGA + ); +END ENTITY; + +ARCHITECTURE result_bram_synth_ARCH OF result_bram_synth IS + + +COMPONENT result_bram_exdes + PORT ( + --Inputs - Port A + WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0); + ADDRA : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DINA : IN STD_LOGIC_VECTOR(191 DOWNTO 0); + CLKA : IN STD_LOGIC; + + --Inputs - Port B + ADDRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0); + DOUTB : OUT STD_LOGIC_VECTOR(191 DOWNTO 0); + CLKB : IN STD_LOGIC + + ); + +END COMPONENT; + + + SIGNAL CLKA: STD_LOGIC := '0'; + SIGNAL RSTA: STD_LOGIC := '0'; + SIGNAL WEA: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL WEA_R: STD_LOGIC_VECTOR(0 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRA_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA: STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DINA_R: STD_LOGIC_VECTOR(191 DOWNTO 0) := (OTHERS => '0'); + SIGNAL CLKB: STD_LOGIC := '0'; + SIGNAL RSTB: STD_LOGIC := '0'; + SIGNAL ADDRB: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ADDRB_R: STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL DOUTB: STD_LOGIC_VECTOR(191 DOWNTO 0); + SIGNAL CHECKER_EN : STD_LOGIC:='0'; + SIGNAL CHECKER_EN_R : STD_LOGIC:='0'; + SIGNAL STIMULUS_FLOW : STD_LOGIC_VECTOR(22 DOWNTO 0) := (OTHERS =>'0'); + SIGNAL clk_in_i: STD_LOGIC; + + SIGNAL RESET_SYNC_R1 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R2 : STD_LOGIC:='1'; + SIGNAL RESET_SYNC_R3 : STD_LOGIC:='1'; + + SIGNAL clkb_in_i: STD_LOGIC; + SIGNAL RESETB_SYNC_R1 : STD_LOGIC := '1'; + SIGNAL RESETB_SYNC_R2 : STD_LOGIC := '1'; + SIGNAL RESETB_SYNC_R3 : STD_LOGIC := '1'; + SIGNAL ITER_R0 : STD_LOGIC := '0'; + SIGNAL ITER_R1 : STD_LOGIC := '0'; + SIGNAL ITER_R2 : STD_LOGIC := '0'; + + SIGNAL ISSUE_FLAG : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + SIGNAL ISSUE_FLAG_STATUS : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0'); + + BEGIN + +-- clk_buf: bufg +-- PORT map( +-- i => CLK_IN, +-- o => clk_in_i +-- ); + clk_in_i <= CLK_IN; + CLKA <= clk_in_i; + +-- clkb_buf: bufg +-- PORT map( +-- i => CLKB_IN, +-- o => clkb_in_i +-- ); + clkb_in_i <= CLKB_IN; + CLKB <= clkb_in_i; + RSTA <= RESET_SYNC_R3 AFTER 50 ns; + + + PROCESS(clk_in_i) + BEGIN + IF(RISING_EDGE(clk_in_i)) THEN + RESET_SYNC_R1 <= RESET_IN; + RESET_SYNC_R2 <= RESET_SYNC_R1; + RESET_SYNC_R3 <= RESET_SYNC_R2; + END IF; + END PROCESS; + + RSTB <= RESETB_SYNC_R3 AFTER 50 ns; + + PROCESS(clkb_in_i) + BEGIN + IF(RISING_EDGE(clkb_in_i)) THEN + RESETB_SYNC_R1 <= RESET_IN; + RESETB_SYNC_R2 <= RESETB_SYNC_R1; + RESETB_SYNC_R3 <= RESETB_SYNC_R2; + END IF; + END PROCESS; + +PROCESS(CLKA) +BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ISSUE_FLAG_STATUS<= (OTHERS => '0'); + ELSE + ISSUE_FLAG_STATUS <= ISSUE_FLAG_STATUS OR ISSUE_FLAG; + END IF; + END IF; +END PROCESS; + +STATUS(7 DOWNTO 0) <= ISSUE_FLAG_STATUS; + + + + + BMG_DATA_CHECKER_INST: ENTITY work.CHECKER + GENERIC MAP ( + WRITE_WIDTH => 192, + READ_WIDTH => 192 ) + PORT MAP ( + CLK => clkb_in_i, + RST => RSTB, + EN => CHECKER_EN_R, + DATA_IN => DOUTB, + STATUS => ISSUE_FLAG(0) + ); + + PROCESS(clkb_in_i) + BEGIN + IF(RISING_EDGE(clkb_in_i)) THEN + IF(RSTB='1') THEN + CHECKER_EN_R <= '0'; + ELSE + CHECKER_EN_R <= CHECKER_EN AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_STIM_GEN_INST:ENTITY work.BMG_STIM_GEN + PORT MAP( + CLKA => clk_in_i, + CLKB => clkb_in_i, + TB_RST => RSTA, + ADDRA => ADDRA, + DINA => DINA, + WEA => WEA, + ADDRB => ADDRB, + CHECK_DATA => CHECKER_EN + ); + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STATUS(8) <= '0'; + iter_r2 <= '0'; + iter_r1 <= '0'; + iter_r0 <= '0'; + ELSE + STATUS(8) <= iter_r2; + iter_r2 <= iter_r1; + iter_r1 <= iter_r0; + iter_r0 <= STIMULUS_FLOW(8); + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + STIMULUS_FLOW <= (OTHERS => '0'); + ELSIF(WEA(0)='1') THEN + STIMULUS_FLOW <= STIMULUS_FLOW+1; + END IF; + END IF; + END PROCESS; + + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + WEA_R <= (OTHERS=>'0') AFTER 50 ns; + DINA_R <= (OTHERS=>'0') AFTER 50 ns; + + + ELSE + WEA_R <= WEA AFTER 50 ns; + DINA_R <= DINA AFTER 50 ns; + + END IF; + END IF; + END PROCESS; + + + PROCESS(CLKA) + BEGIN + IF(RISING_EDGE(CLKA)) THEN + IF(RESET_SYNC_R3='1') THEN + ADDRA_R <= (OTHERS=> '0') AFTER 50 ns; + ADDRB_R <= (OTHERS=> '0') AFTER 50 ns; + ELSE + ADDRA_R <= ADDRA AFTER 50 ns; + ADDRB_R <= ADDRB AFTER 50 ns; + END IF; + END IF; + END PROCESS; + + + BMG_PORT: result_bram_exdes PORT MAP ( + --Port A + WEA => WEA_R, + ADDRA => ADDRA_R, + DINA => DINA_R, + CLKA => CLKA, + --Port B + ADDRB => ADDRB_R, + DOUTB => DOUTB, + CLKB => CLKB + + ); +END ARCHITECTURE; diff --git a/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_tb.vhd b/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_tb.vhd new file mode 100755 index 0000000..b32aed4 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/result_bram/simulation/result_bram_tb.vhd @@ -0,0 +1,142 @@ +-------------------------------------------------------------------------------- +-- +-- BLK MEM GEN v7_3 Core - Top File for the Example Testbench +-- +-------------------------------------------------------------------------------- +-- +-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved. +-- +-- This file contains confidential and proprietary information +-- of Xilinx, Inc. and is protected under U.S. and +-- international copyright and other intellectual property +-- laws. +-- +-- DISCLAIMER +-- This disclaimer is not a license and does not grant any +-- rights to the materials distributed herewith. Except as +-- otherwise provided in a valid license issued to you by +-- Xilinx, and to the maximum extent permitted by applicable +-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +-- (2) Xilinx shall not be liable (whether in contract or tort, +-- including negligence, or under any other theory of +-- liability) for any loss or damage of any kind or nature +-- related to, arising under or in connection with these +-- materials, including for any direct, or any indirect, +-- special, incidental, or consequential loss or damage +-- (including loss of data, profits, goodwill, or any type of +-- loss or damage suffered as a result of any action brought +-- by a third party) even if such damage or loss was +-- reasonably foreseeable or Xilinx had been advised of the +-- possibility of the same. +-- +-- CRITICAL APPLICATIONS +-- Xilinx products are not designed or intended to be fail- +-- safe, or for use in any application requiring fail-safe +-- performance, such as life-support or safety devices or +-- systems, Class III medical devices, nuclear facilities, +-- applications related to the deployment of airbags, or any +-- other applications that could lead to death, personal +-- injury, or severe property or environmental damage +-- (individually and collectively, "Critical +-- Applications"). Customer assumes the sole risk and +-- liability of any use of Xilinx products in Critical +-- Applications, subject only to applicable laws and +-- regulations governing limitations on product liability. +-- +-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +-- PART OF THIS FILE AT ALL TIMES. + +-------------------------------------------------------------------------------- +-- Filename: result_bram_tb.vhd +-- Description: +-- Testbench Top +-------------------------------------------------------------------------------- +-- Author: IP Solutions Division +-- +-- History: Sep 12, 2011 - First Release +-------------------------------------------------------------------------------- +-- +-------------------------------------------------------------------------------- +-- Library Declarations +-------------------------------------------------------------------------------- + +LIBRARY IEEE; +USE IEEE.STD_LOGIC_1164.ALL; +USE IEEE.STD_LOGIC_ARITH.ALL; +USE IEEE.STD_LOGIC_UNSIGNED.ALL; + +LIBRARY work; +USE work.ALL; + +ENTITY result_bram_tb IS +END ENTITY; + + +ARCHITECTURE result_bram_tb_ARCH OF result_bram_tb IS + SIGNAL STATUS : STD_LOGIC_VECTOR(8 DOWNTO 0); + SIGNAL CLK : STD_LOGIC := '1'; + SIGNAL CLKB : STD_LOGIC := '1'; + SIGNAL RESET : STD_LOGIC; + + BEGIN + + + CLK_GEN: PROCESS BEGIN + CLK <= NOT CLK; + WAIT FOR 100 NS; + CLK <= NOT CLK; + WAIT FOR 100 NS; + END PROCESS; + CLKB_GEN: PROCESS BEGIN + CLKB <= NOT CLKB; + WAIT FOR 100 NS; + CLKB <= NOT CLKB; + WAIT FOR 100 NS; + END PROCESS; + + RST_GEN: PROCESS BEGIN + RESET <= '1'; + WAIT FOR 1000 NS; + RESET <= '0'; + WAIT; + END PROCESS; + + +--STOP_SIM: PROCESS BEGIN +-- WAIT FOR 200 US; -- STOP SIMULATION AFTER 1 MS +-- ASSERT FALSE +-- REPORT "END SIMULATION TIME REACHED" +-- SEVERITY FAILURE; +--END PROCESS; +-- +PROCESS BEGIN + WAIT UNTIL STATUS(8)='1'; + IF( STATUS(7 downto 0)/="0") THEN + ASSERT false + REPORT "Test Completed Successfully" + SEVERITY NOTE; + REPORT "Simulation Failed" + SEVERITY FAILURE; + ELSE + ASSERT false + REPORT "TEST PASS" + SEVERITY NOTE; + REPORT "Test Completed Successfully" + SEVERITY FAILURE; + END IF; + +END PROCESS; + + result_bram_synth_inst:ENTITY work.result_bram_synth + PORT MAP( + CLK_IN => CLK, + CLKB_IN => CLK, + RESET_IN => RESET, + STATUS => STATUS + ); + +END ARCHITECTURE; diff --git a/FPGA/Generator/ipcore_dir/wide_mult.gise b/FPGA/Generator/ipcore_dir/wide_mult.gise new file mode 100644 index 0000000..3da6a8c --- /dev/null +++ b/FPGA/Generator/ipcore_dir/wide_mult.gise @@ -0,0 +1,53 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FPGA/Generator/ipcore_dir/wide_mult.vhd b/FPGA/Generator/ipcore_dir/wide_mult.vhd new file mode 100644 index 0000000..8879fd9 --- /dev/null +++ b/FPGA/Generator/ipcore_dir/wide_mult.vhd @@ -0,0 +1,102 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used solely -- +-- for design, simulation, implementation and creation of design files -- +-- limited to Xilinx devices or technologies. Use with non-Xilinx -- +-- devices or technologies is expressly prohibited and immediately -- +-- terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY -- +-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY -- +-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE -- +-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS -- +-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY -- +-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY -- +-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY -- +-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A -- +-- PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support appliances, -- +-- devices, or systems. Use in such applications are expressly -- +-- prohibited. -- +-- -- +-- (c) Copyright 1995-2022 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file wide_mult.vhd when simulating +-- the core, wide_mult. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synthesis directives "translate_off/translate_on" specified +-- below are supported by Xilinx, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synthesis translate_off +LIBRARY XilinxCoreLib; +-- synthesis translate_on +ENTITY wide_mult IS + PORT ( + clk : IN STD_LOGIC; + a : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(26 DOWNTO 0); + ce : IN STD_LOGIC; + p : OUT STD_LOGIC_VECTOR(39 DOWNTO 0) + ); +END wide_mult; + +ARCHITECTURE wide_mult_a OF wide_mult IS +-- synthesis translate_off +COMPONENT wrapped_wide_mult + PORT ( + clk : IN STD_LOGIC; + a : IN STD_LOGIC_VECTOR(12 DOWNTO 0); + b : IN STD_LOGIC_VECTOR(26 DOWNTO 0); + ce : IN STD_LOGIC; + p : OUT STD_LOGIC_VECTOR(39 DOWNTO 0) + ); +END COMPONENT; + +-- Configuration specification + FOR ALL : wrapped_wide_mult USE ENTITY XilinxCoreLib.mult_gen_v11_2(behavioral) + GENERIC MAP ( + c_a_type => 1, + c_a_width => 13, + c_b_type => 1, + c_b_value => "10000001", + c_b_width => 27, + c_ccm_imp => 0, + c_ce_overrides_sclr => 0, + c_has_ce => 1, + c_has_sclr => 0, + c_has_zero_detect => 0, + c_latency => 5, + c_model_type => 0, + c_mult_type => 1, + c_optimize_goal => 1, + c_out_high => 39, + c_out_low => 0, + c_round_output => 0, + c_round_pt => 0, + c_verbosity => 0, + c_xdevicefamily => "spartan6" + ); +-- synthesis translate_on +BEGIN +-- synthesis translate_off +U0 : wrapped_wide_mult + PORT MAP ( + clk => clk, + a => a, + b => b, + ce => ce, + p => p + ); +-- synthesis translate_on + +END wide_mult_a; diff --git a/FPGA/VNA/SPIConfig.vhd b/FPGA/VNA/SPIConfig.vhd index 5d7aaa9..351a917 100644 --- a/FPGA/VNA/SPIConfig.vhd +++ b/FPGA/VNA/SPIConfig.vhd @@ -51,7 +51,7 @@ entity SPICommands is SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0); NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0); STAGES : out STD_LOGIC_VECTOR (2 downto 0); - INDIVIDUAL_HALT : out STD_LOGIC; + SYNC_ENABLED : out STD_LOGIC; PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0); PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0); PORT1_EN : out STD_LOGIC; @@ -253,7 +253,7 @@ begin when 4 => ADC_PRESCALER <= spi_buf_out(7 downto 0); when 5 => ADC_PHASEINC <= spi_buf_out(11 downto 0); when 6 => STAGES <= spi_buf_out(15 downto 13); - INDIVIDUAL_HALT <= spi_buf_out(12); + SYNC_ENABLED <= spi_buf_out(12); PORT1_STAGE <= spi_buf_out(5 downto 3); PORT2_STAGE <= spi_buf_out(2 downto 0); when 7 => SPI_OVERWRITE_ENABLED <= spi_buf_out(15); diff --git a/FPGA/VNA/Sweep.vhd b/FPGA/VNA/Sweep.vhd index f2ff7d0..9f95290 100644 --- a/FPGA/VNA/Sweep.vhd +++ b/FPGA/VNA/Sweep.vhd @@ -61,13 +61,16 @@ entity Sweep is SWEEP_HALTED : out STD_LOGIC; SWEEP_RESUME : in STD_LOGIC; + SYNC_ENABLED : in STD_LOGIC; + TRIGGER_IN : in STD_LOGIC; + TRIGGER_OUT : out STD_LOGIC; + ATTENUATOR : out STD_LOGIC_VECTOR(6 downto 0); SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0); --SETTLING_TIME : in STD_LOGIC_VECTOR (15 downto 0); STAGES : in STD_LOGIC_VECTOR (2 downto 0); - INDIVIDUAL_HALT : in STD_LOGIC; PORT1_STAGE : in STD_LOGIC_VECTOR (2 downto 0); PORT2_STAGE : in STD_LOGIC_VECTOR (2 downto 0); @@ -82,12 +85,13 @@ end Sweep; architecture Behavioral of Sweep is signal point_cnt : unsigned(12 downto 0); - type Point_states is (TriggerSetup, SettingUp, Settling, Exciting, NextPoint, Done); + type Point_states is (TriggerSetup, SettingUp, Settling, WaitTriggerHigh, Exciting, WaitTriggerLow, SamplingDone, NextPoint, Done); signal state : Point_states; signal settling_cnt : unsigned(15 downto 0); signal settling_time : unsigned(15 downto 0); signal stage_cnt : unsigned (2 downto 0); signal config_reg : std_logic_vector(95 downto 0); + signal source_active : std_logic; begin CONFIG_ADDRESS <= std_logic_vector(point_cnt); @@ -124,16 +128,22 @@ begin std_logic_vector(to_unsigned(1904, 13)) when config_reg(92 downto 90) = "110" else std_logic_vector(to_unsigned(5712, 13)); - DEBUG_STATUS(10 downto 8) <= "000" when state = TriggerSetup else - "001" when state = SettingUp else - "010" when state = Settling else - "011" when state = Exciting else - "110" when state = Done else - "111"; - DEBUG_STATUS(7) <= PLL_RELOAD_DONE; - DEBUG_STATUS(6) <= PLL_RELOAD_DONE and PLL_LOCKED; - DEBUG_STATUS(5) <= SAMPLING_BUSY; - DEBUG_STATUS(4 downto 0) <= (others => '1'); + DEBUG_STATUS(10 downto 7) <= "0000" when state = TriggerSetup else + "0001" when state = SettingUp else + "0010" when state = Settling else + "0011" when state = WaitTriggerHigh else + "0100" when state = Exciting else + "0101" when state = WaitTriggerLow else + "0110" when state = SamplingDone else + "0111" when state = NextPoint else + "1000" when state = Done else + "1001"; + DEBUG_STATUS(6) <= PLL_RELOAD_DONE; + DEBUG_STATUS(5) <= PLL_RELOAD_DONE and PLL_LOCKED; + DEBUG_STATUS(4) <= SAMPLING_BUSY; + DEBUG_STATUS(3) <= TRIGGER_IN; + DEBUG_STATUS(2) <= source_active; + DEBUG_STATUS(1 downto 0) <= (others => '1'); config_reg <= CONFIG_DATA; @@ -150,6 +160,8 @@ begin RESULT_INDEX <= (others => '1'); PORT1_ACTIVE <= '0'; PORT2_ACTIVE <= '0'; + TRIGGER_OUT <= '0'; + source_active <= '0'; else case state is when TriggerSetup => @@ -177,13 +189,16 @@ begin end if; end if; when Settling => + source_active <= '0'; if std_logic_vector(stage_cnt) = PORT1_STAGE then PORT1_ACTIVE <= '1'; + source_active <= '1'; else PORT1_ACTIVE <= '0'; end if; if std_logic_vector(stage_cnt) = PORT2_STAGE then PORT2_ACTIVE <= '1'; + source_active <= '1'; else PORT2_ACTIVE <= '0'; end if; @@ -191,6 +206,24 @@ begin if settling_cnt > 0 then settling_cnt <= settling_cnt - 1; else + if SYNC_ENABLED = '1' then + -- need to wait for the trigger + state <= WaitTriggerHigh; + if source_active = '1' then + -- this device generates the stimulus signal, it needs start the trigger itself + TRIGGER_OUT <= '1'; + end if; + else + -- can start sampling directly + START_SAMPLING <= '1'; + if SAMPLING_BUSY = '1' then + state <= Exciting; + end if; + end if; + end if; + when WaitTriggerHigh => + if TRIGGER_IN = '1' then + TRIGGER_OUT <= '1'; -- pass on trigger signal START_SAMPLING <= '1'; if SAMPLING_BUSY = '1' then state <= Exciting; @@ -201,20 +234,30 @@ begin START_SAMPLING <= '0'; if SAMPLING_BUSY = '0' then RESULT_INDEX <= std_logic_vector(stage_cnt) & std_logic_vector(point_cnt); - if stage_cnt < unsigned(STAGES) then - stage_cnt <= stage_cnt + 1; - if INDIVIDUAL_HALT = '1' then - -- wait for HALT SWEEP bit again if set - state <= SettingUp; - else - -- no need to halt again, can go directly to settling - state <= Settling; + if SYNC_ENABLED = '1' then + state <= WaitTriggerLow; + if source_active = '1' then + -- this device generated the stimulus signal, it needs to reset the trigger itself + TRIGGER_OUT <= '0'; end if; else - state <= NextPoint; + state <= SamplingDone; end if; - settling_cnt <= settling_time; end if; + when WaitTriggerLow => + if TRIGGER_IN = '0' then + TRIGGER_OUT <= '0'; + state <= SamplingDone; + end if; + when SamplingDone => + if stage_cnt < unsigned(STAGES) then + stage_cnt <= stage_cnt + 1; + -- can go directly to settling + state <= Settling; + else + state <= NextPoint; + end if; + settling_cnt <= settling_time; when NextPoint => if point_cnt < unsigned(NPOINTS) then point_cnt <= point_cnt + 1; diff --git a/FPGA/VNA/VNA.gise b/FPGA/VNA/VNA.gise index 2f95209..bcce93c 100644 --- a/FPGA/VNA/VNA.gise +++ b/FPGA/VNA/VNA.gise @@ -224,7 +224,7 @@ - + @@ -253,7 +253,7 @@ - + @@ -271,11 +271,11 @@ - + - + @@ -284,7 +284,7 @@ - + @@ -298,7 +298,7 @@ - + @@ -312,7 +312,7 @@ - + @@ -365,7 +365,7 @@ - + diff --git a/FPGA/VNA/top.bin b/FPGA/VNA/top.bin index 061f534..cd69dfd 100644 Binary files a/FPGA/VNA/top.bin and b/FPGA/VNA/top.bin differ diff --git a/FPGA/VNA/top.ucf b/FPGA/VNA/top.ucf index ab7be65..0181c9c 100644 --- a/FPGA/VNA/top.ucf +++ b/FPGA/VNA/top.ucf @@ -57,6 +57,8 @@ NET "MCU_MOSI" IOSTANDARD = LVCMOS33; NET "MCU_INTR" IOSTANDARD = LVCMOS33; NET "MCU_AUX2" IOSTANDARD = LVCMOS33; NET "MCU_AUX3" IOSTANDARD = LVCMOS33; +NET "TRIGGER_IN" IOSTANDARD = LVCMOS33; +NET "TRIGGER_OUT" IOSTANDARD = LVCMOS33; NET "PORT1_SCLK" SLEW = FAST; NET "PORT2_SCLK" SLEW = FAST; @@ -95,6 +97,8 @@ NET "LO1_RF_EN" LOC = P55; NET "MCU_AUX1" LOC = P78; NET "MCU_AUX2" LOC = P75; NET "MCU_AUX3" LOC = P74; +NET "TRIGGER_IN" LOC = P80; +NET "TRIGGER_OUT" LOC = P81; NET "MCU_INTR" LOC = P59; NET "MCU_MISO" LOC = P62; NET "MCU_MOSI" LOC = P61; diff --git a/FPGA/VNA/top.vhd b/FPGA/VNA/top.vhd index a3b61ac..bccf536 100644 --- a/FPGA/VNA/top.vhd +++ b/FPGA/VNA/top.vhd @@ -40,6 +40,8 @@ entity top is MCU_AUX1 : in STD_LOGIC; MCU_AUX2 : in STD_LOGIC; MCU_AUX3 : in STD_LOGIC; + TRIGGER_IN : in STD_LOGIC; + TRIGGER_OUT : out STD_LOGIC; PORT2_CONVSTART : out STD_LOGIC; PORT2_SDO : in STD_LOGIC; PORT2_SCLK : out STD_LOGIC; @@ -136,10 +138,12 @@ architecture Behavioral of top is RELOAD_PLL_REGS : OUT std_logic; SWEEP_HALTED : out STD_LOGIC; SWEEP_RESUME : in STD_LOGIC; + SYNC_ENABLED : in STD_LOGIC; + TRIGGER_IN : in STD_LOGIC; + TRIGGER_OUT : out STD_LOGIC; ATTENUATOR : OUT std_logic_vector(6 downto 0); SOURCE_FILTER : OUT std_logic_vector(1 downto 0); STAGES : in STD_LOGIC_VECTOR (2 downto 0); - INDIVIDUAL_HALT : in STD_LOGIC; PORT1_STAGE : in STD_LOGIC_VECTOR (2 downto 0); PORT2_STAGE : in STD_LOGIC_VECTOR (2 downto 0); @@ -248,7 +252,7 @@ architecture Behavioral of top is SWEEP_POINTS : OUT std_logic_vector(12 downto 0); NSAMPLES : OUT std_logic_vector(12 downto 0); STAGES : out STD_LOGIC_VECTOR (2 downto 0); - INDIVIDUAL_HALT : out STD_LOGIC; + SYNC_ENABLED : out STD_LOGIC; PORT1_STAGE : out STD_LOGIC_VECTOR (2 downto 0); PORT2_STAGE : out STD_LOGIC_VECTOR (2 downto 0); PORT1_EN : out STD_LOGIC; @@ -371,7 +375,7 @@ architecture Behavioral of top is -- Sweep signals signal sweep_points : std_logic_vector(12 downto 0); signal sweep_stages : STD_LOGIC_VECTOR (2 downto 0); - signal sweep_individual_halt : STD_LOGIC; + signal sweep_sync_enabled: STD_LOGIC; signal sweep_port1_stage : STD_LOGIC_VECTOR (2 downto 0); signal sweep_port2_stage : STD_LOGIC_VECTOR (2 downto 0); signal sweep_config_data : std_logic_vector(95 downto 0); @@ -684,10 +688,12 @@ begin PLL_LOCKED => plls_locked, SWEEP_HALTED => sweep_halted, SWEEP_RESUME => sweep_resume, + SYNC_ENABLED => sweep_sync_enabled, + TRIGGER_IN => TRIGGER_IN, + TRIGGER_OUT => TRIGGER_OUT, ATTENUATOR => sweep_attenuator, SOURCE_FILTER => sweep_source_filter, STAGES => sweep_stages, - INDIVIDUAL_HALT => sweep_individual_halt, PORT1_STAGE => sweep_port1_stage, PORT2_STAGE => sweep_port2_stage, @@ -765,7 +771,7 @@ begin SWEEP_HALTED => sweep_halted, SWEEP_RESUME => sweep_resume, STAGES => sweep_stages, - INDIVIDUAL_HALT => sweep_individual_halt, + SYNC_ENABLED => sweep_sync_enabled, PORT1_STAGE => sweep_port1_stage, PORT2_STAGE => sweep_port2_stage, SPI_OVERWRITE_ENABLED => HW_overwrite_enabled, diff --git a/Software/PC_Application/Device/compounddevice.cpp b/Software/PC_Application/Device/compounddevice.cpp index 260400d..1ada202 100644 --- a/Software/PC_Application/Device/compounddevice.cpp +++ b/Software/PC_Application/Device/compounddevice.cpp @@ -75,3 +75,13 @@ QString CompoundDevice::getDesription() { return name + ", "+QString::number(deviceSerials.size())+" devices, "+QString::number(portMapping.size())+" ports in total"; } + +int CompoundDevice::PortMapping::findActiveStage(std::vector map, int device, int port) +{ + for(unsigned int i=0;i map, int device, int port); }; enum class Synchronization { diff --git a/Software/PC_Application/Device/device.cpp b/Software/PC_Application/Device/device.cpp index b3fbc3c..027dfe0 100644 --- a/Software/PC_Application/Device/device.cpp +++ b/Software/PC_Application/Device/device.cpp @@ -26,7 +26,7 @@ USBInBuffer::USBInBuffer(libusb_device_handle *handle, unsigned char endpoint, i { buffer = new unsigned char[buffer_size]; transfer = libusb_alloc_transfer(0); - libusb_fill_bulk_transfer(transfer, handle, endpoint, buffer, buffer_size, CallbackTrampoline, this, 100); + libusb_fill_bulk_transfer(transfer, handle, endpoint, buffer, buffer_size, CallbackTrampoline, this, 0); libusb_submit_transfer(transfer); } @@ -66,9 +66,11 @@ int USBInBuffer::getReceived() const void USBInBuffer::Callback(libusb_transfer *transfer) { +// qDebug() << libusb_error_name(transfer->status); switch(transfer->status) { case LIBUSB_TRANSFER_COMPLETED: received_size += transfer->actual_length; +// qDebug() << transfer->actual_length <<"total:" << received_size; inCallback = true; emit DataReceived(); inCallback = false; @@ -249,6 +251,7 @@ bool Device::SendPacket(const Protocol::PacketInfo& packet, std::function lock(transmissionMutex); transmissionQueue.enqueue(t); // qDebug() << "Enqueued packet, queue at " << transmissionQueue.size(); if(!transmissionActive) { @@ -321,6 +324,16 @@ std::set Device::GetDevices() return serials; } +void Device::SetTrigger(bool set) +{ + qDebug() << "Trigger" << set << "to" << this; + if(set) { + SendCommandWithoutPayload(Protocol::PacketType::SetTrigger); + } else { + SendCommandWithoutPayload(Protocol::PacketType::ClearTrigger); + } +} + void Device::USBHandleThread() { qDebug() << "Receive thread started"; @@ -460,7 +473,9 @@ void Device::ReceivedData() uint16_t handled_len; // qDebug() << "Received data"; do { +// qDebug() << "Decoding" << dataBuffer->getReceived() << "Bytes"; handled_len = Protocol::DecodeBuffer(dataBuffer->getBuffer(), dataBuffer->getReceived(), &packet); +// qDebug() << "Handled" << handled_len << "Bytes, type:" << (int) packet.type; dataBuffer->removeBytes(handled_len); switch(packet.type) { case Protocol::PacketType::VNADatapoint: @@ -502,6 +517,14 @@ void Device::ReceivedData() case Protocol::PacketType::FrequencyCorrection: emit FrequencyCorrectionReceived(packet.frequencyCorrection.ppm); break; + case Protocol::PacketType::SetTrigger: + qDebug() << "Trigger" << true << "from" << this; + emit TriggerReceived(true); + break; + case Protocol::PacketType::ClearTrigger: + qDebug() << "Trigger" << false << "from" << this; + emit TriggerReceived(false); + break; default: break; } @@ -557,8 +580,9 @@ bool Device::startNextTransmission() void Device::transmissionFinished(TransmissionResult result) { + lock_guard lock(transmissionMutex); // remove transmitted packet -// qDebug() << "Transmission finsished (" << result << "), queue at " << transmissionQueue.size(); +// qDebug() << "Transmission finsished (" << result << "), queue at " << transmissionQueue.size() << " Outstanding ACKs:"< #include #include +#include Q_DECLARE_METATYPE(Protocol::Datapoint) Q_DECLARE_METATYPE(Protocol::ManualStatusV1) @@ -87,8 +88,11 @@ signals: void ConnectionLost(); void AckReceived(); void NackReceived(); + void TriggerReceived(bool set); void LogLineReceived(QString line); void NeedsFirmwareUpdate(int usedProtocol, int requiredProtocol); +public slots: + void SetTrigger(bool set); private slots: void ReceivedData(); void ReceivedLog(); @@ -120,6 +124,7 @@ private: std::function callback; }; + std::mutex transmissionMutex; QQueue transmissionQueue; bool startNextTransmission(); QTimer transmissionTimer; diff --git a/Software/PC_Application/Device/virtualdevice.cpp b/Software/PC_Application/Device/virtualdevice.cpp index 8bdca9e..a087f75 100644 --- a/Software/PC_Application/Device/virtualdevice.cpp +++ b/Software/PC_Application/Device/virtualdevice.cpp @@ -1,6 +1,7 @@ #include "virtualdevice.h" #include "preferences.h" +#include "CustomWidgets/informationbox.h" #include "../VNA_embedded/Application/Communication/Protocol.hpp" #include @@ -99,130 +100,74 @@ public: } }; -static constexpr VirtualDevice::Info defaultInfo = { - .ProtocolVersion = Protocol::Version, - .FW_major = 0, - .FW_minor = 0, - .FW_patch = 0, - .hardware_version = 1, - .HW_Revision = '0', - .ports = 2, - .supportsVNAmode = true, - .supportsSAmode = true, - .supportsSGmode = true, - .supportsExtRef = true, - .Limits = { - .minFreq = 0, - .maxFreq = 6000000000, - .maxFreqHarmonic = 18000000000, - .minIFBW = 10, - .maxIFBW = 1000000, - .maxPoints = 10000, - .mindBm = -100, - .maxdBm = 100, - .minRBW = 1, - .maxRBW = 1000000, - } -}; - -static const VirtualDevice::Status defaultStatus = { - .statusString = "", - .overload = false, - .unlocked = false, - .unlevel = false, - .extRef = false, -}; - VirtualDevice::VirtualDevice(QString serial) : QObject(), info{}, status{} { cdev = nullptr; - isCompound = false; + cdev = nullptr; zerospan = false; - auto dev = new Device(serial); - devices.push_back(dev); + + // Check if this is a compound device + auto pref = Preferences::getInstance(); + for(auto cd : pref.compoundDevices) { + if(cd->name == serial) { + // connect request to this compound device + cdev = cd; + break; + } + } if(!isCompoundDevice()) { // just acting as a wrapper for device, pass on signals + auto dev = new Device(serial); + devices.push_back(dev); connect(dev, &Device::ConnectionLost, this, &VirtualDevice::ConnectionLost); - connect(dev, &Device::DeviceInfoUpdated, [&](){ - auto i = devices[0]->Info(); - info.ProtocolVersion = i.ProtocolVersion; - info.FW_major = i.FW_major; - info.FW_minor = i.FW_minor; - info.FW_patch = i.FW_patch; - info.hardware_version = i.hardware_version; - info.HW_Revision = i.HW_Revision; - info.ports = 2; - info.supportsVNAmode = true; - info.supportsSAmode = true; - info.supportsSGmode = true; - info.supportsExtRef = true; - info.Limits.minFreq = i.limits_minFreq; - info.Limits.maxFreq = i.limits_maxFreq; - info.Limits.maxFreqHarmonic = i.limits_maxFreqHarmonic; - info.Limits.minIFBW = i.limits_minIFBW; - info.Limits.maxIFBW = i.limits_maxIFBW; - info.Limits.maxPoints = i.limits_maxPoints; - info.Limits.mindBm = (double) i.limits_cdbm_min / 100; - info.Limits.maxdBm = (double) i.limits_cdbm_max / 100; - info.Limits.minRBW = i.limits_minRBW; - info.Limits.maxRBW = i.limits_minRBW; + connect(dev, &Device::DeviceInfoUpdated, [=](){ + info = Info(devices[0]); emit InfoUpdated(); }); connect(dev, &Device::LogLineReceived, this, &VirtualDevice::LogLineReceived); - connect(dev, &Device::DeviceStatusUpdated, [&](){ - status.statusString = devices[0]->getLastDeviceInfoString(); - status.overload = devices[0]->StatusV1().ADC_overload; - status.unlevel = devices[0]->StatusV1().unlevel; - status.unlocked = !devices[0]->StatusV1().LO1_locked || !devices[0]->StatusV1().source_locked; - status.extRef = devices[0]->StatusV1().extRefInUse; + connect(dev, &Device::DeviceStatusUpdated, [=](){ + status = Status(devices[0]); emit StatusUpdated(status); }); connect(dev, &Device::NeedsFirmwareUpdate, this, &VirtualDevice::NeedsFirmwareUpdate); - - connect(dev, &Device::SpectrumResultReceived, [&](Protocol::SpectrumAnalyzerResult res){ - SAMeasurement m; - m.pointNum = res.pointNum; - if(zerospan) { - m.us = res.us; - } else { - m.frequency = res.frequency; - } - m.measurements["PORT1"] = res.port1; - m.measurements["PORT2"] = res.port2; - emit SAmeasurementReceived(m); - }); - connect(dev, &Device::DatapointReceived, [&](Protocol::VNADatapoint<32> *res){ - VNAMeasurement m; - m.pointNum = res->pointNum; - m.Z0 = 50.0; - if(zerospan) { - m.us = res->us; - } else { - m.frequency = res->frequency; - m.dBm = (double) res->cdBm / 100; - } - for(auto map : portStageMapping) { - // map.first is the port (starts at zero) - // map.second is the stage at which this port had the stimulus (starts at zero) - complex ref = res->getValue(map.second, map.first, true); - for(int i=0;i<2;i++) { - complex input = res->getValue(map.second, i, false); - if(!std::isnan(ref.real()) && !std::isnan(input.real())) { - // got both required measurements - QString name = "S"+QString::number(i+1)+QString::number(map.first+1); - m.measurements[name] = input / ref; - } - } - } - delete res; - emit VNAmeasurementReceived(m); - }); + connect(dev, &Device::SpectrumResultReceived, this, &VirtualDevice::singleSpectrumResultReceived); + connect(dev, &Device::DatapointReceived, this, &VirtualDevice::singleDatapointReceived); } else { - // TODO + // Connect to the actual devices + for(auto devSerial : cdev->deviceSerials) { + auto dev = new Device(devSerial); + devices.push_back(dev); + // Create device connections + connect(dev, &Device::ConnectionLost, this, &VirtualDevice::ConnectionLost); + connect(dev, &Device::NeedsFirmwareUpdate, this, &VirtualDevice::NeedsFirmwareUpdate); + connect(dev, &Device::LogLineReceived, [=](QString line){ + emit LogLineReceived(line.prepend(dev->serial()+": ")); + }); + connect(dev, &Device::DeviceInfoUpdated, [=](){ + compoundInfoUpdated(dev); + }); + connect(dev, &Device::DeviceStatusUpdated, [=](){ + compoundStatusUpdated(dev); + }); + connect(dev, &Device::DatapointReceived, [=](Protocol::VNADatapoint<32> *data){ + compoundDatapointReceivecd(data, dev); + }); + connect(dev, &Device::SpectrumResultReceived, [=](Protocol::SpectrumAnalyzerResult res) { + compoundSpectrumResultReceived(res, dev); + }); + } + if(cdev->sync == CompoundDevice::Synchronization::USB) { + // create trigger connections for USB synchronization + for(int i=0;iinfo; } else { - return defaultInfo; + return Info(); } } @@ -285,12 +230,12 @@ const VirtualDevice::Status &VirtualDevice::getStatus() const return status; } -const VirtualDevice::Status &VirtualDevice::getStatus(VirtualDevice *vdev) +VirtualDevice::Status VirtualDevice::getStatus(VirtualDevice *vdev) { if(vdev) { return vdev->status; } else { - return defaultStatus; + return Status(); } } @@ -316,26 +261,27 @@ bool VirtualDevice::setVNA(const VirtualDevice::VNASettings &s, std::functionstage mapping portStageMapping.clear(); - for(int i=0;iConfigure(sd, [=](Device::TransmissionResult r){ if(cb) { @@ -343,8 +289,31 @@ bool VirtualDevice::setVNA(const VirtualDevice::VNASettings &s, std::functionsync) { + case CompoundDevice::Synchronization::USB: sd.syncMode = 1; break; + case CompoundDevice::Synchronization::ExtRef: sd.syncMode = 2; break; + case CompoundDevice::Synchronization::Trigger: sd.syncMode = 3; break; + } + // create vector of currently used stimulus ports + vector activeMapping; + for(auto p : s.excitedPorts) { + activeMapping.push_back(cdev->portMapping[p]); + } + // Configure the devices + results.clear(); + bool success = true; + for(unsigned int i=0;iConfigure(sd, [=](Device::TransmissionResult r){ + if(cb) { + results[devices[i]] = r; + checkIfAllTransmissionsComplete(cb); + } + }); + } + return success; } } @@ -353,8 +322,7 @@ QString VirtualDevice::serial() if(!isCompoundDevice()) { return devices[0]->serial(); } else { - // TODO - return ""; + return cdev->name; } } @@ -420,18 +388,30 @@ bool VirtualDevice::setSG(const SGSettings &s) return false; } auto pref = Preferences::getInstance(); + Protocol::PacketInfo packet; + packet.type = Protocol::PacketType::Generator; + Protocol::GeneratorSettings &sd = packet.generator; + sd.frequency = s.freq; + sd.cdbm_level = s.dBm * 100; + sd.applyAmplitudeCorrection = 1; + if(!isCompoundDevice()) { - Protocol::PacketInfo packet; - packet.type = Protocol::PacketType::Generator; - Protocol::GeneratorSettings &sd = packet.generator; - sd.frequency = s.freq; - sd.cdbm_level = s.dBm * 100; sd.activePort = s.port; - sd.applyAmplitudeCorrection = 1; return devices[0]->SendPacket(packet); } else { - // TODO - return false; + // configure all devices + bool success = true; + for(unsigned int i=0;i 0) { + if(cdev->portMapping[s.port-1].device == i) { + // this device has the active port + sd.activePort = cdev->portMapping[s.port-1].port+1; + } + } + success &= devices[i]->SendPacket(packet); + } + return success; } } @@ -443,17 +423,7 @@ bool VirtualDevice::setIdle(std::function cb) success &= dev->SetIdle([=](Device::TransmissionResult r){ if(cb) { results[dev] = r; - if(results.size() == devices.size()) { - // got all responses - bool success = true; - for(auto res : results) { - if(res.second != Device::TransmissionResult::Ack) { - success = false; - break; - } - } - cb(success); - } + checkIfAllTransmissionsComplete(cb); } }); } @@ -523,10 +493,25 @@ bool VirtualDevice::setExtRef(QString option_in, QString option_out) return success; } -std::set VirtualDevice::GetDevices() +std::set VirtualDevice::GetAvailableVirtualDevices() { + auto pref = Preferences::getInstance(); auto ret = Device::GetDevices(); - // TODO check if compound devices are configured and add them if all sub-devices are available + // Add compound devices as well + for(auto vdev : pref.compoundDevices) { + // check if all serial number required for this compound device are available + bool serialMissing = false; + for(auto s : vdev->deviceSerials) { + if(ret.count(s) == 0) { + serialMissing = true; + break; + } + } + if(!serialMissing) { + // this compound device is available + ret.insert(vdev->name); + } + } return ret; } @@ -535,6 +520,164 @@ VirtualDevice *VirtualDevice::getConnected() return connected; } +void VirtualDevice::singleDatapointReceived(Protocol::VNADatapoint<32> *res) +{ + VNAMeasurement m; + m.pointNum = res->pointNum; + m.Z0 = 50.0; + if(zerospan) { + m.us = res->us; + } else { + m.frequency = res->frequency; + m.dBm = (double) res->cdBm / 100; + } + for(auto map : portStageMapping) { + // map.first is the port (starts at zero) + // map.second is the stage at which this port had the stimulus (starts at zero) + complex ref = res->getValue(map.second, map.first, true); + for(int i=0;i<2;i++) { + complex input = res->getValue(map.second, i, false); + if(!std::isnan(ref.real()) && !std::isnan(input.real())) { + // got both required measurements + QString name = "S"+QString::number(i+1)+QString::number(map.first+1); + m.measurements[name] = input / ref; + } + } + } + delete res; + emit VNAmeasurementReceived(m); +} + +void VirtualDevice::compoundDatapointReceivecd(Protocol::VNADatapoint<32> *data, Device *dev) +{ + if(!compoundVNABuffer.count(data->pointNum)) { + compoundVNABuffer[data->pointNum] = std::map*>(); + } + auto &buf = compoundVNABuffer[data->pointNum]; + buf[dev] = data; + if(buf.size() == devices.size()) { + // Got datapoints from all devices, can create merged VNA result + VNAMeasurement m; + m.pointNum = data->pointNum; + m.Z0 = 50.0; + if(zerospan) { + m.us = data->us; + } else { + m.frequency = data->frequency; + m.dBm = (double) data->cdBm / 100; + } + // assemble data + for(auto map : portStageMapping) { + // map.first is the port (starts at zero) + // map.second is the stage at which this port had the stimulus (starts at zero) + + // figure out which device had the stimulus for the port... + auto stimulusDev = devices[cdev->portMapping[map.first].device]; + // ...and which device port was used for the stimulus... + auto stimulusDevPort = cdev->portMapping[map.first].port; + // ...grab the reference receiver data + complex ref = buf[stimulusDev]->getValue(map.second, stimulusDevPort, true); + + // for all ports of the compound device... + for(unsigned int i=0;iportMapping.size();i++) { + // ...figure out which physical device and port was used for this input... + auto inputDevice = devices[cdev->portMapping[i].device]; + // ...and grab the data + auto inputPort = cdev->portMapping[i].port; + complex input = buf[inputDevice]->getValue(map.second, inputPort, false); + if(!std::isnan(ref.real()) && !std::isnan(input.real())) { + // got both required measurements + QString name = "S"+QString::number(i+1)+QString::number(map.first+1); + m.measurements[name] = input / ref; + } + } + } + + emit VNAmeasurementReceived(m); + + // Clear this and all incomplete older datapoint buffers + for(auto p : compoundVNABuffer) { + for(auto d : p.second) { + delete d.second; + } + } + compoundVNABuffer.clear(); + } +} + +void VirtualDevice::singleSpectrumResultReceived(Protocol::SpectrumAnalyzerResult res) +{ + SAMeasurement m; + m.pointNum = res.pointNum; + if(zerospan) { + m.us = res.us; + } else { + m.frequency = res.frequency; + } + m.measurements["PORT1"] = res.port1; + m.measurements["PORT2"] = res.port2; + emit SAmeasurementReceived(m); +} + +void VirtualDevice::compoundSpectrumResultReceived(Protocol::SpectrumAnalyzerResult res, Device *dev) +{ + +} + +void VirtualDevice::compoundInfoUpdated(Device *dev) +{ + compoundInfoBuffer[dev] = dev->Info(); + if(compoundInfoBuffer.size() == devices.size()) { + // got information of all devices + info = Info(devices[0]); + for(int i=1;isync == CompoundDevice::Synchronization::ExtRef) { + // can't use the external reference if it is used for synchronization + info.supportsExtRef = false; + } + info.ports = cdev->portMapping.size(); + emit InfoUpdated(); + } +} + +void VirtualDevice::compoundStatusUpdated(Device *dev) +{ + compoundStatusBuffer[dev] = dev->StatusV1(); + if(compoundStatusBuffer.size() == devices.size()) { + // got status of all devices + status = Status(devices[0]); + for(int i=1;i cb) +{ + if(results.size() == devices.size()) { + // got all responses + bool success = true; + for(auto res : results) { + if(res.second != Device::TransmissionResult::Ack) { + success = false; + break; + } + } + if(cb) { + cb(success); + } + } +} + Sparam VirtualDevice::VNAMeasurement::toSparam(int port1, int port2) { Sparam S; @@ -579,3 +722,109 @@ VirtualDevice::VNAMeasurement VirtualDevice::VNAMeasurement::interpolateTo(const } return ret; } + +VirtualDevice::Info::Info() +{ + ProtocolVersion = Protocol::Version; + FW_major = 0; + FW_minor = 0; + FW_patch = 0; + hardware_version = 1; + HW_Revision = '0'; + ports = 2; + supportsVNAmode = true; + supportsSAmode = true; + supportsSGmode = true; + supportsExtRef = true; + Limits = { + .minFreq = 0, + .maxFreq = 6000000000, + .maxFreqHarmonic = 18000000000, + .minIFBW = 10, + .maxIFBW = 1000000, + .maxPoints = 10000, + .mindBm = -100, + .maxdBm = 100, + .minRBW = 1, + .maxRBW = 1000000, + }; +} + +VirtualDevice::Info::Info(Device *dev) +{ + auto info = dev->Info(); + ProtocolVersion = info.ProtocolVersion; + FW_major = info.FW_major; + FW_minor = info.FW_minor; + FW_patch = info.FW_patch; + hardware_version = info.hardware_version; + HW_Revision = info.HW_Revision; + ports = 2; + supportsVNAmode = true; + supportsSAmode = true; + supportsSGmode = true; + supportsExtRef = true; + Limits.minFreq = info.limits_minFreq; + Limits.maxFreq = info.limits_maxFreq; + Limits.maxFreqHarmonic = info.limits_maxFreqHarmonic; + Limits.minIFBW = info.limits_minIFBW; + Limits.maxIFBW = info.limits_maxIFBW; + Limits.maxPoints = info.limits_maxPoints; + Limits.mindBm = (double) info.limits_cdbm_min / 100; + Limits.maxdBm = (double) info.limits_cdbm_max / 100; + Limits.minRBW = info.limits_minRBW; + Limits.maxRBW = info.limits_minRBW; +} + +void VirtualDevice::Info::subset(const VirtualDevice::Info &merge) +{ + if((merge.ProtocolVersion != ProtocolVersion) + || (merge.FW_major != FW_major) + || (merge.FW_minor != FW_minor) + || (merge.FW_patch != FW_patch)) { + throw runtime_error("Incompatible device, unable to create compound device. All devices must run the same firmware version."); + } + ports += merge.ports; + supportsVNAmode &= merge.supportsVNAmode; + supportsSGmode &= merge.supportsSGmode; + supportsSAmode &= merge.supportsSAmode; + supportsExtRef &= merge.supportsExtRef; + Limits.minFreq = max(Limits.minFreq, merge.Limits.minFreq); + Limits.maxFreq = min(Limits.maxFreq, merge.Limits.maxFreq); + Limits.maxFreqHarmonic = min(Limits.maxFreqHarmonic, merge.Limits.maxFreqHarmonic); + Limits.minIFBW = max(Limits.minIFBW, merge.Limits.minIFBW); + Limits.maxIFBW = min(Limits.maxIFBW, merge.Limits.maxIFBW); + Limits.maxPoints = min(Limits.maxPoints, merge.Limits.maxPoints); + Limits.mindBm = max(Limits.mindBm, merge.Limits.mindBm); + Limits.maxdBm = min(Limits.maxdBm, merge.Limits.maxdBm); + Limits.minRBW = max(Limits.minRBW, merge.Limits.minRBW); + Limits.maxRBW = min(Limits.maxRBW, merge.Limits.maxRBW); +} + +VirtualDevice::Status::Status() +{ + statusString = ""; + overload = false; + unlocked = false; + unlevel = false; + extRef = false; +} + +VirtualDevice::Status::Status(Device *dev) +{ + auto status = dev->StatusV1(); + statusString = dev->getLastDeviceInfoString(); + overload = status.ADC_overload; + unlevel = status.unlevel; + unlocked = !status.LO1_locked || !status.source_locked; + extRef = status.extRefInUse; +} + +void VirtualDevice::Status::merge(const VirtualDevice::Status &merge) +{ + statusString += " / "+merge.statusString; + overload |= merge.overload; + unlevel |= merge.unlevel; + unlocked |= merge.unlocked; + extRef &= merge.extRef; +} diff --git a/Software/PC_Application/Device/virtualdevice.h b/Software/PC_Application/Device/virtualdevice.h index 9a8d1d7..ff57d96 100644 --- a/Software/PC_Application/Device/virtualdevice.h +++ b/Software/PC_Application/Device/virtualdevice.h @@ -19,6 +19,11 @@ public: class Info { public: + Info(); + Info(Device *dev); + + void subset(const Info &merge); + uint16_t ProtocolVersion; uint8_t FW_major; uint8_t FW_minor; @@ -42,6 +47,11 @@ public: class Status { public: + Status(); + Status(Device *dev); + + void merge(const Status &merge); + QString statusString; bool overload; bool unlocked; @@ -56,9 +66,9 @@ public: CompoundDevice *getCompoundDevice(); std::vector getDevices(); const Info& getInfo() const; - static const VirtualDevice::Info &getInfo(VirtualDevice *vdev); + static VirtualDevice::Info getInfo(VirtualDevice *vdev); const Status &getStatus() const; - static const VirtualDevice::Status &getStatus(VirtualDevice *vdev); + static VirtualDevice::Status getStatus(VirtualDevice *vdev); class VNASettings { public: @@ -148,7 +158,7 @@ public: public: double freq; double dBm; - int port; + int port; // starts at one, set to zero to disable all ports }; QStringList availableSGPorts(); @@ -161,7 +171,7 @@ public: bool setExtRef(QString option_in, QString option_out); - static std::set GetDevices(); + static std::set GetAvailableVirtualDevices(); static VirtualDevice* getConnected(); signals: @@ -172,10 +182,19 @@ signals: void StatusUpdated(Status status); void LogLineReceived(QString line); void NeedsFirmwareUpdate(int usedProtocol, int requiredProtocol); + +private slots: + void singleDatapointReceived(Protocol::VNADatapoint<32> *res); + void compoundDatapointReceivecd(Protocol::VNADatapoint<32> *data, Device *dev); + void singleSpectrumResultReceived(Protocol::SpectrumAnalyzerResult res); + void compoundSpectrumResultReceived(Protocol::SpectrumAnalyzerResult res, Device *dev); + void compoundInfoUpdated(Device *dev); + void compoundStatusUpdated(Device *dev); private: + void checkIfAllTransmissionsComplete(std::function cb = nullptr); + Info info; Status status; - bool isCompound; std::vector devices; bool zerospan; @@ -183,7 +202,10 @@ private: CompoundDevice *cdev; - std::map*>> compoundDataBuffer; + std::map*>> compoundVNABuffer; + std::map> compoundSABuffer; + std::map compoundInfoBuffer; + std::map compoundStatusBuffer; std::map portStageMapping; // maps from excitedPort (count starts at zero) to stage (count starts at zero) }; diff --git a/Software/PC_Application/Generator/generator.h b/Software/PC_Application/Generator/generator.h index 2bfbd9b..456aeee 100644 --- a/Software/PC_Application/Generator/generator.h +++ b/Software/PC_Application/Generator/generator.h @@ -19,7 +19,7 @@ public: virtual nlohmann::json toJSON() override; virtual void fromJSON(nlohmann::json j) override; - void setAveragingMode(Averaging::Mode mode) override {Q_UNUSED(mode)}; + void setAveragingMode(Averaging::Mode mode) override {Q_UNUSED(mode)} private slots: void updateDevice(); diff --git a/Software/PC_Application/Generator/signalgenwidget.cpp b/Software/PC_Application/Generator/signalgenwidget.cpp index 7cf8d2a..32747a4 100644 --- a/Software/PC_Application/Generator/signalgenwidget.cpp +++ b/Software/PC_Application/Generator/signalgenwidget.cpp @@ -94,18 +94,10 @@ SignalgeneratorWidget::SignalgeneratorWidget(VirtualDevice *dev, QWidget *parent connect(ui->levelSlider, &QSlider::valueChanged, [=](int value) { setLevel((double) value / 100.0); }); - connect(ui->EnablePort1, &QCheckBox::toggled, [=](){ - if(ui->EnablePort1->isChecked() && ui->EnablePort2->isChecked()) { - ui->EnablePort2->setCheckState(Qt::CheckState::Unchecked); - } - emit SettingsChanged(); - }); - connect(ui->EnablePort2, &QCheckBox::toggled, [=](){ - if(ui->EnablePort1->isChecked() && ui->EnablePort2->isChecked()) { - ui->EnablePort1->setCheckState(Qt::CheckState::Unchecked); - } - emit SettingsChanged(); - }); + connect(ui->EnablePort1, &QCheckBox::toggled, this, &SignalgeneratorWidget::SettingsChanged); + connect(ui->EnablePort2, &QCheckBox::toggled, this, &SignalgeneratorWidget::SettingsChanged); + connect(ui->EnablePort3, &QCheckBox::toggled, this, &SignalgeneratorWidget::SettingsChanged); + connect(ui->EnablePort4, &QCheckBox::toggled, this, &SignalgeneratorWidget::SettingsChanged); connect(ui->EnabledSweep, &QCheckBox::toggled, [=](bool enabled){ ui->current->setEnabled(enabled); if(enabled) { @@ -152,6 +144,10 @@ VirtualDevice::SGSettings SignalgeneratorWidget::getDeviceStatus() s.port = 1; } else if(ui->EnablePort2->isChecked()) { s.port = 2; + } else if(ui->EnablePort3->isChecked()) { + s.port = 3; + } else if(ui->EnablePort4->isChecked()) { + s.port = 4; } else { s.port = 0; } diff --git a/Software/PC_Application/Generator/signalgenwidget.ui b/Software/PC_Application/Generator/signalgenwidget.ui index a8da534..d5ec422 100644 --- a/Software/PC_Application/Generator/signalgenwidget.ui +++ b/Software/PC_Application/Generator/signalgenwidget.ui @@ -142,6 +142,9 @@ Port 1 + + buttonGroup + @@ -149,6 +152,29 @@ Port 2 + + buttonGroup + + + + + + + Port 3 + + + buttonGroup + + + + + + + Port 4 + + + buttonGroup + @@ -277,4 +303,7 @@ + + + diff --git a/Software/PC_Application/appwindow.cpp b/Software/PC_Application/appwindow.cpp index 27fd83f..7530f3f 100644 --- a/Software/PC_Application/appwindow.cpp +++ b/Software/PC_Application/appwindow.cpp @@ -436,7 +436,7 @@ void AppWindow::SetupSCPI() })); scpi_dev->add(new SCPICommand("LIST", nullptr, [=](QStringList) -> QString { QString ret; - for(auto d : Device::GetDevices()) { + for(auto d : VirtualDevice::GetAvailableVirtualDevices()) { ret += d + ","; } // remove last comma @@ -854,7 +854,7 @@ int AppWindow::UpdateDeviceList() { deviceActionGroup->setExclusive(true); ui->menuConnect_to->clear(); - auto devices = Device::GetDevices(); + auto devices = VirtualDevice::GetAvailableVirtualDevices(); if(vdevice) { devices.insert(vdevice->serial()); } diff --git a/Software/VNA_embedded/Application/App.cpp b/Software/VNA_embedded/Application/App.cpp index 048d4dd..6c48ed2 100644 --- a/Software/VNA_embedded/Application/App.cpp +++ b/Software/VNA_embedded/Application/App.cpp @@ -19,6 +19,7 @@ #include "Generator.hpp" #include "SpectrumAnalyzer.hpp" #include "HW_HAL.hpp" +#include "Trigger.hpp" #define LOG_LEVEL LOG_LEVEL_INFO #define LOG_MODULE "App" @@ -37,7 +38,10 @@ static bool sweepActive; extern ADC_HandleTypeDef hadc1; -#define FLAG_USB_PACKET 0x01 +#define FLAG_USB_PACKET 0x01 +#define FLAG_TRIGGER_OUT_ISR 0x02 + +static bool lastReportedTrigger; static void USBPacketReceived(const Protocol::PacketInfo &p) { recv_packet = p; @@ -46,6 +50,12 @@ static void USBPacketReceived(const Protocol::PacketInfo &p) { portYIELD_FROM_ISR(woken); } +static void TriggerOutISR() { + BaseType_t woken = false; + xTaskNotifyFromISR(handle, FLAG_TRIGGER_OUT_ISR, eSetBits, &woken); + portYIELD_FROM_ISR(woken); +} + inline void App_Init() { STM::Init(); Delay::Init(); @@ -60,6 +70,7 @@ inline void App_Init() { Log_SetRedirect(usb_log); LOG_INFO("Start"); Exti::Init(); + Trigger::Init(TriggerOutISR); #ifdef HAS_FLASH if(!HWHAL::flash.isPresent()) { LOG_CRIT("Failed to detect onboard FLASH"); @@ -247,16 +258,60 @@ inline void App_Process() { HW::setAcquisitionFrequencies(recv_packet.acquisitionFrequencySettings); Communication::SendWithoutPayload(Protocol::PacketType::Ack); break; + case Protocol::PacketType::SetTrigger: + if(Trigger::GetMode() == Trigger::Mode::USB_GUI) { + Trigger::SetInput(true); + Communication::SendWithoutPayload(Protocol::PacketType::Ack); + } else { + Communication::SendWithoutPayload(Protocol::PacketType::Nack); + } + break; + case Protocol::PacketType::ClearTrigger: + if(Trigger::GetMode() == Trigger::Mode::USB_GUI) { + Trigger::SetInput(false); + Communication::SendWithoutPayload(Protocol::PacketType::Ack); + } else { + Communication::SendWithoutPayload(Protocol::PacketType::Nack); + } + break; default: // this packet type is not supported Communication::SendWithoutPayload(Protocol::PacketType::Nack); break; } } + if(notification & FLAG_TRIGGER_OUT_ISR) { + // trigger output (from FPGA) changed level + bool set = Trigger::GetOutput(); + switch(Trigger::GetMode()) { + case Trigger::Mode::Off: + // nothing to do + break; + case Trigger::Mode::USB_GUI: + lastReportedTrigger = set; + Communication::SendWithoutPayload(set ? Protocol::PacketType::SetTrigger : Protocol::PacketType::ClearTrigger); + break; + case Trigger::Mode::ExtRef: + if(set) { + HWHAL::Si5351.Enable(HWHAL::SiChannel::ReferenceOut); + } else { + HWHAL::Si5351.Disable(HWHAL::SiChannel::ReferenceOut); + } + break; + case Trigger::Mode::Trigger: + // not supported by the hardware, nothing to do + break; + } + } } if(HW::TimedOut()) { + vTaskDelay(1000); + LOG_WARN("Timed out, FPGA status: 0x%04x", FPGA::GetStatus()); + vTaskDelay(1000); + LOG_WARN("Trigger out: %d (last reported: %d), in: %d", (uint8_t) Trigger::GetOutput(), (uint8_t) lastReportedTrigger, (uint8_t) Trigger::GetInput()); HW::SetMode(HW::Mode::Idle); // insert the last received packet (restarts the timed out operation) + Communication::BlockNextAck(); USBPacketReceived(last_measure_packet); } HW::updateDeviceStatus(); diff --git a/Software/VNA_embedded/Application/Communication/Communication.cpp b/Software/VNA_embedded/Application/Communication/Communication.cpp index 6df300a..bd9f0ff 100644 --- a/Software/VNA_embedded/Application/Communication/Communication.cpp +++ b/Software/VNA_embedded/Application/Communication/Communication.cpp @@ -8,8 +8,8 @@ static uint8_t inputBuffer[1024]; uint16_t inputCnt = 0; static uint8_t outputBuffer[1024]; - static Communication::Callback callback = nullptr; +static uint8_t blockAcks = 0; void Communication::SetCallback(Callback cb) { callback = cb; @@ -66,7 +66,15 @@ void communication_usb_input(const uint8_t *buf, uint16_t len) { } bool Communication::SendWithoutPayload(Protocol::PacketType type) { + if(type == Protocol::PacketType::Ack && blockAcks) { + blockAcks--; + return true; + } Protocol::PacketInfo p; p.type = type; return Send(p); } + +void Communication::BlockNextAck() { + blockAcks++; +} diff --git a/Software/VNA_embedded/Application/Communication/Communication.h b/Software/VNA_embedded/Application/Communication/Communication.h index 130e45d..bec3022 100644 --- a/Software/VNA_embedded/Application/Communication/Communication.h +++ b/Software/VNA_embedded/Application/Communication/Communication.h @@ -13,6 +13,7 @@ using Callback = void(*)(const Protocol::PacketInfo&); void SetCallback(Callback cb); void Input(const uint8_t *buf, uint16_t len); bool Send(const Protocol::PacketInfo &packet); +void BlockNextAck(); bool SendWithoutPayload(Protocol::PacketType type); } diff --git a/Software/VNA_embedded/Application/Communication/Protocol.cpp b/Software/VNA_embedded/Application/Communication/Protocol.cpp index 7d94264..3b1aa15 100644 --- a/Software/VNA_embedded/Application/Communication/Protocol.cpp +++ b/Software/VNA_embedded/Application/Communication/Protocol.cpp @@ -117,6 +117,8 @@ uint16_t Protocol::EncodePacket(const PacketInfo &packet, uint8_t *dest, uint16_ case PacketType::RequestFrequencyCorrection: case PacketType::RequestAcquisitionFrequencySettings: case PacketType::RequestDeviceStatus: + case PacketType::SetTrigger: + case PacketType::ClearTrigger: // no payload break; case PacketType::VNADatapoint: payload_size = packet.VNAdatapoint->requiredBufferSize(); break; diff --git a/Software/VNA_embedded/Application/Communication/Protocol.hpp b/Software/VNA_embedded/Application/Communication/Protocol.hpp index 2593aa8..abb9992 100644 --- a/Software/VNA_embedded/Application/Communication/Protocol.hpp +++ b/Software/VNA_embedded/Application/Communication/Protocol.hpp @@ -331,6 +331,8 @@ enum class PacketType : uint8_t { DeviceStatusV1 = 25, RequestDeviceStatus = 26, VNADatapoint = 27, + SetTrigger = 28, + ClearTrigger = 29, }; using PacketInfo = struct _packetinfo { diff --git a/Software/VNA_embedded/Application/Drivers/Si5351C.cpp b/Software/VNA_embedded/Application/Drivers/Si5351C.cpp index cd9800c..58f869d 100644 --- a/Software/VNA_embedded/Application/Drivers/Si5351C.cpp +++ b/Software/VNA_embedded/Application/Drivers/Si5351C.cpp @@ -325,7 +325,6 @@ bool Si5351C::WriteRegisterRange(Reg start, const uint8_t *data, uint8_t len) { bool Si5351C::ExtCLKAvailable() { uint8_t value; ReadRegister(Reg::DeviceStatus, &value); - LOG_DEBUG("Device status: 0x%02x", value); if (value & 0x10) { return false; } else { diff --git a/Software/VNA_embedded/Application/SpectrumAnalyzer.cpp b/Software/VNA_embedded/Application/SpectrumAnalyzer.cpp index a1e8810..8bebd54 100644 --- a/Software/VNA_embedded/Application/SpectrumAnalyzer.cpp +++ b/Software/VNA_embedded/Application/SpectrumAnalyzer.cpp @@ -7,6 +7,7 @@ #include "FreeRTOS.h" #include "task.h" #include "Util.hpp" +#include "Trigger.hpp" #include #define LOG_LEVEL LOG_LEVEL_DEBUG @@ -229,6 +230,7 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) { FPGA::Enable(FPGA::Periphery::Amplifier, s.trackingGenerator); FPGA::Enable(FPGA::Periphery::Port1Mixer); FPGA::Enable(FPGA::Periphery::Port2Mixer); + Trigger::SetMode((Trigger::Mode) s.syncMode); if(s.SignalID) { // use different ADC prescalers depending on RBW: For small RBWs, images with the shifted ADC samplerate can be closer to the IF @@ -431,7 +433,9 @@ void SA::Work() { // more measurements required for signal ID signalIDstep++; } - HW::Ref::update(); + if(Trigger::GetMode() != Trigger::Mode::ExtRef) { + HW::Ref::update(); + } StartNextSample(); } diff --git a/Software/VNA_embedded/Application/Trigger.cpp b/Software/VNA_embedded/Application/Trigger.cpp new file mode 100644 index 0000000..f845ea8 --- /dev/null +++ b/Software/VNA_embedded/Application/Trigger.cpp @@ -0,0 +1,73 @@ +#include "Trigger.hpp" + +#include "Drivers/Exti.hpp" +#include "main.h" +#include "HW_HAL.hpp" +#include "Communication/Protocol.hpp" +#include "Hardware.hpp" + +static Trigger::Mode mode; +static Trigger::CallbackISR callback = nullptr; + +void Trigger::Init(CallbackISR cb) { + mode = Mode::Off; + callback = cb; + Exti::SetCallback(FPGA_TRIGGER_OUT_GPIO_Port, FPGA_TRIGGER_OUT_Pin, Exti::EdgeType::Both, Exti::Pull::Down, [](void*){ + STM::DispatchToInterrupt(callback); + }, nullptr); +} + +extern "C" { +void vApplicationIdleHook() { + if(mode == Trigger::Mode::ExtRef) { + STM::DispatchToInterrupt([](){ + Trigger::SetInput(HW::Ref::available()); + }); + } +} +} + +void Trigger::SetMode(Mode m) { + if(mode == m) { + // already in the correct mdoe + return; + } + if(mode == Mode::ExtRef) { + // reset reference to default settings + HWHAL::Si5351.Disable(HWHAL::SiChannel::ReferenceOut); + } + mode = m; + if(mode == Mode::ExtRef) { + // Disable the external reference + Protocol::ReferenceSettings s; + s.AutomaticSwitch = 0; + s.ExtRefOuputFreq = 0; + s.UseExternalRef = 0; + HW::Ref::set(s); + HW::Ref::update(); + + HWHAL::Si5351.SetCLK(HWHAL::SiChannel::ReferenceOut, 10000000, Si5351C::PLL::A); + if(GetOutput()) { + HWHAL::Si5351.Enable(HWHAL::SiChannel::ReferenceOut); + } else { + HWHAL::Si5351.Disable(HWHAL::SiChannel::ReferenceOut); + } + } +} +Trigger::Mode Trigger::GetMode() { + return mode; +} + +void Trigger::SetInput(bool high) { + if(high) { + FPGA_TRIGGER_IN_GPIO_Port->BSRR = FPGA_TRIGGER_IN_Pin; + } else { + FPGA_TRIGGER_IN_GPIO_Port->BSRR = FPGA_TRIGGER_IN_Pin << 16; + } +} +bool Trigger::GetOutput() { + return FPGA_TRIGGER_OUT_GPIO_Port->IDR & FPGA_TRIGGER_OUT_Pin; +} +bool Trigger::GetInput() { + return FPGA_TRIGGER_IN_GPIO_Port->IDR & FPGA_TRIGGER_IN_Pin; +} diff --git a/Software/VNA_embedded/Application/Trigger.hpp b/Software/VNA_embedded/Application/Trigger.hpp new file mode 100644 index 0000000..78371b4 --- /dev/null +++ b/Software/VNA_embedded/Application/Trigger.hpp @@ -0,0 +1,25 @@ +#pragma once + +#include + +namespace Trigger { + +enum class Mode : uint8_t { + Off = 0, + USB_GUI = 1, + ExtRef = 2, + Trigger = 3, +}; + +using CallbackISR = void(*)(void); + +void Init(CallbackISR cb); + +void SetMode(Mode m); +Mode GetMode(); + +void SetInput(bool high); +bool GetOutput(); +bool GetInput(); + +} diff --git a/Software/VNA_embedded/Application/VNA.cpp b/Software/VNA_embedded/Application/VNA.cpp index d975a7e..8c75c18 100644 --- a/Software/VNA_embedded/Application/VNA.cpp +++ b/Software/VNA_embedded/Application/VNA.cpp @@ -13,6 +13,7 @@ #include "task.h" #include "Util.hpp" #include "usb.h" +#include "Trigger.hpp" #include #define LOG_LEVEL LOG_LEVEL_INFO @@ -279,6 +280,7 @@ bool VNA::Setup(Protocol::SweepSettings s) { FPGA::Enable(FPGA::Periphery::LO1Chip); FPGA::Enable(FPGA::Periphery::LO1RF); FPGA::SetupSweep(s.stages, s.port1Stage, s.port2Stage, s.syncMode != 0); + Trigger::SetMode((Trigger::Mode) s.syncMode); FPGA::Enable(FPGA::Periphery::PortSwitch); pointCnt = 0; stageCnt = 0; @@ -350,7 +352,9 @@ bool VNA::MeasurementDone(const FPGA::SamplingResult &result) { void VNA::Work() { // end of sweep - HW::Ref::update(); + if(Trigger::GetMode() != Trigger::Mode::ExtRef) { + HW::Ref::update(); + } // Compile info packet Protocol::PacketInfo packet; packet.type = Protocol::PacketType::DeviceStatusV1; @@ -365,86 +369,87 @@ void VNA::SweepHalted() { if(!active) { return; } - LOG_DEBUG("Halted before point %d", pointCnt); - // Check if IF table has entry at this point - if (IFTableIndexCnt < IFTableNumEntries && IFTable[IFTableIndexCnt].pointCnt == pointCnt) { - Si5351.WriteRawCLKConfig(SiChannel::Port1LO2, IFTable[IFTableIndexCnt].clkconfig); - Si5351.WriteRawCLKConfig(SiChannel::Port2LO2, IFTable[IFTableIndexCnt].clkconfig); - Si5351.WriteRawCLKConfig(SiChannel::RefLO2, IFTable[IFTableIndexCnt].clkconfig); - Si5351.ResetPLL(Si5351C::PLL::B); - IFTableIndexCnt++; - // PLL reset causes the 2.LO to turn off briefly and then ramp on back, needs delay before next point - Delay::us(1300); - } - uint64_t frequency = getPointFrequency(pointCnt); - int16_t power = settings.cdbm_excitation_start - + (settings.cdbm_excitation_stop - settings.cdbm_excitation_start) - * pointCnt / (settings.points - 1); - bool adcShiftRequired = false; - if (frequency < HW::BandSwitchFrequency) { - auto driveStrength = fixedPowerLowband; - if(!settings.fixedPowerSetting) { - auto amplitude = HW::GetAmplitudeSettings(power, frequency, true, false); - // attenuator value has already been set in sweep setup - driveStrength = amplitude.lowBandPower; - } - - // need the Si5351 as Source - bool freqSuccess = Si5351.SetCLK(SiChannel::LowbandSource, frequency, Si5351C::PLL::B, driveStrength); - static bool lowbandDisabled = false; - if (pointCnt == 0) { - // First point in sweep, switch to correct source - FPGA::Disable(FPGA::Periphery::SourceRF); - lowbandDisabled = true; - } - if(lowbandDisabled && freqSuccess) { - // frequency is valid, can enable lowband source now - Si5351.Enable(SiChannel::LowbandSource); + // Resuming the halted sweep requires I2C bus operations to the Si5355. When trigger synchronization is enabled + // in the external reference mode, this might collide with the trigger input check. Instead both these actions + // are handled through the STM::DispatchToInterrupt functionality, ensuring that they do not interrupt each other + STM::DispatchToInterrupt([](){ + LOG_DEBUG("Halted before point %d", pointCnt); + // Check if IF table has entry at this point + if (IFTableIndexCnt < IFTableNumEntries && IFTable[IFTableIndexCnt].pointCnt == pointCnt) { + Si5351.WriteRawCLKConfig(SiChannel::Port1LO2, IFTable[IFTableIndexCnt].clkconfig); + Si5351.WriteRawCLKConfig(SiChannel::Port2LO2, IFTable[IFTableIndexCnt].clkconfig); + Si5351.WriteRawCLKConfig(SiChannel::RefLO2, IFTable[IFTableIndexCnt].clkconfig); + Si5351.ResetPLL(Si5351C::PLL::B); + IFTableIndexCnt++; + // PLL reset causes the 2.LO to turn off briefly and then ramp on back, needs delay before next point Delay::us(1300); - lowbandDisabled = false; } - - // At low frequencies the 1.LO feedthrough mixes with the 2.LO in the second mixer. - // Depending on the stimulus frequency, the resulting mixing product might alias to the 2.IF - // in the ADC which causes a spike. Check for this and shift the ADC sampling frequency if necessary - - uint32_t LO_mixing = (HW::getIF1() + frequency) - (HW::getIF1() - HW::getIF2()); - if(abs(Util::Alias(LO_mixing, HW::getADCRate()) - HW::getIF2()) <= actualBandwidth * 2) { - // the image is in or near the IF bandwidth and would cause a peak - // Use a slightly different ADC sample rate if possible - if(HW::getIF2() == HW::DefaultIF2) { - adcShiftRequired = true; + uint64_t frequency = getPointFrequency(pointCnt); + int16_t power = settings.cdbm_excitation_start + + (settings.cdbm_excitation_stop - settings.cdbm_excitation_start) + * pointCnt / (settings.points - 1); + bool adcShiftRequired = false; + if (frequency < HW::BandSwitchFrequency) { + auto driveStrength = fixedPowerLowband; + if(!settings.fixedPowerSetting) { + auto amplitude = HW::GetAmplitudeSettings(power, frequency, true, false); + // attenuator value has already been set in sweep setup + driveStrength = amplitude.lowBandPower; } + + // need the Si5351 as Source + bool freqSuccess = Si5351.SetCLK(SiChannel::LowbandSource, frequency, Si5351C::PLL::B, driveStrength); + static bool lowbandDisabled = false; + if (pointCnt == 0) { + // First point in sweep, switch to correct source + FPGA::Disable(FPGA::Periphery::SourceRF); + lowbandDisabled = true; + } + if(lowbandDisabled && freqSuccess) { + // frequency is valid, can enable lowband source now + Si5351.Enable(SiChannel::LowbandSource); + Delay::us(1300); + lowbandDisabled = false; + } + + // At low frequencies the 1.LO feedthrough mixes with the 2.LO in the second mixer. + // Depending on the stimulus frequency, the resulting mixing product might alias to the 2.IF + // in the ADC which causes a spike. Check for this and shift the ADC sampling frequency if necessary + + uint32_t LO_mixing = (HW::getIF1() + frequency) - (HW::getIF1() - HW::getIF2()); + if(abs(Util::Alias(LO_mixing, HW::getADCRate()) - HW::getIF2()) <= actualBandwidth * 2) { + // the image is in or near the IF bandwidth and would cause a peak + // Use a slightly different ADC sample rate if possible + if(HW::getIF2() == HW::DefaultIF2) { + adcShiftRequired = true; + } + } + } else if(!FPGA::IsEnabled(FPGA::Periphery::SourceRF)){ + // first sweep point in highband is also halted, disable lowband source + Si5351.Disable(SiChannel::LowbandSource); + FPGA::Enable(FPGA::Periphery::SourceRF); } - } else if(!FPGA::IsEnabled(FPGA::Periphery::SourceRF)){ - // first sweep point in highband is also halted, disable lowband source - Si5351.Disable(SiChannel::LowbandSource); - FPGA::Enable(FPGA::Periphery::SourceRF); - } - if (pointCnt == 0) { - HAL_Delay(2); - } + if (pointCnt == 0) { + HAL_Delay(2); + } - if(adcShiftRequired) { - FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, alternativePrescaler); - FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, alternativePhaseInc); - adcShifted = true; - } else if(adcShifted) { - // reset to default value - FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, HW::getADCPrescaler()); - FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, HW::getDFTPhaseInc()); - adcShifted = false; - } + if(adcShiftRequired) { + FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, alternativePrescaler); + FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, alternativePhaseInc); + adcShifted = true; + } else if(adcShifted) { + // reset to default value + FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, HW::getADCPrescaler()); + FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, HW::getDFTPhaseInc()); + adcShifted = false; + } - if(usb_available_buffer() >= reservedUSBbuffer) { - // enough space available, can resume immediately - FPGA::ResumeHaltedSweep(); - } else { - // USB buffer could potentially overflow before next halted point, wait until more space is available. - // This function is called from a low level interrupt, need to dispatch to lower priority to allow USB - // handling to continue - STM::DispatchToInterrupt([](){ + if(usb_available_buffer() >= reservedUSBbuffer) { + // enough space available, can resume immediately + FPGA::ResumeHaltedSweep(); + } else { + // USB buffer could potentially overflow before next halted point, wait until more space is available. uint32_t start = HAL_GetTick(); while(usb_available_buffer() < reservedUSBbuffer) { if(HAL_GetTick() - start > 100) { @@ -457,8 +462,8 @@ void VNA::SweepHalted() { } } FPGA::ResumeHaltedSweep(); - }); - } + } + }); } void VNA::Stop() { diff --git a/Software/VNA_embedded/Inc/FreeRTOSConfig.h b/Software/VNA_embedded/Inc/FreeRTOSConfig.h index d372258..15f0e65 100644 --- a/Software/VNA_embedded/Inc/FreeRTOSConfig.h +++ b/Software/VNA_embedded/Inc/FreeRTOSConfig.h @@ -58,7 +58,7 @@ #define configUSE_PREEMPTION 1 #define configSUPPORT_STATIC_ALLOCATION 1 #define configSUPPORT_DYNAMIC_ALLOCATION 0 -#define configUSE_IDLE_HOOK 0 +#define configUSE_IDLE_HOOK 1 #define configUSE_TICK_HOOK 0 #define configCPU_CLOCK_HZ ( SystemCoreClock ) #define configTICK_RATE_HZ ((TickType_t)1000) diff --git a/Software/VNA_embedded/Inc/main.h b/Software/VNA_embedded/Inc/main.h index beb2f79..082fbbe 100644 --- a/Software/VNA_embedded/Inc/main.h +++ b/Software/VNA_embedded/Inc/main.h @@ -89,6 +89,10 @@ void Error_Handler(void); #define FPGA_PROGRAM_B_GPIO_Port GPIOB #define EN_6V_Pin GPIO_PIN_12 #define EN_6V_GPIO_Port GPIOB +#define FPGA_TRIGGER_OUT_Pin GPIO_PIN_11 +#define FPGA_TRIGGER_OUT_GPIO_Port GPIOC +#define FPGA_TRIGGER_IN_Pin GPIO_PIN_3 +#define FPGA_TRIGGER_IN_GPIO_Port GPIOB #define FPGA_RESET_Pin GPIO_PIN_5 #define FPGA_RESET_GPIO_Port GPIOB #define FPGA_DONE_Pin GPIO_PIN_9 diff --git a/Software/VNA_embedded/Src/app_freertos.c b/Software/VNA_embedded/Src/app_freertos.c index 28bd50e..c9d390c 100644 --- a/Software/VNA_embedded/Src/app_freertos.c +++ b/Software/VNA_embedded/Src/app_freertos.c @@ -55,6 +55,24 @@ /* GetIdleTaskMemory prototype (linked to static allocation support) */ void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); +/* Hook prototypes */ +void vApplicationIdleHook(void); + +/* USER CODE BEGIN 2 */ +__weak void vApplicationIdleHook( void ) +{ + /* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set + to 1 in FreeRTOSConfig.h. It will be called on each iteration of the idle + task. It is essential that code added to this hook function never attempts + to block in any way (for example, call xQueueReceive() with a block time + specified, or call vTaskDelay()). If the application makes use of the + vTaskDelete() API function (as this demo application does) then it is also + important that vApplicationIdleHook() is permitted to return to its calling + function, because it is the responsibility of the idle task to clean up + memory allocated by the kernel to any task that has since been deleted. */ +} +/* USER CODE END 2 */ + /* USER CODE BEGIN GET_IDLE_TASK_MEMORY */ static StaticTask_t xIdleTaskTCBBuffer; static StackType_t xIdleStack[configMINIMAL_STACK_SIZE]; diff --git a/Software/VNA_embedded/Src/main.c b/Software/VNA_embedded/Src/main.c index c2393a9..1ab5992 100644 --- a/Software/VNA_embedded/Src/main.c +++ b/Software/VNA_embedded/Src/main.c @@ -724,7 +724,7 @@ static void MX_GPIO_Init(void) HAL_GPIO_WritePin(FLASH_CS_GPIO_Port, FLASH_CS_Pin, GPIO_PIN_SET); /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOB, FPGA_PROGRAM_B_Pin|EN_6V_Pin|FPGA_RESET_Pin, GPIO_PIN_RESET); + HAL_GPIO_WritePin(GPIOB, FPGA_PROGRAM_B_Pin|EN_6V_Pin|FPGA_TRIGGER_IN_Pin|FPGA_RESET_Pin, GPIO_PIN_RESET); /*Configure GPIO pin : FPGA_INIT_B_Pin */ GPIO_InitStruct.Pin = FPGA_INIT_B_Pin; @@ -752,13 +752,19 @@ static void MX_GPIO_Init(void) GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(FPGA_INTR_GPIO_Port, &GPIO_InitStruct); - /*Configure GPIO pins : FPGA_PROGRAM_B_Pin EN_6V_Pin FPGA_RESET_Pin */ - GPIO_InitStruct.Pin = FPGA_PROGRAM_B_Pin|EN_6V_Pin|FPGA_RESET_Pin; + /*Configure GPIO pins : FPGA_PROGRAM_B_Pin EN_6V_Pin FPGA_TRIGGER_IN_Pin FPGA_RESET_Pin */ + GPIO_InitStruct.Pin = FPGA_PROGRAM_B_Pin|EN_6V_Pin|FPGA_TRIGGER_IN_Pin|FPGA_RESET_Pin; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + /*Configure GPIO pin : FPGA_TRIGGER_OUT_Pin */ + GPIO_InitStruct.Pin = FPGA_TRIGGER_OUT_Pin; + GPIO_InitStruct.Mode = GPIO_MODE_INPUT; + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + HAL_GPIO_Init(FPGA_TRIGGER_OUT_GPIO_Port, &GPIO_InitStruct); + /*Configure GPIO pin : FPGA_DONE_Pin */ GPIO_InitStruct.Pin = FPGA_DONE_Pin; GPIO_InitStruct.Mode = GPIO_MODE_INPUT; diff --git a/Software/VNA_embedded/VNA_embedded.ioc b/Software/VNA_embedded/VNA_embedded.ioc index 8897fba..1a13187 100644 --- a/Software/VNA_embedded/VNA_embedded.ioc +++ b/Software/VNA_embedded/VNA_embedded.ioc @@ -86,14 +86,16 @@ FREERTOS.INCLUDE_vTaskDelete=0 FREERTOS.INCLUDE_vTaskPrioritySet=0 FREERTOS.INCLUDE_vTaskSuspend=1 FREERTOS.INCLUDE_xTaskResumeFromISR=0 -FREERTOS.IPParameters=Tasks01,INCLUDE_vTaskDelete,INCLUDE_vTaskPrioritySet,INCLUDE_uxTaskPriorityGet,INCLUDE_xTaskResumeFromISR,INCLUDE_vTaskSuspend,MEMORY_ALLOCATION,configTOTAL_HEAP_SIZE,configENABLE_BACKWARD_COMPATIBILITY,configUSE_MUTEXES,FootprintOK,configUSE_NEWLIB_REENTRANT +FREERTOS.IPParameters=Tasks01,INCLUDE_vTaskDelete,INCLUDE_vTaskPrioritySet,INCLUDE_uxTaskPriorityGet,INCLUDE_xTaskResumeFromISR,INCLUDE_vTaskSuspend,MEMORY_ALLOCATION,configTOTAL_HEAP_SIZE,configENABLE_BACKWARD_COMPATIBILITY,configUSE_MUTEXES,FootprintOK,configUSE_NEWLIB_REENTRANT,configUSE_IDLE_HOOK FREERTOS.MEMORY_ALLOCATION=1 FREERTOS.Tasks01=defaultTask,0,1024,StartDefaultTask,Default,NULL,Static,defaultTaskBuffer,defaultTaskControlBlock FREERTOS.configENABLE_BACKWARD_COMPATIBILITY=1 FREERTOS.configTOTAL_HEAP_SIZE=2048 +FREERTOS.configUSE_IDLE_HOOK=1 FREERTOS.configUSE_MUTEXES=1 FREERTOS.configUSE_NEWLIB_REENTRANT=1 File.Version=6 +GPIO.groupedBy=Group By Peripherals I2C2.I2C_Speed_Mode=I2C_Fast I2C2.IPParameters=Timing,I2C_Speed_Mode I2C2.Timing=0x00F07BFF @@ -134,24 +136,26 @@ Mcu.Pin21=PA13 Mcu.Pin22=PA14 Mcu.Pin23=PA15 Mcu.Pin24=PC10 -Mcu.Pin25=PB4 -Mcu.Pin26=PB5 -Mcu.Pin27=PB6 -Mcu.Pin28=PB9 -Mcu.Pin29=VP_ADC1_TempSens_Input +Mcu.Pin25=PC11 +Mcu.Pin26=PB3 +Mcu.Pin27=PB4 +Mcu.Pin28=PB5 +Mcu.Pin29=PB6 Mcu.Pin3=PA3 -Mcu.Pin30=VP_FREERTOS_VS_CMSIS_V1 -Mcu.Pin31=VP_SYS_VS_tim17 -Mcu.Pin32=VP_SYS_VS_DBSignals -Mcu.Pin33=VP_TIM1_VS_ClockSourceINT -Mcu.Pin34=VP_TIM2_VS_ClockSourceINT +Mcu.Pin30=PB9 +Mcu.Pin31=VP_ADC1_TempSens_Input +Mcu.Pin32=VP_FREERTOS_VS_CMSIS_V1 +Mcu.Pin33=VP_SYS_VS_tim17 +Mcu.Pin34=VP_SYS_VS_DBSignals +Mcu.Pin35=VP_TIM1_VS_ClockSourceINT +Mcu.Pin36=VP_TIM2_VS_ClockSourceINT Mcu.Pin4=PA4 Mcu.Pin5=PA5 Mcu.Pin6=PA6 Mcu.Pin7=PA7 Mcu.Pin8=PC4 Mcu.Pin9=PB0 -Mcu.PinsNb=35 +Mcu.PinsNb=37 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32G431CBUx @@ -270,6 +274,10 @@ PB2.GPIOParameters=GPIO_Label PB2.GPIO_Label=FPGA_PROGRAM_B PB2.Locked=true PB2.Signal=GPIO_Output +PB3.GPIOParameters=GPIO_Label +PB3.GPIO_Label=FPGA_TRIGGER_IN +PB3.Locked=true +PB3.Signal=GPIO_Output PB4.Locked=true PB4.Mode=Sink_AllSignals PB4.Signal=UCPD1_CC2 @@ -287,6 +295,11 @@ PB9.Signal=GPIO_Input PC10.Locked=true PC10.Mode=Asynchronous PC10.Signal=USART3_TX +PC11.GPIOParameters=GPIO_PuPd,GPIO_Label +PC11.GPIO_Label=FPGA_TRIGGER_OUT +PC11.GPIO_PuPd=GPIO_PULLDOWN +PC11.Locked=true +PC11.Signal=GPIO_Input PC4.GPIOParameters=GPIO_Pu PC4.GPIO_Pu=GPIO_PULLUP PC4.Locked=true @@ -311,7 +324,7 @@ ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=true -ProjectManager.LastFirmware=true +ProjectManager.LastFirmware=false ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Src ProjectManager.NoMain=false