Zero span improvements
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6393ae7fc3
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@ -843,9 +843,8 @@ void VNA::NewDatapoint(Protocol::Datapoint d)
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auto vd = VNAData(d);
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auto vd = VNAData(d);
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if(!settings.zerospan) {
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vd = average.process(vd);
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vd = average.process(vd);
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}
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if(calMeasuring) {
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if(calMeasuring) {
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if(average.currentSweep() == averages) {
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if(average.currentSweep() == averages) {
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// this is the last averaging sweep, use values for calibration
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// this is the last averaging sweep, use values for calibration
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@ -9,7 +9,7 @@ void Delay::Init() {
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// enable update interrupt
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// enable update interrupt
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TIM1->DIER |= TIM_DIER_UIE;
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TIM1->DIER |= TIM_DIER_UIE;
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HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, 0, 0);
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HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, 6, 0);
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HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
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HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
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TIM1->CR1 |= TIM_CR1_CEN;
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TIM1->CR1 |= TIM_CR1_CEN;
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@ -36,8 +36,8 @@ void Delay::ms(uint32_t t) {
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}
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}
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}
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}
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void Delay::us(uint32_t t) {
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void Delay::us(uint32_t t) {
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uint64_t start = get_us();
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uint64_t start = TIM1->CNT;
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while(start + t > get_us());
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while(TIM1->CNT - start < t);
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}
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}
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extern "C" {
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extern "C" {
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@ -61,8 +61,8 @@ static void ReadComplete(const FPGA::SamplingResult &result) {
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}
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}
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static void FPGA_Interrupt(void*) {
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static void FPGA_Interrupt(void*) {
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lastISR = Delay::get_us();
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FPGA::InitiateSampleRead(ReadComplete);
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FPGA::InitiateSampleRead(ReadComplete);
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lastISR = Delay::get_us();
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}
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}
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void HW::Work() {
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void HW::Work() {
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