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WIP: synchronization

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This commit is contained in:
Jan Käberich 2022-08-07 13:28:31 +02:00
parent 58918f81c1
commit 7b3aa6e158
7 changed files with 46 additions and 46 deletions
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60
FPGA/VNA/Sweep.vhd
View File

@ -153,7 +153,7 @@ begin
if RESET = '1' then
point_cnt <= (others => '0');
stage_cnt <= (others => '0');
state <= TriggerSetup;
state <= WaitTriggerLow;
START_SAMPLING <= '0';
RELOAD_PLL_REGS <= '0';
SWEEP_HALTED <= '0';
@ -164,9 +164,22 @@ begin
source_active <= '0';
else
case state is
when WaitTriggerLow =>
if SYNC_ENABLED = '1' and (std_logic_vector(stage_cnt) = PORT1_STAGE or std_logic_vector(stage_cnt) = PORT2_STAGE) then
TRIGGER_OUT <= '0';
end if;
if TRIGGER_IN = '0' or SYNC_ENABLED = '0' then
TRIGGER_OUT <= '0';
if stage_cnt = 0 then
-- first stage in point, need to trigger PLL setup
state <= TriggerSetup;
else
-- PLLs already configured correctly
state <= SettingUp;
end if;
end if;
when TriggerSetup =>
RELOAD_PLL_REGS <= '1';
stage_cnt <= (others => '0');
if PLL_RELOAD_DONE = '0' then
state <= SettingUp;
end if;
@ -206,24 +219,16 @@ begin
if settling_cnt > 0 then
settling_cnt <= settling_cnt - 1;
else
if SYNC_ENABLED = '1' then
-- need to wait for the trigger
state <= WaitTriggerHigh;
if source_active = '1' then
-- this device generates the stimulus signal, it needs start the trigger itself
TRIGGER_OUT <= '1';
end if;
else
-- can start sampling directly
START_SAMPLING <= '1';
if SAMPLING_BUSY = '1' then
state <= Exciting;
end if;
-- need to wait for the trigger
state <= WaitTriggerHigh;
if SYNC_ENABLED = '1' and (std_logic_vector(stage_cnt) = PORT1_STAGE or std_logic_vector(stage_cnt) = PORT2_STAGE) then
-- this device generates the stimulus signal, it needs start the trigger itself
TRIGGER_OUT <= '1';
end if;
end if;
when WaitTriggerHigh =>
if TRIGGER_IN = '1' then
TRIGGER_OUT <= '1'; -- pass on trigger signal
if TRIGGER_IN = '1' or SYNC_ENABLED = '0' then
TRIGGER_OUT <= SYNC_ENABLED; -- pass on trigger signal if enabled
START_SAMPLING <= '1';
if SAMPLING_BUSY = '1' then
state <= Exciting;
@ -234,26 +239,13 @@ begin
START_SAMPLING <= '0';
if SAMPLING_BUSY = '0' then
RESULT_INDEX <= std_logic_vector(stage_cnt) & std_logic_vector(point_cnt);
if SYNC_ENABLED = '1' then
state <= WaitTriggerLow;
if source_active = '1' then
-- this device generated the stimulus signal, it needs to reset the trigger itself
TRIGGER_OUT <= '0';
end if;
else
state <= SamplingDone;
end if;
end if;
when WaitTriggerLow =>
if TRIGGER_IN = '0' then
TRIGGER_OUT <= '0';
state <= SamplingDone;
end if;
when SamplingDone =>
if stage_cnt < unsigned(STAGES) then
stage_cnt <= stage_cnt + 1;
-- can go directly to settling
state <= Settling;
-- can go directly to preperation for next stage
state <= WaitTriggerLow;
else
state <= NextPoint;
end if;
@ -261,10 +253,12 @@ begin
when NextPoint =>
if point_cnt < unsigned(NPOINTS) then
point_cnt <= point_cnt + 1;
state <= TriggerSetup;
stage_cnt <= (others => '0');
state <= WaitTriggerLow;
else
point_cnt <= (others => '0');
state <= Done;
TRIGGER_OUT <= '0';
end if;
when others =>
end case;

14
FPGA/VNA/VNA.gise
View File

@ -224,7 +224,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1659800083" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1659800083">
<transform xil_pn:end_ts="1659868712" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1659868712">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@ -253,7 +253,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1659829999" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1659829990">
<transform xil_pn:end_ts="1659869263" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1659869254">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -275,7 +275,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1659830003" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1659829999">
<transform xil_pn:end_ts="1659869266" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1659869263">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
@ -284,7 +284,7 @@
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1659830122" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1659830003">
<transform xil_pn:end_ts="1659869298" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1659869266">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -298,7 +298,7 @@
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1659830134" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1659830122">
<transform xil_pn:end_ts="1659869311" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1659869298">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -312,7 +312,7 @@
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1659830141" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1659830134">
<transform xil_pn:end_ts="1659869318" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1659869311">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@ -365,7 +365,7 @@
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1659830134" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1659830131">
<transform xil_pn:end_ts="1659869311" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1659869308">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

BIN
FPGA/VNA/top.bin
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Binary file not shown.

7
Software/PC_Application/Device/virtualdevice.cpp
View File

@ -588,7 +588,12 @@ void VirtualDevice::compoundDatapointReceivecd(Protocol::VNADatapoint<32> *data,
if(!std::isnan(ref.real()) && !std::isnan(input.real())) {
// got both required measurements
QString name = "S"+QString::number(i+1)+QString::number(map.first+1);
m.measurements[name] = input / ref;
auto S = input / ref;
if(inputDevice != stimulusDev) {
// can't use phase information when measuring across devices
S = abs(S);
}
m.measurements[name] = S;
}
}
}

6
Software/PC_Application/Traces/trace.cpp
View File

@ -143,7 +143,7 @@ void Trace::addData(const Trace::Data &d, const VirtualDevice::SASettings &s, in
}
void Trace::setName(QString name) {
name = name;
_name = name;
emit nameChanged();
}
@ -305,8 +305,8 @@ void Trace::fromMath()
}
void Trace::setColor(QColor color) {
if(color != color) {
color = color;
if(_color != color) {
_color = color;
emit colorChanged(this);
}
}

3
Software/PC_Application/Traces/traceeditdialog.cpp
View File

@ -323,6 +323,7 @@ TraceEditDialog::TraceEditDialog(Trace &t, QWidget *parent) :
t.swapMathOrder(index.row());
ui->view->setCurrentIndex(index.sibling(index.row() + 1, 0));
});
connect(ui->buttonBox->button(QDialogButtonBox::Ok), &QPushButton::clicked, this, &TraceEditDialog::okClicked);
}
TraceEditDialog::~TraceEditDialog()
@ -330,7 +331,7 @@ TraceEditDialog::~TraceEditDialog()
delete ui;
}
void TraceEditDialog::on_buttonBox_accepted()
void TraceEditDialog::okClicked()
{
trace.setName(ui->name->text());
trace.setVelocityFactor(ui->vFactor->value());

2
Software/PC_Application/Traces/traceeditdialog.h
View File

@ -46,7 +46,7 @@ public:
~TraceEditDialog();
private slots:
void on_buttonBox_accepted();
void okClicked();
private:
Ui::TraceEditDialog *ui;