diff --git a/Documentation/DeveloperInfo/FPGA_protocol.tex b/Documentation/DeveloperInfo/FPGA_protocol.tex
index 9660519..40acb96 100644
--- a/Documentation/DeveloperInfo/FPGA_protocol.tex
+++ b/Documentation/DeveloperInfo/FPGA_protocol.tex
@@ -386,7 +386,7 @@ Setting & Window type\\
 \begin{itemize}
 \item \textbf{Presc[7:0]:} Amount of FPGA clock cycles between ADC samples.
 $$ SR_{ADC} = \frac{\SI{102.4}{\mega\hertz}}{Presc} $$
-The minimum value for this register is 111, which results in a samplerate of roughly \SI{922.5}{\kilo\hertz}. If Presc is set to a lower value, the data acquisition from the ADC is not done when the next sample starts and samples will be skipped.
+The minimum value for this register is 112, which results in a samplerate of roughly \SI{914.3}{\kilo\hertz}. If Presc is set to a lower value, the data acquisition from the ADC is not done when the next sample starts and samples will be skipped.
 \end{itemize}
 
 \subsection{Phase Increment: 0x05}
@@ -446,7 +446,7 @@ See datasheet of MAX2871 for bit descriptions. Bits for the fields N, FRAC, M, V
 \label{dft}
 In addition to the single bin DFT configured through the ADC prescaler and phase increment registers (see \ref{reg:ADC} and \ref{reg:phaseinc}), the FPGA also includes a multiple point DFT. This DFT only operates on the port 1 and port 2 receivers and is intended to speed up spectrum analyzer measurements. If enabled, the DFT runs in parallel to all other calculations.
 
-The DFT has a fixed number of bins (64), but the frequencies these bins correspond to can be changed.
+The DFT has a fixed number of bins (96), but the frequencies these bins correspond to can be changed.
 
 \subsubsection{DFT\_FIRST\_BIN: 0x12}
 \begin{center}
diff --git a/FPGA/VNA/DFT.vhd b/FPGA/VNA/DFT.vhd
index 9a90d40..8975b9b 100644
--- a/FPGA/VNA/DFT.vhd
+++ b/FPGA/VNA/DFT.vhd
@@ -33,8 +33,8 @@ entity DFT is
 	Generic (BINS : integer);
     Port ( CLK : in  STD_LOGIC;
            RESET : in  STD_LOGIC;
-           PORT1 : in  STD_LOGIC_VECTOR (15 downto 0);
-           PORT2 : in  STD_LOGIC_VECTOR (15 downto 0);
+           PORT1 : in  STD_LOGIC_VECTOR (17 downto 0);
+           PORT2 : in  STD_LOGIC_VECTOR (17 downto 0);
            NEW_SAMPLE : in  STD_LOGIC;
 			  NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
            BIN1_PHASEINC : in  STD_LOGIC_VECTOR (15 downto 0);
@@ -45,25 +45,14 @@ entity DFT is
 end DFT;
 
 architecture Behavioral of DFT is
-COMPONENT dft_result
-GENERIC(depth : integer);
-PORT(
-	CLK : IN std_logic;
-	READ_ADDRESS : in integer range 0 to depth-1;
-	WRITE_ADDRESS : in integer range 0 to depth-1;
-	DATA_IN : IN std_logic_vector(191 downto 0);
-	WE : IN std_logic;          
-	DATA_OUT : OUT std_logic_vector(191 downto 0)
-	);
-END COMPONENT;
 COMPONENT result_bram
   PORT (
     clka : IN STD_LOGIC;
     wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
-    addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
     clkb : IN STD_LOGIC;
-    addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+    addrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0)
   );
 END COMPONENT;
@@ -75,14 +64,6 @@ COMPONENT SinCos
     sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
   );
 END COMPONENT;
-COMPONENT SinCosMult
-  PORT (
-    clk : IN STD_LOGIC;
-    a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-    b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-    p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
-  );
-END COMPONENT;
 COMPONENT DSP_SLICE
   PORT (
     clk : IN STD_LOGIC;
@@ -120,16 +101,16 @@ END COMPONENT;
 	
 	signal read_address : integer range 0 to BINS-1;
 	signal write_address : integer range 0 to BINS-1;
-	signal read_address_vector : std_logic_vector(5 downto 0);
-	signal write_address_vector : std_logic_vector(5 downto 0);
+	signal read_address_vector : std_logic_vector(7 downto 0);
+	signal write_address_vector : std_logic_vector(7 downto 0);
 	signal we : std_logic_vector(0 downto 0);
 	signal ram_in : std_logic_vector(191 downto 0);
 	signal ram_out : std_logic_vector(191 downto 0);
 	
 	type States is (WaitingForSample, WaitMult, WaitSinCos, Busy, Ready);
 	signal state : States;
-	signal port1_latch : std_logic_vector(15 downto 0);
-	signal port2_latch : std_logic_vector(15 downto 0);
+	signal port1_latch : std_logic_vector(17 downto 0);
+	signal port2_latch : std_logic_vector(17 downto 0);
 	
 	signal phase : std_logic_vector(31 downto 0);
 	signal phase_inc : std_logic_vector(31 downto 0);
@@ -219,8 +200,8 @@ begin
 		doutb => ram_out
 	);
 	
-	read_address_vector <= std_logic_vector(to_unsigned(read_address, 6));
-	write_address_vector <= std_logic_vector(to_unsigned(write_address, 6));
+	read_address_vector <= std_logic_vector(to_unsigned(read_address, 8));
+	write_address_vector <= std_logic_vector(to_unsigned(write_address, 8));
 	OUTPUT <= ram_out;
 	
 	mult1_c <= ram_out(191 downto 144);
@@ -294,13 +275,13 @@ begin
 							mult_enable <= '1';
 							read_address <= 1;
 							-- sign extended multiplication
-							mult1_a <= port1_latch(15) & port1_latch(15) & port1_latch;
+							mult1_a <= port1_latch;
 							mult1_b <= sine(15) & sine(15) & sine;
-							mult2_a <= port1_latch(15) & port1_latch(15) & port1_latch;
+							mult2_a <= port1_latch;
 							mult2_b <= cosine(15) & cosine(15) & cosine;
-							mult3_a <= port2_latch(15) & port2_latch(15) & port2_latch;
+							mult3_a <= port2_latch;
 							mult3_b <= sine(15) & sine(15) & sine;
-							mult4_a <= port2_latch(15) & port2_latch(15) & port2_latch;
+							mult4_a <= port2_latch;
 							mult4_b <= cosine(15) & cosine(15) & cosine;
 							state <= BUSY;
 							if sample_cnt = 0 then
@@ -319,13 +300,13 @@ begin
 						RESULT_READY <= '0';
 						phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
 						-- sign extended multiplication
-						mult1_a <= port1_latch(15) & port1_latch(15) & port1_latch;
+						mult1_a <= port1_latch;
 						mult1_b <= sine(15) & sine(15) & sine;
-						mult2_a <= port1_latch(15) & port1_latch(15) & port1_latch;
+						mult2_a <= port1_latch;
 						mult2_b <= cosine(15) & cosine(15) & cosine;
-						mult3_a <= port2_latch(15) & port2_latch(15) & port2_latch;
+						mult3_a <= port2_latch;
 						mult3_b <= sine(15) & sine(15) & sine;
-						mult4_a <= port2_latch(15) & port2_latch(15) & port2_latch;
+						mult4_a <= port2_latch;
 						mult4_b <= cosine(15) & cosine(15) & cosine;
 						if bin_cnt >= 3 then
 							-- multiplier result is available, advance write address
diff --git a/FPGA/VNA/Sampling.vhd b/FPGA/VNA/Sampling.vhd
index f1b2287..0c752e2 100644
--- a/FPGA/VNA/Sampling.vhd
+++ b/FPGA/VNA/Sampling.vhd
@@ -35,9 +35,9 @@ entity Sampling is
            RESET : in  STD_LOGIC;
 			  ADC_PRESCALER : in STD_LOGIC_VECTOR(7 downto 0);
 			  PHASEINC : in STD_LOGIC_VECTOR(11 downto 0);
-           PORT1 : in  STD_LOGIC_VECTOR (15 downto 0);
-           PORT2 : in  STD_LOGIC_VECTOR (15 downto 0);
-           REF : in  STD_LOGIC_VECTOR (15 downto 0);
+           PORT1 : in  STD_LOGIC_VECTOR (17 downto 0);
+           PORT2 : in  STD_LOGIC_VECTOR (17 downto 0);
+           REF : in  STD_LOGIC_VECTOR (17 downto 0);
 			  ADC_START : out STD_LOGIC;
            NEW_SAMPLE : in  STD_LOGIC;
            DONE : out  STD_LOGIC;
@@ -62,13 +62,16 @@ COMPONENT SinCos
     sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
   );
 END COMPONENT;
-COMPONENT SinCosMult
-  PORT (
-    clk : IN STD_LOGIC;
-    a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-    b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
-    p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
-  );
+COMPONENT DSP_SLICE
+	PORT (
+		clk : IN STD_LOGIC;
+		ce : IN STD_LOGIC;
+		sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+		a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+		b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+		c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+		p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+	);
 END COMPONENT;
 COMPONENT window
 PORT(
@@ -79,12 +82,12 @@ PORT(
 	);
 END COMPONENT;
 
-	signal p1_I : signed(47 downto 0);
-	signal p1_Q : signed(47 downto 0);
-	signal p2_I : signed(47 downto 0);
-	signal p2_Q : signed(47 downto 0);
-	signal r_I : signed(47 downto 0);
-	signal r_Q : signed(47 downto 0);
+	signal p1_I : std_logic_vector(47 downto 0);
+	signal p1_Q : std_logic_vector(47 downto 0);
+	signal p2_I : std_logic_vector(47 downto 0);
+	signal p2_Q : std_logic_vector(47 downto 0);
+	signal r_I : std_logic_vector(47 downto 0);
+	signal r_Q : std_logic_vector(47 downto 0);
 	signal clk_cnt : integer range 0 to 255;
 	signal sample_cnt : integer range 0 to 131071;
 	signal samples_to_take : integer range 0 to 131071;
@@ -93,16 +96,15 @@ END COMPONENT;
 	signal sine : std_logic_vector(15 downto 0);
 	signal cosine : std_logic_vector(15 downto 0);
 	
-	signal mult1_I : std_logic_vector(31 downto 0);
-	signal mult1_Q : std_logic_vector(31 downto 0);
-	signal mult2_I : std_logic_vector(31 downto 0);
-	signal mult2_Q : std_logic_vector(31 downto 0);
-	signal multR_I : std_logic_vector(31 downto 0);
-	signal multR_Q : std_logic_vector(31 downto 0);
+	signal mult_a : std_logic_vector(17 downto 0);
+	signal mult_b : std_logic_vector(17 downto 0);
+	signal mult_c : std_logic_vector(47 downto 0);
+	signal mult_p : std_logic_vector(47 downto 0);
 	
-	signal last_sample : std_logic;
+	signal mult_enable : std_logic;
+	signal mult_accumulate : std_logic_vector(0 downto 0);
 	
-	type States is (Idle, Sampling, WaitForMult, Accumulating, Ready);
+	type States is (Idle, Sampling, P1Q, P2I, P2Q, RI, RQ, SaveP1Q, SaveP2I, SaveP2Q, SaveRI, SaveRQ, Ready);
 	signal state : States;
 begin
 -- Always fails for simulation, comment out
@@ -117,49 +119,21 @@ begin
 		cosine => cosine,
 		sine => sine
 	);
-	Port1_I_Mult : SinCosMult
+
+	Mult : DSP_SLICE
 	PORT MAP (
 		clk => CLK,
-		a => PORT1,
-		b => cosine,
-		p => mult1_I
-	);
-	Port1_Q_Mult : SinCosMult
-	PORT MAP (
-		clk => CLK,
-		a => PORT1,
-		b => sine,
-		p => mult1_Q
-	);
-	Port2_I_Mult : SinCosMult
-	PORT MAP (
-		clk => CLK,
-		a => PORT2,
-		b => cosine,
-		p => mult2_I
-	);
-	Port2_Q_Mult : SinCosMult
-	PORT MAP (
-		clk => CLK,
-		a => PORT2,
-		b => sine,
-		p => mult2_Q
-	);
-	Ref_I_Mult : SinCosMult
-	PORT MAP (
-		clk => CLK,
-		a => REF,
-		b => cosine,
-		p => multR_I
-	);
-	Ref_Q_Mult : SinCosMult
-	PORT MAP (
-		clk => CLK,
-		a => REF,
-		b => sine,
-		p => multR_Q
+		ce => mult_enable,
+		sel => mult_accumulate,
+		a => mult_a,
+		b => mult_b,
+		c => mult_c,
+		p => mult_p
 	);
 	
+	-- sign extend b input of multiplier (sin/cos)
+	mult_b(17 downto 16) <= mult_b(15) & mult_b(15);
+	
 	process(CLK, RESET)
 	begin
 		if rising_edge(CLK) then
@@ -172,15 +146,14 @@ begin
 				clk_cnt <= 0;
 				sample_cnt <= 0;
 				phase <= (others => '0');
+				mult_enable <= '0';
+				mult_accumulate <= "0";
 			else
 				-- when not idle, generate pulses for ADCs
 				if state /= Idle then
-					if clk_cnt = unsigned(ADC_PRESCALER) - 1 and last_sample = '0' then
-						ADC_START <= '1';
+					if clk_cnt = unsigned(ADC_PRESCALER) - 1 then
 						if sample_cnt < samples_to_take then
-							sample_cnt <= sample_cnt + 1;
-						else
-							last_sample <= '1';
+							ADC_START <= '1';
 						end if;
 						clk_cnt <= 0;
 					else
@@ -193,50 +166,116 @@ begin
 				-- handle state transitions
 				case state is
 					when Idle =>
-						last_sample <= '0';
 						sample_cnt <= 0;
 						DONE <= '0';
 						PRE_DONE <= '0';
 						ACTIVE <= '0';
 						clk_cnt <= 0;
 						phase <= (others => '0');
-						p1_I <= (others => '0');
-						p1_Q <= (others => '0');
-						p2_I <= (others => '0');
-						p2_Q <= (others => '0');
-						r_I <= (others => '0');
-						r_Q <= (others => '0');
-						phase <= (others => '0');
+						mult_enable <= '0';
+						mult_accumulate <= "0";
 						if START = '1' then
 							state <= Sampling;
-							samples_to_take <= to_integer(unsigned(SAMPLES & "0000") - 1);
+							samples_to_take <= to_integer(unsigned(SAMPLES & "0000"));
 						end if;
 					when Sampling =>
 						DONE <= '0';
 						PRE_DONE <= '0';
 						ACTIVE <= '1';
+						mult_enable <= '0';
 						if NEW_SAMPLE = '1' then
-							state <= WaitForMult;
+							sample_cnt <= sample_cnt + 1;
+							mult_enable <= '1';
+							mult_a <= PORT1;
+							mult_b(15 downto 0) <= cosine;
+							mult_c <= p1_I;
+							state <= P1Q;
 						end if;
-					when WaitForMult =>
-						DONE <= '0';
-						PRE_DONE <= '0';
-						ACTIVE <= '1';
-						state <= Accumulating;
-					when Accumulating =>
-						-- multipliers are finished with the sample
-						p1_I <= p1_I + signed(mult1_I);
-						p1_Q <= p1_Q + signed(mult1_Q);
-						p2_I <= p2_I + signed(mult2_I);
-						p2_Q <= p2_Q + signed(mult2_Q);
-						r_I <= r_I + signed(multR_I);
-						r_Q <= r_Q + signed(multR_Q);
-						-- advance phase
+					when P1Q =>
 						ACTIVE <= '1';
 						DONE <= '0';
 						PRE_DONE <= '0';
+						mult_enable <= '1';
+						mult_a <= PORT1;
+						mult_b(15 downto 0) <= sine;
+						mult_c <= p1_Q;
+						state <= P2I;
+					when P2I =>
+						ACTIVE <= '1';
+						DONE <= '0';
+						PRE_DONE <= '0';
+						mult_enable <= '1';
+						mult_a <= PORT2;
+						mult_b(15 downto 0) <= cosine;
+						mult_c <= p2_I;
+						state <= P2Q;
+					when P2Q =>
+						ACTIVE <= '1';
+						DONE <= '0';
+						PRE_DONE <= '0';
+						mult_enable <= '1';
+						mult_a <= PORT2;
+						mult_b(15 downto 0) <= sine;
+						mult_c <= p2_Q;
+						state <= RI;
+					when RI =>
+						ACTIVE <= '1';
+						DONE <= '0';
+						PRE_DONE <= '0';
+						mult_enable <= '1';
+						mult_a <= REF;
+						mult_b(15 downto 0) <= cosine;
+						mult_c <= r_I;
+						state <= RQ;						
+					when RQ =>
+						ACTIVE <= '1';
+						DONE <= '0';
+						PRE_DONE <= '0';
+						mult_enable <= '1';
+						mult_a <= REF;
+						mult_b(15 downto 0) <= sine;
+						mult_c <= r_Q;
+						-- first result is available
+						p1_I <= mult_p;
+						state <= SaveP1Q;
+					when SaveP1Q =>
+						ACTIVE <= '1';
+						DONE <= '0';
+						PRE_DONE <= '0';
+						mult_enable <= '1';
+						p1_Q <= mult_p;
+						state <= SaveP2I;
+					when SaveP2I =>
+						ACTIVE <= '1';
+						DONE <= '0';
+						PRE_DONE <= '0';
+						mult_enable <= '1';
+						p2_I <= mult_p;
+						state <= SaveP2Q;
+					when SaveP2Q =>
+						ACTIVE <= '1';
+						DONE <= '0';
+						PRE_DONE <= '0';
+						mult_enable <= '1';
+						p2_Q <= mult_p;
+						state <= SaveRI;
+					when SaveRI =>
+						ACTIVE <= '1';
+						DONE <= '0';
+						PRE_DONE <= '0';
+						mult_enable <= '1';
+						r_I <= mult_p;
+						state <= SaveRQ;
+					when SaveRQ =>
+						ACTIVE <= '1';
+						DONE <= '0';
+						PRE_DONE <= '0';
+						mult_enable <= '0';
+						r_Q <= mult_p;
+						-- from now on accumulate results
+						mult_accumulate <= "1";
 						phase <= std_logic_vector(unsigned(phase) + unsigned(PHASEINC));
-						if last_sample = '0' then
+						if sample_cnt < samples_to_take then
 							state <= Sampling;
 						else
 							state <= Ready;
@@ -245,12 +284,13 @@ begin
 						ACTIVE <= '1';
 						DONE <= '1';
 						PRE_DONE <= '1';
-						PORT1_I <= std_logic_vector(p1_I);
-						PORT1_Q <= std_logic_vector(p1_Q);
-						PORT2_I <= std_logic_vector(p2_I);
-						PORT2_Q <= std_logic_vector(p2_Q);
-						REF_I <= std_logic_vector(r_I);
-						REF_Q <= std_logic_vector(r_Q);
+						mult_enable <= '0';
+						PORT1_I <= p1_I;
+						PORT1_Q <= p1_Q;
+						PORT2_I <= p2_I;
+						PORT2_Q <= p2_Q;
+						REF_I <= r_I;
+						REF_Q <= r_Q;
 						state <= Idle;
 				end case;
 			end if;
diff --git a/FPGA/VNA/Test_DFT.vhd b/FPGA/VNA/Test_DFT.vhd
index 2bd28ad..85ecc36 100644
--- a/FPGA/VNA/Test_DFT.vhd
+++ b/FPGA/VNA/Test_DFT.vhd
@@ -44,8 +44,8 @@ ARCHITECTURE behavior OF Test_DFT IS
     PORT(
          CLK : IN  std_logic;
          RESET : IN  std_logic;
-         PORT1 : IN  std_logic_vector(15 downto 0);
-         PORT2 : IN  std_logic_vector(15 downto 0);
+         PORT1 : IN  std_logic_vector(17 downto 0);
+         PORT2 : IN  std_logic_vector(17 downto 0);
          NEW_SAMPLE : IN  std_logic;
 			NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
          BIN1_PHASEINC : IN  std_logic_vector(15 downto 0);
@@ -60,8 +60,8 @@ ARCHITECTURE behavior OF Test_DFT IS
    --Inputs
    signal CLK : std_logic := '0';
    signal RESET : std_logic := '0';
-   signal PORT1 : std_logic_vector(15 downto 0) := (others => '0');
-   signal PORT2 : std_logic_vector(15 downto 0) := (others => '0');
+   signal PORT1 : std_logic_vector(17 downto 0) := (others => '0');
+   signal PORT2 : std_logic_vector(17 downto 0) := (others => '0');
    signal NEW_SAMPLE : std_logic := '0';
    signal BIN1_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
    signal DIFFBIN_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
@@ -109,11 +109,11 @@ BEGIN
    begin		
       -- hold reset state for 100 ns.
 		RESET <= '1';
-		PORT1 <= "1000000000000000";
-		PORT2 <= "0100000000000000";
+		PORT1 <= "100000000000000000";
+		PORT2 <= "010000000000000000";
 		BIN1_PHASEINC <= "0100000000000000";
 		DIFFBIN_PHASEINC <= "0010000000000000";
-		NSAMPLES <= "0000000000000011";
+		NSAMPLES <= "0000000000011";
       wait for 100 ns;	
 		RESET <= '0';
       wait for CLK_period*10;
diff --git a/FPGA/VNA/Test_SPICommands.vhd b/FPGA/VNA/Test_SPICommands.vhd
index 3bdc1da..957a524 100644
--- a/FPGA/VNA/Test_SPICommands.vhd
+++ b/FPGA/VNA/Test_SPICommands.vhd
@@ -48,19 +48,18 @@ ARCHITECTURE behavior OF Test_SPICommands IS
          MISO : OUT  std_logic;
          NSS : IN  std_logic;
          NEW_SAMPLING_DATA : IN  std_logic;
-         SAMPLING_RESULT : IN  std_logic_vector(287 downto 0);
+         SAMPLING_RESULT : IN  std_logic_vector(303 downto 0);
          SOURCE_UNLOCKED : IN  std_logic;
          LO_UNLOCKED : IN  std_logic;
          MAX2871_DEF_4 : OUT  std_logic_vector(31 downto 0);
          MAX2871_DEF_3 : OUT  std_logic_vector(31 downto 0);
          MAX2871_DEF_1 : OUT  std_logic_vector(31 downto 0);
          MAX2871_DEF_0 : OUT  std_logic_vector(31 downto 0);
-         SWEEP_DATA : OUT  std_logic_vector(111 downto 0);
+         SWEEP_DATA : OUT  std_logic_vector(95 downto 0);
          SWEEP_ADDRESS : OUT  std_logic_vector(12 downto 0);
          SWEEP_WRITE : OUT  std_logic_vector(0 downto 0);
          SWEEP_POINTS : OUT  std_logic_vector(12 downto 0);
-         NSAMPLES : OUT  std_logic_vector(16 downto 0);
-         SETTLING_TIME : OUT  std_logic_vector(15 downto 0);
+         NSAMPLES : OUT  std_logic_vector(12 downto 0);
          PORT1_EN : OUT  std_logic;
          PORT2_EN : OUT  std_logic;
          REF_EN : OUT  std_logic;
@@ -80,7 +79,7 @@ ARCHITECTURE behavior OF Test_SPICommands IS
    signal MOSI : std_logic := '0';
    signal NSS : std_logic := '0';
    signal NEW_SAMPLING_DATA : std_logic := '0';
-   signal SAMPLING_RESULT : std_logic_vector(287 downto 0) := (others => '0');
+   signal SAMPLING_RESULT : std_logic_vector(303 downto 0) := (others => '0');
    signal SOURCE_UNLOCKED : std_logic := '1';
    signal LO_UNLOCKED : std_logic := '1';
 
@@ -90,12 +89,11 @@ ARCHITECTURE behavior OF Test_SPICommands IS
    signal MAX2871_DEF_3 : std_logic_vector(31 downto 0);
    signal MAX2871_DEF_1 : std_logic_vector(31 downto 0);
    signal MAX2871_DEF_0 : std_logic_vector(31 downto 0);
-   signal SWEEP_DATA : std_logic_vector(111 downto 0);
+   signal SWEEP_DATA : std_logic_vector(95 downto 0);
    signal SWEEP_ADDRESS : std_logic_vector(12 downto 0);
    signal SWEEP_WRITE : std_logic_vector(0 downto 0);
    signal SWEEP_POINTS : std_logic_vector(12 downto 0);
-   signal NSAMPLES : std_logic_vector(16 downto 0);
-   signal SETTLING_TIME : std_logic_vector(15 downto 0);
+   signal NSAMPLES : std_logic_vector(12 downto 0);
    signal PORT1_EN : std_logic;
    signal PORT2_EN : std_logic;
    signal REF_EN : std_logic;
@@ -133,7 +131,6 @@ BEGIN
           SWEEP_WRITE => SWEEP_WRITE,
           SWEEP_POINTS => SWEEP_POINTS,
           NSAMPLES => NSAMPLES,
-          SETTLING_TIME => SETTLING_TIME,
           PORT1_EN => PORT1_EN,
           PORT2_EN => PORT2_EN,
           REF_EN => REF_EN,
diff --git a/FPGA/VNA/Test_Sampling.vhd b/FPGA/VNA/Test_Sampling.vhd
index a964baa..b56f330 100644
--- a/FPGA/VNA/Test_Sampling.vhd
+++ b/FPGA/VNA/Test_Sampling.vhd
@@ -46,13 +46,12 @@ ARCHITECTURE behavior OF Test_Sampling IS
 		RESET : IN std_logic;
 		ADC_PRESCALER : IN std_logic_vector(7 downto 0);
 		PHASEINC : IN std_logic_vector(11 downto 0);
-		PORT1 : IN std_logic_vector(15 downto 0);
-		PORT2 : IN std_logic_vector(15 downto 0);
-		REF : IN std_logic_vector(15 downto 0);
+		PORT1 : IN std_logic_vector(17 downto 0);
+		PORT2 : IN std_logic_vector(17 downto 0);
+		REF : IN std_logic_vector(17 downto 0);
 		NEW_SAMPLE : IN std_logic;
 		START : IN std_logic;
-		SAMPLES : IN std_logic_vector(12 downto 0);
-		WINDOW_TYPE : IN std_logic_vector(1 downto 0);          
+		SAMPLES : IN std_logic_vector(12 downto 0);      
 		ADC_START : OUT std_logic;
 		DONE : OUT std_logic;
 		PRE_DONE : OUT std_logic;
@@ -70,9 +69,9 @@ ARCHITECTURE behavior OF Test_Sampling IS
    --Inputs
    signal CLK : std_logic := '0';
    signal RESET : std_logic := '0';
-   signal PORT1 : std_logic_vector(15 downto 0) := (others => '0');
-   signal PORT2 : std_logic_vector(15 downto 0) := (others => '0');
-   signal REF : std_logic_vector(15 downto 0) := (others => '0');
+   signal PORT1 : std_logic_vector(17 downto 0) := (others => '0');
+   signal PORT2 : std_logic_vector(17 downto 0) := (others => '0');
+   signal REF : std_logic_vector(17 downto 0) := (others => '0');
    signal NEW_SAMPLE : std_logic := '0';
    signal START : std_logic := '0';
    signal SAMPLES : std_logic_vector(12 downto 0) := (others => '0');
@@ -107,8 +106,7 @@ BEGIN
 			REF => REF,
 			NEW_SAMPLE => NEW_SAMPLE,
 			START => START,
-			SAMPLES => SAMPLES,
-			WINDOW_TYPE => "00",        
+			SAMPLES => SAMPLES,     
 			ADC_START => ADC_START,
 			DONE => DONE,
 			PRE_DONE => PRE_DONE,
@@ -117,7 +115,7 @@ BEGIN
 			PORT2_I => PORT2_I,
 			PORT2_Q => PORT2_Q,
 			REF_I => REF_I,
-			REF_Q => REF_I,
+			REF_Q => REF_Q,
 			ACTIVE => open
         );
 
@@ -141,11 +139,11 @@ BEGIN
       wait for CLK_period*10;
 
       -- insert stimulus here
-		ADC_PRESCALER <= "01110000";
+		ADC_PRESCALER <= "011110000";
 		PHASEINC <= "010001100000";
-		PORT1 <= "0111111111111111";
-		PORT2 <= "0111111111111111";
-		REF <= "0111111111111111";
+		PORT1 <= "000001111111111111";
+		PORT2 <= "000011111111111111";
+		REF <= "000111111111111111";
 		SAMPLES <= "0000000000001";
 		START <= '1';
 		while True loop
diff --git a/FPGA/VNA/Test_Sync.vhd b/FPGA/VNA/Test_Sync.vhd
deleted file mode 100644
index 2e75fef..0000000
--- a/FPGA/VNA/Test_Sync.vhd
+++ /dev/null
@@ -1,117 +0,0 @@
---------------------------------------------------------------------------------
--- Company: 
--- Engineer:
---
--- Create Date:   14:55:06 05/10/2020
--- Design Name:   
--- Module Name:   /home/jan/Projekte/VNA/FPGA/VNA/Test_Sync.vhd
--- Project Name:  VNA
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: SwitchingSync
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
---------------------------------------------------------------------------------
-LIBRARY ieee;
-USE ieee.std_logic_1164.ALL;
- 
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
-ENTITY Test_Sync IS
-END Test_Sync;
- 
-ARCHITECTURE behavior OF Test_Sync IS 
- 
-    -- Component Declaration for the Unit Under Test (UUT)
- 
-    COMPONENT SwitchingSync
-	 Generic (CLK_DIV : integer);
-    PORT(
-         CLK : IN  std_logic;
-         RESET : IN  std_logic;
-         SETTING : IN  std_logic_vector(1 downto 0);
-         SYNC_OUT : OUT  std_logic;
-         SYNC_PULSE_IN : IN  std_logic
-        );
-    END COMPONENT;
-    
-
-   --Inputs
-   signal CLK : std_logic := '0';
-   signal RESET : std_logic := '0';
-   signal SETTING : std_logic_vector(1 downto 0) := (others => '0');
-   signal SYNC_PULSE_IN : std_logic := '0';
-
- 	--Outputs
-   signal SYNC_OUT : std_logic;
-
-   -- Clock period definitions
-   constant CLK_period : time := 6.25 ns;
-	constant SYNC_PULSE_period : time := 1031.25 ns;
- 
-BEGIN
- 
-	-- Instantiate the Unit Under Test (UUT)
-   uut: SwitchingSync
-	GENERIC MAP (CLK_DIV => 160)
-	PORT MAP (
-          CLK => CLK,
-          RESET => RESET,
-          SETTING => SETTING,
-          SYNC_OUT => SYNC_OUT,
-          SYNC_PULSE_IN => SYNC_PULSE_IN
-        );
-
-   -- Clock process definitions
-   CLK_process :process
-   begin
-		CLK <= '0';
-		wait for CLK_period/2;
-		CLK <= '1';
-		wait for CLK_period/2;
-   end process;
-	
-	SYNC_process :process
-   begin
-		SYNC_PULSE_IN <= '1';
-		wait for CLK_period;
-		SYNC_PULSE_IN <= '0';
-		wait for SYNC_PULSE_period - CLK_period;
-   end process;
- 
-
-   -- Stimulus process
-   stim_proc: process
-   begin		
-      -- hold reset state for 100 ns.
-		RESET <= '1';
-      wait for 100 ns;	
-		RESET <= '0';
-      wait for CLK_period*10;
-
-      -- insert stimulus here 
-		SETTING <= "00";
-		wait for CLK_period*1600;
-		SETTING <= "01";
-		wait for CLK_period*1600;
-		SETTING <= "10";
-		wait for CLK_period*1600;
-      wait;
-   end process;
-
-END;
diff --git a/FPGA/VNA/Test_Window.vhd b/FPGA/VNA/Test_Window.vhd
index 5da84dc..fc53c7f 100644
--- a/FPGA/VNA/Test_Window.vhd
+++ b/FPGA/VNA/Test_Window.vhd
@@ -43,7 +43,7 @@ ARCHITECTURE behavior OF Test_Window IS
     PORT(
          CLK : IN  std_logic;
          INDEX : IN  std_logic_vector(6 downto 0);
-         WINDOW : IN  std_logic_vector(1 downto 0);
+         WINDOW_TYPE : IN  std_logic_vector(1 downto 0);
          VALUE : OUT  std_logic_vector(15 downto 0)
         );
     END COMPONENT;
@@ -52,7 +52,7 @@ ARCHITECTURE behavior OF Test_Window IS
    --Inputs
    signal CLK : std_logic := '0';
    signal INDEX : std_logic_vector(6 downto 0) := (others => '0');
-   signal WINDOW2 : std_logic_vector(1 downto 0) := (others => '0');
+   signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0');
 
  	--Outputs
    signal VALUE : std_logic_vector(15 downto 0);
@@ -66,7 +66,7 @@ BEGIN
    uut: window PORT MAP (
           CLK => CLK,
           INDEX => INDEX,
-          WINDOW => WINDOW2,
+          WINDOW_TYPE => WINDOW_TYPE,
           VALUE => VALUE
         );
 
@@ -85,11 +85,11 @@ BEGIN
    begin		
       -- hold reset state for 100 ns.
       wait for 100 ns;	
-		WINDOW2 <= "00";
+		WINDOW_TYPE <= "00";
 		INDEX <= "0000000";
 		wait for CLK_period*10;
 
-		WINDOW2 <= "10";
+		WINDOW_TYPE <= "10";
       -- insert stimulus here 
 		wait for CLK_period*10;
 		INDEX <= "0000001";
diff --git a/FPGA/VNA/Test_Windowing.vhd b/FPGA/VNA/Test_Windowing.vhd
index 58517e4..398db59 100644
--- a/FPGA/VNA/Test_Windowing.vhd
+++ b/FPGA/VNA/Test_Windowing.vhd
@@ -48,9 +48,9 @@ ARCHITECTURE behavior OF Test_Windowing IS
          PORT2_RAW : IN  std_logic_vector(15 downto 0);
          REF_RAW : IN  std_logic_vector(15 downto 0);
          ADC_READY : IN  std_logic;
-         PORT1_WINDOWED : OUT  std_logic_vector(15 downto 0);
-         PORT2_WINDOWED : OUT  std_logic_vector(15 downto 0);
-         REF_WINDOWED : OUT  std_logic_vector(15 downto 0);
+         PORT1_WINDOWED : OUT  std_logic_vector(17 downto 0);
+         PORT2_WINDOWED : OUT  std_logic_vector(17 downto 0);
+         REF_WINDOWED : OUT  std_logic_vector(17 downto 0);
          WINDOWING_DONE : OUT  std_logic;
          NSAMPLES : IN  std_logic_vector(12 downto 0)
         );
@@ -68,9 +68,9 @@ ARCHITECTURE behavior OF Test_Windowing IS
    signal NSAMPLES : std_logic_vector(12 downto 0) := (others => '0');
 
  	--Outputs
-   signal PORT1_WINDOWED : std_logic_vector(15 downto 0);
-   signal PORT2_WINDOWED : std_logic_vector(15 downto 0);
-   signal REF_WINDOWED : std_logic_vector(15 downto 0);
+   signal PORT1_WINDOWED : std_logic_vector(17 downto 0);
+   signal PORT2_WINDOWED : std_logic_vector(17 downto 0);
+   signal REF_WINDOWED : std_logic_vector(17 downto 0);
    signal WINDOWING_DONE : std_logic;
 
    -- Clock period definitions
diff --git a/FPGA/VNA/VNA.gise b/FPGA/VNA/VNA.gise
index 955d340..f25e55f 100644
--- a/FPGA/VNA/VNA.gise
+++ b/FPGA/VNA/VNA.gise
@@ -47,11 +47,11 @@
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Sync_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Sync_isim_beh.wdb"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Window_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Windowing_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Windowing_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Windowing_isim_beh.wdb"/>
     <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Windowing_stx_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_top_isim_beh.exe"/>
     <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Windowing.vhi"/>
@@ -71,6 +71,7 @@
     <file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
@@ -121,6 +122,9 @@
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
     <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
     <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="window.vhi"/>
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="window_beh.prj"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="window_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="window_isim_beh.wdb"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
@@ -131,7 +135,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604688338" xil_pn:in_ck="7920041737510621142" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1604688338">
+    <transform xil_pn:end_ts="1604764195" xil_pn:in_ck="-3235419683908193302" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1604764195">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -154,7 +158,6 @@
       <outfile xil_pn:name="Test_SPICommands.vhd"/>
       <outfile xil_pn:name="Test_Sampling.vhd"/>
       <outfile xil_pn:name="Test_SinCos.vhd"/>
-      <outfile xil_pn:name="Test_Sync.vhd"/>
       <outfile xil_pn:name="Test_Window.vhd"/>
       <outfile xil_pn:name="Test_Windowing.vhd"/>
       <outfile xil_pn:name="Windowing.vhd"/>
@@ -162,89 +165,56 @@
       <outfile xil_pn:name="top.vhd"/>
       <outfile xil_pn:name="window.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1604684486" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="1671761620692912459" xil_pn:start_ts="1604684486">
+    <transform xil_pn:end_ts="1604764128" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="3044368668303368987" xil_pn:start_ts="1604764128">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604684486" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="6847665263640105929" xil_pn:start_ts="1604684486">
+    <transform xil_pn:end_ts="1604764128" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-7898843873652552295" xil_pn:start_ts="1604764128">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604671666" xil_pn:in_ck="6306144844996157057" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604671665">
+    <transform xil_pn:end_ts="1604763670" xil_pn:in_ck="6306144844996157057" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604763670">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
-      <outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
-      <outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/SinCosMult.ngc"/>
-      <outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
-      <outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
-      <outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+      <status xil_pn:value="OutputRemoved"/>
     </transform>
-    <transform xil_pn:end_ts="1604684548" xil_pn:in_ck="2301248572745587975" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1604684548">
+    <transform xil_pn:end_ts="1604764195" xil_pn:in_ck="-9185925483828391381" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1604764195">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="InputChanged"/>
-      <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="DFT.vhd"/>
-      <outfile xil_pn:name="MAX2871.vhd"/>
-      <outfile xil_pn:name="MCP33131.vhd"/>
-      <outfile xil_pn:name="ResetDelay.vhd"/>
-      <outfile xil_pn:name="SPIConfig.vhd"/>
-      <outfile xil_pn:name="Sampling.vhd"/>
-      <outfile xil_pn:name="Sweep.vhd"/>
-      <outfile xil_pn:name="Synchronizer.vhd"/>
-      <outfile xil_pn:name="Test_DFT.vhd"/>
-      <outfile xil_pn:name="Test_MAX2871.vhd"/>
-      <outfile xil_pn:name="Test_MCP33131.vhd"/>
-      <outfile xil_pn:name="Test_PLL.vhd"/>
-      <outfile xil_pn:name="Test_SPI.vhd"/>
-      <outfile xil_pn:name="Test_SPICommands.vhd"/>
-      <outfile xil_pn:name="Test_Sampling.vhd"/>
-      <outfile xil_pn:name="Test_SinCos.vhd"/>
-      <outfile xil_pn:name="Test_Sync.vhd"/>
-      <outfile xil_pn:name="Test_Window.vhd"/>
-      <outfile xil_pn:name="Test_Windowing.vhd"/>
-      <outfile xil_pn:name="Windowing.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
-      <outfile xil_pn:name="spi_slave.vhd"/>
-      <outfile xil_pn:name="top.vhd"/>
-      <outfile xil_pn:name="window.vhd"/>
+      <status xil_pn:value="InputRemoved"/>
+      <status xil_pn:value="OutputRemoved"/>
     </transform>
-    <transform xil_pn:end_ts="1604684552" xil_pn:in_ck="2301248572745587975" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="7968903525862259638" xil_pn:start_ts="1604684548">
+    <transform xil_pn:end_ts="1604764196" xil_pn:in_ck="4954137158046299803" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="3520630626282717961" xil_pn:start_ts="1604764195">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForProperties"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputAdded"/>
       <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_Windowing_beh.prj"/>
-      <outfile xil_pn:name="Test_Windowing_isim_beh.exe"/>
-      <outfile xil_pn:name="fuse.log"/>
-      <outfile xil_pn:name="isim"/>
-      <outfile xil_pn:name="xilinxsim.ini"/>
+      <status xil_pn:value="OutputRemoved"/>
     </transform>
-    <transform xil_pn:end_ts="1604684553" xil_pn:in_ck="-2626831050236864990" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-4828419273139430045" xil_pn:start_ts="1604684552">
+    <transform xil_pn:end_ts="1604764196" xil_pn:in_ck="-6978407093755538946" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8357625476205656394" xil_pn:start_ts="1604764196">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="OutOfDateForProperties"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="InputRemoved"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_Windowing_isim_beh.wdb"/>
-      <outfile xil_pn:name="isim.cmd"/>
+      <status xil_pn:value="OutputRemoved"/>
     </transform>
     <transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600270761">
       <status xil_pn:value="SuccessfullyRun"/>
@@ -254,7 +224,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604675434" xil_pn:in_ck="6306144844996157057" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604675434">
+    <transform xil_pn:end_ts="1604764706" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604764706">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@@ -262,8 +232,6 @@
       <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
       <outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
-      <outfile xil_pn:name="ipcore_dir/SinCosMult.ngc"/>
-      <outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
       <outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
       <outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
@@ -285,7 +253,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604704764" xil_pn:in_ck="-480514955089580632" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1604704739">
+    <transform xil_pn:end_ts="1604764767" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1604764742">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -307,7 +275,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604704771" xil_pn:in_ck="-614491687805493712" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1604704764">
+    <transform xil_pn:end_ts="1604764774" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1604764767">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_ngo"/>
@@ -316,10 +284,12 @@
       <outfile xil_pn:name="top.ngd"/>
       <outfile xil_pn:name="top_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1604704833" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1604704771">
+    <transform xil_pn:end_ts="1604764932" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1604764774">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
       <outfile xil_pn:name="top.pcf"/>
       <outfile xil_pn:name="top_map.map"/>
@@ -330,7 +300,7 @@
       <outfile xil_pn:name="top_summary.xml"/>
       <outfile xil_pn:name="top_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1604704864" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1604704833">
+    <transform xil_pn:end_ts="1604764964" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1604764932">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@@ -344,7 +314,7 @@
       <outfile xil_pn:name="top_pad.txt"/>
       <outfile xil_pn:name="top_par.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1604704879" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1604704864">
+    <transform xil_pn:end_ts="1604764980" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1604764964">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -398,7 +368,7 @@
       <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="InputRemoved"/>
     </transform>
-    <transform xil_pn:end_ts="1604704864" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1604704856">
+    <transform xil_pn:end_ts="1604764964" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1604764957">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
diff --git a/FPGA/VNA/VNA.xise b/FPGA/VNA/VNA.xise
index 1327387..7f1807b 100644
--- a/FPGA/VNA/VNA.xise
+++ b/FPGA/VNA/VNA.xise
@@ -17,14 +17,14 @@
   <files>
     <file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -34,21 +34,17 @@
     </file>
     <file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="ipcore_dir/SweepConfigMem.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
-    </file>
-    <file xil_pn:name="ipcore_dir/SinCosMult.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
@@ -64,15 +60,15 @@
     </file>
     <file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -92,19 +88,15 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="124"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="124"/>
     </file>
-    <file xil_pn:name="Test_Sync.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="124"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="124"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="124"/>
-    </file>
     <file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="20"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="Test_SPI.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -114,7 +106,7 @@
     </file>
     <file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="window.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
@@ -128,7 +120,7 @@
     </file>
     <file xil_pn:name="DFT.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="Test_DFT.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -138,18 +130,18 @@
     </file>
     <file xil_pn:name="ipcore_dir/result_bram.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="ipcore_dir/DSP_SLICE.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="Windowing.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="Test_Windowing.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="176"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="176"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="176"/>
@@ -160,9 +152,6 @@
     <file xil_pn:name="ipcore_dir/SinCos.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="ipcore_dir/SinCosMult.xise" xil_pn:type="FILE_COREGENISE">
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
@@ -358,7 +347,7 @@
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -416,8 +405,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_Windowing" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_Windowing" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_DFT" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -435,7 +424,7 @@
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_Windowing" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -487,7 +476,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_Windowing|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|window|Behavioral" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
diff --git a/FPGA/VNA/Windowing.vhd b/FPGA/VNA/Windowing.vhd
index 8271d3f..3750645 100644
--- a/FPGA/VNA/Windowing.vhd
+++ b/FPGA/VNA/Windowing.vhd
@@ -37,9 +37,9 @@ entity Windowing is
            PORT2_RAW : in  STD_LOGIC_VECTOR (15 downto 0);
            REF_RAW : in  STD_LOGIC_VECTOR (15 downto 0);
            ADC_READY : in  STD_LOGIC;
-           PORT1_WINDOWED : out  STD_LOGIC_VECTOR (15 downto 0);
-           PORT2_WINDOWED : out  STD_LOGIC_VECTOR (15 downto 0);
-           REF_WINDOWED : out  STD_LOGIC_VECTOR (15 downto 0);
+           PORT1_WINDOWED : out  STD_LOGIC_VECTOR (17 downto 0);
+           PORT2_WINDOWED : out  STD_LOGIC_VECTOR (17 downto 0);
+           REF_WINDOWED : out  STD_LOGIC_VECTOR (17 downto 0);
            WINDOWING_DONE : out  STD_LOGIC;
            NSAMPLES : in  STD_LOGIC_VECTOR (12 downto 0));
 end Windowing;
@@ -171,19 +171,19 @@ begin
 					WINDOWING_DONE <= '0';
 					mult_enable <= '1';
 					mult_b(15 downto 0) <= (others => '0');
-					PORT1_WINDOWED <= mult_p(30 downto 15); 
+					PORT1_WINDOWED <= mult_p(30 downto 13); 
 					state <= StorePort2;
 				when StorePort2 =>
 					WINDOWING_DONE <= '0';
 					mult_enable <= '1';
 					mult_b(15 downto 0) <= (others => '0');
-					PORT2_WINDOWED <= mult_p(30 downto 15);
+					PORT2_WINDOWED <= mult_p(30 downto 13);
 					state <= StoreRef;
 				when StoreRef =>
 					WINDOWING_DONE <= '1';
 					mult_enable <= '0';
 					mult_b(15 downto 0) <= (others => '0');
-					REF_WINDOWED <= mult_p(30 downto 15);
+					REF_WINDOWED <= mult_p(30 downto 13);
 					-- update window increment
 					if window_sample_cnt + window_sample_cnt_inc < window_sample_compare then
 						window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc;
diff --git a/FPGA/VNA/ipcore_dir/SinCosMult.xco b/FPGA/VNA/ipcore_dir/SinCosMult.xco
deleted file mode 100644
index bae637f..0000000
--- a/FPGA/VNA/ipcore_dir/SinCosMult.xco
+++ /dev/null
@@ -1,68 +0,0 @@
-##############################################################
-#
-# Xilinx Core Generator version 14.6
-# Date: Tue May  5 15:41:30 2020
-#
-##############################################################
-#
-#  This file contains the customisation parameters for a
-#  Xilinx CORE Generator IP GUI. It is strongly recommended
-#  that you do not manually alter this file as it may cause
-#  unexpected and unsupported behavior.
-#
-##############################################################
-#
-#  Generated from component: xilinx.com:ip:mult_gen:11.2
-#
-##############################################################
-#
-# BEGIN Project Options
-SET addpads = false
-SET asysymbol = true
-SET busformat = BusFormatAngleBracketNotRipped
-SET createndf = false
-SET designentry = VHDL
-SET device = xc6slx9
-SET devicefamily = spartan6
-SET flowvendor = Other
-SET formalverification = false
-SET foundationsym = false
-SET implementationfiletype = Ngc
-SET package = tqg144
-SET removerpms = false
-SET simulationfiles = Behavioral
-SET speedgrade = -2
-SET verilogsim = false
-SET vhdlsim = true
-# END Project Options
-# BEGIN Select
-SELECT Multiplier xilinx.com:ip:mult_gen:11.2
-# END Select
-# BEGIN Parameters
-CSET ccmimp=Distributed_Memory
-CSET clockenable=false
-CSET component_name=SinCosMult
-CSET constvalue=129
-CSET internaluser=0
-CSET multiplier_construction=Use_Mults
-CSET multtype=Parallel_Multiplier
-CSET optgoal=Speed
-CSET outputwidthhigh=31
-CSET outputwidthlow=0
-CSET pipestages=2
-CSET portatype=Signed
-CSET portawidth=16
-CSET portbtype=Signed
-CSET portbwidth=16
-CSET roundpoint=0
-CSET sclrcepriority=SCLR_Overrides_CE
-CSET syncclear=false
-CSET use_custom_output_width=false
-CSET userounding=false
-CSET zerodetect=false
-# END Parameters
-# BEGIN Extra information
-MISC pkg_timestamp=2012-11-05T14:23:07Z
-# END Extra information
-GENERATE
-# CRC: 7fa795cb
diff --git a/FPGA/VNA/ipcore_dir/SinCosMult.xise b/FPGA/VNA/ipcore_dir/SinCosMult.xise
deleted file mode 100644
index a9f8a31..0000000
--- a/FPGA/VNA/ipcore_dir/SinCosMult.xise
+++ /dev/null
@@ -1,73 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
-
-  <header>
-    <!-- ISE source project file created by Project Navigator.             -->
-    <!--                                                                   -->
-    <!-- This file contains project source information including a list of -->
-    <!-- project source files, project and process properties.  This file, -->
-    <!-- along with the project source files, is sufficient to open and    -->
-    <!-- implement in ISE Project Navigator.                               -->
-    <!--                                                                   -->
-    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-  </header>
-
-  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
-
-  <files>
-    <file xil_pn:name="SinCosMult.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
-    <file xil_pn:name="SinCosMult.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
-    </file>
-  </files>
-
-  <properties>
-    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|SinCosMult|SinCosMult_a" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="SinCosMult.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/SinCosMult" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
-    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
-    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-    <!--                                                                                  -->
-    <!-- The following properties are for internal use only. These should not be modified.-->
-    <!--                                                                                  -->
-    <property xil_pn:name="PROP_DesignName" xil_pn:value="SinCosMult" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-05-05T17:41:58" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="BF44F186592C9F85C9D39935A7CA77A0" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-  </properties>
-
-  <bindings/>
-
-  <libraries/>
-
-  <autoManagedFiles>
-    <!-- The following files are identified by `include statements in verilog -->
-    <!-- source files and are automatically managed by Project Navigator.     -->
-    <!--                                                                      -->
-    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-    <!-- project is analyzed based on files automatically identified as       -->
-    <!-- include files.                                                       -->
-  </autoManagedFiles>
-
-</project>
diff --git a/FPGA/VNA/ipcore_dir/result_bram.xco b/FPGA/VNA/ipcore_dir/result_bram.xco
index 3baf072..5a73570 100644
--- a/FPGA/VNA/ipcore_dir/result_bram.xco
+++ b/FPGA/VNA/ipcore_dir/result_bram.xco
@@ -1,7 +1,7 @@
 ##############################################################
 #
 # Xilinx Core Generator version 14.6
-# Date: Tue Nov  3 21:55:11 2020
+# Date: Sat Nov  7 15:56:38 2020
 #
 ##############################################################
 #
@@ -97,7 +97,7 @@ CSET use_regcea_pin=false
 CSET use_regceb_pin=false
 CSET use_rsta_pin=false
 CSET use_rstb_pin=false
-CSET write_depth_a=64
+CSET write_depth_a=256
 CSET write_width_a=192
 CSET write_width_b=192
 # END Parameters
@@ -105,4 +105,4 @@ CSET write_width_b=192
 MISC pkg_timestamp=2012-11-19T16:22:25Z
 # END Extra information
 GENERATE
-# CRC: 64af2239
+# CRC: 14273b86
diff --git a/FPGA/VNA/ipcore_dir/result_bram.xise b/FPGA/VNA/ipcore_dir/result_bram.xise
index cb2b34c..0abc844 100644
--- a/FPGA/VNA/ipcore_dir/result_bram.xise
+++ b/FPGA/VNA/ipcore_dir/result_bram.xise
@@ -17,11 +17,11 @@
   <files>
     <file xil_pn:name="result_bram.ngc" xil_pn:type="FILE_NGC">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="result_bram.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
@@ -29,30 +29,359 @@
   </files>
 
   <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="Structural" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|result_bram|result_bram_a" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top File" xil_pn:value="result_bram.vhd" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/result_bram" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="result_bram" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="result_bram_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="result_bram_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="result_bram_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="result_bram_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="result_bram" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-11-03T22:56:00" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="954C7EB37A9CAA0D6F0F8CE18AB6F28F" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-11-07T16:57:27" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="B5404264344E1435540FD7484D40A487" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
diff --git a/FPGA/VNA/top.bin b/FPGA/VNA/top.bin
index 6ad41ec..1a6d8e3 100644
Binary files a/FPGA/VNA/top.bin and b/FPGA/VNA/top.bin differ
diff --git a/FPGA/VNA/top.vhd b/FPGA/VNA/top.vhd
index 41b0f72..391a933 100644
--- a/FPGA/VNA/top.vhd
+++ b/FPGA/VNA/top.vhd
@@ -156,9 +156,9 @@ architecture Behavioral of top is
 		REF_RAW : IN std_logic_vector(15 downto 0);
 		ADC_READY : IN std_logic;
 		NSAMPLES : IN std_logic_vector(12 downto 0);          
-		PORT1_WINDOWED : OUT std_logic_vector(15 downto 0);
-		PORT2_WINDOWED : OUT std_logic_vector(15 downto 0);
-		REF_WINDOWED : OUT std_logic_vector(15 downto 0);
+		PORT1_WINDOWED : OUT std_logic_vector(17 downto 0);
+		PORT2_WINDOWED : OUT std_logic_vector(17 downto 0);
+		REF_WINDOWED : OUT std_logic_vector(17 downto 0);
 		WINDOWING_DONE : OUT std_logic
 		);
 	END COMPONENT;
@@ -170,9 +170,9 @@ architecture Behavioral of top is
 		RESET : IN std_logic;
 		ADC_PRESCALER : in STD_LOGIC_VECTOR(7 downto 0);
 		PHASEINC : in STD_LOGIC_VECTOR(11 downto 0);
-		PORT1 : IN std_logic_vector(15 downto 0);
-		PORT2 : IN std_logic_vector(15 downto 0);
-		REF : IN std_logic_vector(15 downto 0);
+		PORT1 : IN std_logic_vector(17 downto 0);
+		PORT2 : IN std_logic_vector(17 downto 0);
+		REF : IN std_logic_vector(17 downto 0);
 		NEW_SAMPLE : IN std_logic;
 		START : IN std_logic;
 		SAMPLES : IN std_logic_vector(12 downto 0);
@@ -277,8 +277,8 @@ architecture Behavioral of top is
 	PORT(
 		CLK : IN std_logic;
 		RESET : IN std_logic;
-		PORT1 : IN std_logic_vector(15 downto 0);
-		PORT2 : IN std_logic_vector(15 downto 0);
+		PORT1 : IN std_logic_vector(17 downto 0);
+		PORT2 : IN std_logic_vector(17 downto 0);
 		NEW_SAMPLE : IN std_logic;
 		NSAMPLES : IN std_logic_vector(12 downto 0);
 		BIN1_PHASEINC : IN std_logic_vector(15 downto 0);
@@ -342,9 +342,9 @@ architecture Behavioral of top is
 	signal adc_minmax : std_logic_vector(95 downto 0);
 	signal adc_reset_minmax : std_logic;
 	
-	signal port1_windowed : std_logic_vector(15 downto 0);
-	signal port2_windowed : std_logic_vector(15 downto 0);
-	signal ref_windowed : std_logic_vector(15 downto 0);
+	signal port1_windowed : std_logic_vector(17 downto 0);
+	signal port2_windowed : std_logic_vector(17 downto 0);
+	signal ref_windowed : std_logic_vector(17 downto 0);
 	signal windowing_ready : std_logic;
 	
 	-- Sampling signals
@@ -753,7 +753,7 @@ begin
 	
 	dft_reset <= not dft_enable;
 	
-	SA_DFT: DFT GENERIC MAP(BINS => 64)
+	SA_DFT: DFT GENERIC MAP(BINS => 96)
 	PORT MAP(
 		CLK => clk160,
 		RESET => dft_reset,
diff --git a/Software/PC_Application/Device/device.cpp b/Software/PC_Application/Device/device.cpp
index 88c598d..439cfe7 100644
--- a/Software/PC_Application/Device/device.cpp
+++ b/Software/PC_Application/Device/device.cpp
@@ -129,12 +129,12 @@ static constexpr Protocol::DeviceInfo defaultInfo = {
     .limits_minFreq = 0,
     .limits_maxFreq = 6000000000,
     .limits_minIFBW = 10,
-    .limits_maxIFBW = 50000,
-    .limits_maxPoints = 4501,
-    .limits_cdbm_min = -4000,
-    .limits_cdbm_max = 0,
-    .limits_minRBW = 15,
-    .limits_maxRBW = 100000,
+    .limits_maxIFBW = 1000000,
+    .limits_maxPoints = 10000,
+    .limits_cdbm_min = -10000,
+    .limits_cdbm_max = 1000,
+    .limits_minRBW = 1,
+    .limits_maxRBW = 1000000,
 };
 
 Protocol::DeviceInfo Device::lastInfo = defaultInfo;
diff --git a/Software/PC_Application/SpectrumAnalyzer/spectrumanalyzer.cpp b/Software/PC_Application/SpectrumAnalyzer/spectrumanalyzer.cpp
index 252cffc..a1c612e 100644
--- a/Software/PC_Application/SpectrumAnalyzer/spectrumanalyzer.cpp
+++ b/Software/PC_Application/SpectrumAnalyzer/spectrumanalyzer.cpp
@@ -232,8 +232,8 @@ using namespace std;
 void SpectrumAnalyzer::NewDatapoint(Protocol::SpectrumAnalyzerResult d)
 {
     // TODO level adjustment in device
-    d.port1 /= pow(10.0, 7.5);
-    d.port2 /= pow(10.0, 7.5);
+    d.port1 /= 126500000.0;
+    d.port2 /= 126500000.0;
     d = average.process(d);
     traceModel.addSAData(d);
     emit dataChanged();
diff --git a/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp b/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
index cae5e3e..b6624ad 100644
--- a/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
+++ b/Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
@@ -6,7 +6,7 @@
 namespace FPGA {
 
 static constexpr uint16_t MaxPoints = 4501;
-static constexpr uint16_t DFTbins = 64;
+static constexpr uint16_t DFTbins = 96;
 static constexpr uint32_t Clockrate = 102400000UL;
 
 enum class Reg {