refactor evaluation of standby waiting state
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5bb6fdf686
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916d6e3e38
@ -250,6 +250,8 @@ void HW::SetIdle() {
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FPGA::Enable(FPGA::Periphery::RefMixer, false);
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FPGA::Enable(FPGA::Periphery::PortSwitch, false);
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activeMode = Mode::Idle;
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VNA::SetWaitingInStandby(false);
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}
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HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool applyCorrections, bool port2) {
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@ -303,7 +305,7 @@ bool HW::TimedOut() {
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auto bufISR = lastISR;
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uint64_t now = Delay::get_us();
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uint64_t timeSinceLast = now - bufISR;
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if(activeMode != Mode::Idle && activeMode != Mode::Generator && !VNA::GetStandbyMode() && timeSinceLast > timeout) {
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if(activeMode != Mode::Idle && activeMode != Mode::Generator && !VNA::IsWaitingInStandby() && timeSinceLast > timeout) {
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LOG_WARN("Timed out, last ISR was at %lu%06lu, now %lu%06lu"
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, (uint32_t) (bufISR / 1000000), (uint32_t)(bufISR%1000000)
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, (uint32_t) (now / 1000000), (uint32_t)(now%1000000));
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@ -9,6 +9,8 @@ namespace VNA {
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bool Setup(Protocol::SweepSettings s);
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void InitiateSweep();
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bool GetStandbyMode();
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bool IsWaitingInStandby();
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void SetWaitingInStandby(bool waiting);
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bool MeasurementDone(const FPGA::SamplingResult &result);
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void Work();
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void SweepHalted();
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