refactor evaluation of standby waiting state

This commit is contained in:
Andre Dunford 2022-12-20 11:14:02 -08:00
parent 5bb6fdf686
commit 916d6e3e38
2 changed files with 5 additions and 1 deletions

View File

@ -250,6 +250,8 @@ void HW::SetIdle() {
FPGA::Enable(FPGA::Periphery::RefMixer, false); FPGA::Enable(FPGA::Periphery::RefMixer, false);
FPGA::Enable(FPGA::Periphery::PortSwitch, false); FPGA::Enable(FPGA::Periphery::PortSwitch, false);
activeMode = Mode::Idle; activeMode = Mode::Idle;
VNA::SetWaitingInStandby(false);
} }
HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool applyCorrections, bool port2) { HW::AmplitudeSettings HW::GetAmplitudeSettings(int16_t cdbm, uint64_t freq, bool applyCorrections, bool port2) {
@ -303,7 +305,7 @@ bool HW::TimedOut() {
auto bufISR = lastISR; auto bufISR = lastISR;
uint64_t now = Delay::get_us(); uint64_t now = Delay::get_us();
uint64_t timeSinceLast = now - bufISR; uint64_t timeSinceLast = now - bufISR;
if(activeMode != Mode::Idle && activeMode != Mode::Generator && !VNA::GetStandbyMode() && timeSinceLast > timeout) { if(activeMode != Mode::Idle && activeMode != Mode::Generator && !VNA::IsWaitingInStandby() && timeSinceLast > timeout) {
LOG_WARN("Timed out, last ISR was at %lu%06lu, now %lu%06lu" LOG_WARN("Timed out, last ISR was at %lu%06lu, now %lu%06lu"
, (uint32_t) (bufISR / 1000000), (uint32_t)(bufISR%1000000) , (uint32_t) (bufISR / 1000000), (uint32_t)(bufISR%1000000)
, (uint32_t) (now / 1000000), (uint32_t)(now%1000000)); , (uint32_t) (now / 1000000), (uint32_t)(now%1000000));

View File

@ -9,6 +9,8 @@ namespace VNA {
bool Setup(Protocol::SweepSettings s); bool Setup(Protocol::SweepSettings s);
void InitiateSweep(); void InitiateSweep();
bool GetStandbyMode(); bool GetStandbyMode();
bool IsWaitingInStandby();
void SetWaitingInStandby(bool waiting);
bool MeasurementDone(const FPGA::SamplingResult &result); bool MeasurementDone(const FPGA::SamplingResult &result);
void Work(); void Work();
void SweepHalted(); void SweepHalted();