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Bugfixes and speed improvements

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This commit is contained in:
Jan Käberich 2020-09-26 23:34:31 +02:00
parent 199535450d
commit 926392e5b9
37 changed files with 873 additions and 566 deletions
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BIN
Documentation/DeveloperInfo/FPGA_protocol.pdf
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14
Documentation/DeveloperInfo/FPGA_protocol.tex
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@ -248,11 +248,11 @@ The register contains the number of points per sweep negative one, e.g. set to 1
\begin{tikzpicture} \begin{tikzpicture}
\bitrect{16}{16-\bit} \bitrect{16}{16-\bit}
\robits{0}{6}{reserved} \robits{0}{6}{reserved}
\rwbits{6}{10}{SPP[9:0]} \rwbits{3}{13}{SPP[12:0]}
\end{tikzpicture} \end{tikzpicture}
\end{center} \end{center}
\begin{itemize} \begin{itemize}
\item \textbf{SPP[9:0]:} The register contains the number of samples per point in increments of 128 samples (e.g. SPP=0b0000001000=0x08 uses 1024 samples per point). The value of this register is only used if SweepConfig[92:90] is set to 000. Otherwise it is overwritten for the sweep point with one of seven preselected values. \item \textbf{SPP[12:0]:} The register contains the number of samples per point in increments of 16 samples (e.g. SPP=0b0000001000=0x08 uses 128 samples per point). The value of this register is only used if SweepConfig[92:90] is set to 000. Otherwise it is overwritten for the sweep point with one of seven preselected values.
\end{itemize} \end{itemize}
\subsection{System Control Register: 0x03} \subsection{System Control Register: 0x03}
@ -432,11 +432,11 @@ Setting & Time\\
Setting & Samples & Equivalent IF bandwidth\\ Setting & Samples & Equivalent IF bandwidth\\
\hline \hline
000 & Defined by SPP register & \SI{914}{\kilo\hertz}/SPP\\ 000 & Defined by SPP register & \SI{914}{\kilo\hertz}/SPP\\
001 & 128 & \SI{10}{\kilo\hertz}\\ 001 & 96 & \SI{10}{\kilo\hertz}\\
010 & 384 & \SI{3}{\kilo\hertz}\\ 010 & 304 & \SI{3}{\kilo\hertz}\\
011 & 896 & \SI{1}{\kilo\hertz}\\ 011 & 912 & \SI{1}{\kilo\hertz}\\
100 & 3072 & \SI{300}{\hertz}\\ 100 & 3040 & \SI{300}{\hertz}\\
101 & 9088 & \SI{100}{\hertz}\\ 101 & 9136 & \SI{100}{\hertz}\\
110 & 30464 & \SI{30}{\hertz}\\ 110 & 30464 & \SI{30}{\hertz}\\
111 & 91392 & \SI{10}{\hertz}\\ 111 & 91392 & \SI{10}{\hertz}\\
\end{tabular} \end{tabular}

2
FPGA/VNA/DFT.vhd
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@ -86,7 +86,7 @@ END COMPONENT;
signal port2_latch : std_logic_vector(15 downto 0); signal port2_latch : std_logic_vector(15 downto 0);
signal window_index : std_logic_vector(6 downto 0); signal window_index : std_logic_vector(6 downto 0);
signal window_cnt : unsigned(
signal window_value : std_logic_vector(15 downto 0); signal window_value : std_logic_vector(15 downto 0);
signal phase : std_logic_vector(31 downto 0); signal phase : std_logic_vector(31 downto 0);

4
FPGA/VNA/SPIConfig.vhd
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@ -49,7 +49,7 @@ entity SPICommands is
SWEEP_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0); SWEEP_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
SWEEP_WRITE : out STD_LOGIC_VECTOR (0 downto 0); SWEEP_WRITE : out STD_LOGIC_VECTOR (0 downto 0);
SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0); SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0);
NSAMPLES : out STD_LOGIC_VECTOR (9 downto 0); NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
EXCITE_PORT1 : out STD_LOGIC; EXCITE_PORT1 : out STD_LOGIC;
EXCITE_PORT2 : out STD_LOGIC; EXCITE_PORT2 : out STD_LOGIC;
PORT1_EN : out STD_LOGIC; PORT1_EN : out STD_LOGIC;
@ -196,7 +196,7 @@ begin
case selected_register is case selected_register is
when 0 => interrupt_mask <= spi_buf_out; when 0 => interrupt_mask <= spi_buf_out;
when 1 => SWEEP_POINTS <= spi_buf_out(12 downto 0); when 1 => SWEEP_POINTS <= spi_buf_out(12 downto 0);
when 2 => NSAMPLES <= spi_buf_out(9 downto 0); when 2 => NSAMPLES <= spi_buf_out(12 downto 0);
when 3 => PORTSWITCH_EN <= spi_buf_out(0); when 3 => PORTSWITCH_EN <= spi_buf_out(0);
PORT1_EN <= spi_buf_out(15); PORT1_EN <= spi_buf_out(15);
PORT2_EN <= spi_buf_out(14); PORT2_EN <= spi_buf_out(14);

36
FPGA/VNA/Sampling.vhd
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@ -43,7 +43,7 @@ entity Sampling is
DONE : out STD_LOGIC; DONE : out STD_LOGIC;
PRE_DONE : out STD_LOGIC; PRE_DONE : out STD_LOGIC;
START : in STD_LOGIC; START : in STD_LOGIC;
SAMPLES : in STD_LOGIC_VECTOR (9 downto 0); SAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0); WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
PORT1_I : out STD_LOGIC_VECTOR (47 downto 0); PORT1_I : out STD_LOGIC_VECTOR (47 downto 0);
PORT1_Q : out STD_LOGIC_VECTOR (47 downto 0); PORT1_Q : out STD_LOGIC_VECTOR (47 downto 0);
@ -99,7 +99,10 @@ END COMPONENT;
signal window_index : std_logic_vector(6 downto 0); signal window_index : std_logic_vector(6 downto 0);
signal window_value : std_logic_vector(15 downto 0); signal window_value : std_logic_vector(15 downto 0);
signal window_sample_cnt : integer range 0 to 1023; signal window_sample_cnt : integer range 0 to 8191;
signal window_index_inc : integer range 0 to 8;
signal window_sample_compare : integer range 0 to 8191;
signal window_sample_cnt_inc : integer range 0 to 8;
signal mult1_I : std_logic_vector(31 downto 0); signal mult1_I : std_logic_vector(31 downto 0);
signal mult1_Q : std_logic_vector(31 downto 0); signal mult1_Q : std_logic_vector(31 downto 0);
@ -232,7 +235,26 @@ begin
phase <= (others => '0'); phase <= (others => '0');
if START = '1' then if START = '1' then
state <= Sampling; state <= Sampling;
samples_to_take <= to_integer(unsigned(SAMPLES & "0000000") - 1); samples_to_take <= to_integer(unsigned(SAMPLES & "0000") - 1);
window_sample_compare <= to_integer(unsigned(SAMPLES) - 1);
case SAMPLES is
when "0000000000001" =>
-- 16 samples, increment on every sample by 8
window_sample_cnt_inc <= 1;
window_index_inc <= 8;
when "0000000000010" | "0000000000011" =>
-- 32-48 samples, increment by 4
window_sample_cnt_inc <= 2;
window_index_inc <= 4;
when "0000000000100" | "0000000000101" | "0000000000110" | "0000000000111"=>
-- 64-112 samples, increment by 2
window_sample_cnt_inc <= 4;
window_index_inc <= 2;
when others =>
-- 128 or more samples, increment by 1
window_sample_cnt_inc <= 8;
window_index_inc <= 1;
end case;
end if; end if;
when Sampling => when Sampling =>
DONE <= '0'; DONE <= '0';
@ -266,11 +288,11 @@ begin
state <= Ready; state <= Ready;
end if; end if;
-- keep track of window index -- keep track of window index
if window_sample_cnt < unsigned(SAMPLES) - 1 then if window_sample_cnt < window_sample_compare then
window_sample_cnt <= window_sample_cnt + 1; window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc;
else else
window_sample_cnt <= 0; window_sample_cnt <= window_sample_cnt - window_sample_compare;
window_index <= std_logic_vector( unsigned(window_index) + 1 ); window_index <= std_logic_vector( unsigned(window_index) + window_index_inc );
end if; end if;
when Ready => when Ready =>
ACTIVE <= '1'; ACTIVE <= '1';

20
FPGA/VNA/Sweep.vhd
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@ -35,8 +35,8 @@ entity Sweep is
NPOINTS : in STD_LOGIC_VECTOR (12 downto 0); NPOINTS : in STD_LOGIC_VECTOR (12 downto 0);
CONFIG_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0); CONFIG_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
CONFIG_DATA : in STD_LOGIC_VECTOR (95 downto 0); CONFIG_DATA : in STD_LOGIC_VECTOR (95 downto 0);
USER_NSAMPLES : in STD_LOGIC_VECTOR (9 downto 0); USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
NSAMPLES : out STD_LOGIC_VECTOR (9 downto 0); NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
SAMPLING_BUSY : in STD_LOGIC; SAMPLING_BUSY : in STD_LOGIC;
SAMPLING_DONE : in STD_LOGIC; SAMPLING_DONE : in STD_LOGIC;
START_SAMPLING : out STD_LOGIC; START_SAMPLING : out STD_LOGIC;
@ -114,13 +114,13 @@ begin
to_unsigned(55296, 16); -- 540us to_unsigned(55296, 16); -- 540us
NSAMPLES <= USER_NSAMPLES when CONFIG_DATA(92 downto 90) = "000" else NSAMPLES <= USER_NSAMPLES when CONFIG_DATA(92 downto 90) = "000" else
std_logic_vector(to_unsigned(1, 10)) when CONFIG_DATA(92 downto 90) = "001" else std_logic_vector(to_unsigned(6, 13)) when CONFIG_DATA(92 downto 90) = "001" else
std_logic_vector(to_unsigned(3, 10)) when CONFIG_DATA(92 downto 90) = "010" else std_logic_vector(to_unsigned(19, 13)) when CONFIG_DATA(92 downto 90) = "010" else
std_logic_vector(to_unsigned(7, 10)) when CONFIG_DATA(92 downto 90) = "011" else std_logic_vector(to_unsigned(57, 13)) when CONFIG_DATA(92 downto 90) = "011" else
std_logic_vector(to_unsigned(24, 10)) when CONFIG_DATA(92 downto 90) = "100" else std_logic_vector(to_unsigned(190, 13)) when CONFIG_DATA(92 downto 90) = "100" else
std_logic_vector(to_unsigned(71, 10)) when CONFIG_DATA(92 downto 90) = "101" else std_logic_vector(to_unsigned(571, 13)) when CONFIG_DATA(92 downto 90) = "101" else
std_logic_vector(to_unsigned(238, 10)) when CONFIG_DATA(92 downto 90) = "110" else std_logic_vector(to_unsigned(1904, 13)) when CONFIG_DATA(92 downto 90) = "110" else
std_logic_vector(to_unsigned(714, 10)); std_logic_vector(to_unsigned(5712, 13));
DEBUG_STATUS(10 downto 8) <= "000" when state = TriggerSetup else DEBUG_STATUS(10 downto 8) <= "000" when state = TriggerSetup else
"001" when state = SettingUp else "001" when state = SettingUp else
@ -133,7 +133,7 @@ begin
DEBUG_STATUS(7) <= PLL_RELOAD_DONE; DEBUG_STATUS(7) <= PLL_RELOAD_DONE;
DEBUG_STATUS(6) <= PLL_RELOAD_DONE and PLL_LOCKED; DEBUG_STATUS(6) <= PLL_RELOAD_DONE and PLL_LOCKED;
DEBUG_STATUS(5) <= SAMPLING_BUSY; DEBUG_STATUS(5) <= SAMPLING_BUSY;
DEBUG_STATUS(4 downto 0) <= (others => '0'); DEBUG_STATUS(4 downto 0) <= (others => '1');
process(CLK, RESET) process(CLK, RESET)
begin begin

6
FPGA/VNA/Test_SPI.vhd
View File

@ -216,7 +216,11 @@ BEGIN
wait for CLK_period*10; wait for CLK_period*10;
BUF_IN <= "0000111100001111"; BUF_IN <= "0000111100001111";
wait for CLK_period*10;
CS <= '0';
SPI("0101010101010101");
CS <= '1';
wait; wait;
end process; end process;

247
FPGA/VNA/VNA.gise
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@ -45,7 +45,9 @@
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_SPI_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_SPI_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
@ -62,6 +64,7 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/> <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/> <file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/> <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
@ -125,70 +128,112 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1600501620" xil_pn:in_ck="-6581597313105561379" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1600501620"> <transform xil_pn:end_ts="1601146490" xil_pn:in_ck="-760725241865927573" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1601146490">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1600461368" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5354180755060525133" xil_pn:start_ts="1600461368">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600461368" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4601062479098204721" xil_pn:start_ts="1600461368">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600501224" xil_pn:in_ck="-6615228739331305497" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1600501223">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/> <outfile xil_pn:name="DFT.vhd"/>
<outfile xil_pn:name="MAX2871.vhd"/>
<outfile xil_pn:name="MCP33131.vhd"/>
<outfile xil_pn:name="ResetDelay.vhd"/>
<outfile xil_pn:name="SPIConfig.vhd"/>
<outfile xil_pn:name="Sampling.vhd"/>
<outfile xil_pn:name="Sweep.vhd"/>
<outfile xil_pn:name="Synchronizer.vhd"/>
<outfile xil_pn:name="Test_DFT.vhd"/>
<outfile xil_pn:name="Test_MAX2871.vhd"/>
<outfile xil_pn:name="Test_MCP33131.vhd"/>
<outfile xil_pn:name="Test_PLL.vhd"/>
<outfile xil_pn:name="Test_SPI.vhd"/>
<outfile xil_pn:name="Test_SPICommands.vhd"/>
<outfile xil_pn:name="Test_Sampling.vhd"/>
<outfile xil_pn:name="Test_SinCos.vhd"/>
<outfile xil_pn:name="Test_Sync.vhd"/>
<outfile xil_pn:name="Test_Window.vhd"/>
<outfile xil_pn:name="spi_slave.vhd"/>
<outfile xil_pn:name="top.vhd"/>
<outfile xil_pn:name="window.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1600461349" xil_pn:in_ck="-760725241865927573" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1600461349"> <transform xil_pn:end_ts="1601125757" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2603858341434889151" xil_pn:start_ts="1601125757">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1601125757" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4552913978128179903" xil_pn:start_ts="1601125757">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1601125758" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1601125757">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCosMult.ngc"/>
<outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
</transform>
<transform xil_pn:end_ts="1601146490" xil_pn:in_ck="-7092619378539932792" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1601146490">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/> <outfile xil_pn:name="DFT.vhd"/>
<outfile xil_pn:name="MAX2871.vhd"/>
<outfile xil_pn:name="MCP33131.vhd"/>
<outfile xil_pn:name="ResetDelay.vhd"/>
<outfile xil_pn:name="SPIConfig.vhd"/>
<outfile xil_pn:name="Sampling.vhd"/>
<outfile xil_pn:name="Sweep.vhd"/>
<outfile xil_pn:name="Synchronizer.vhd"/>
<outfile xil_pn:name="Test_DFT.vhd"/>
<outfile xil_pn:name="Test_MAX2871.vhd"/>
<outfile xil_pn:name="Test_MCP33131.vhd"/>
<outfile xil_pn:name="Test_PLL.vhd"/>
<outfile xil_pn:name="Test_SPI.vhd"/>
<outfile xil_pn:name="Test_SPICommands.vhd"/>
<outfile xil_pn:name="Test_Sampling.vhd"/>
<outfile xil_pn:name="Test_SinCos.vhd"/>
<outfile xil_pn:name="Test_Sync.vhd"/>
<outfile xil_pn:name="Test_Window.vhd"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
<outfile xil_pn:name="spi_slave.vhd"/>
<outfile xil_pn:name="top.vhd"/>
<outfile xil_pn:name="window.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1600461373" xil_pn:in_ck="-7092619378539932792" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-5642200015192194106" xil_pn:start_ts="1600461368"> <transform xil_pn:end_ts="1601146493" xil_pn:in_ck="-7092619378539932792" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-75338102225213726" xil_pn:start_ts="1601146490">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/> <outfile xil_pn:name="Test_SPI_beh.prj"/>
<outfile xil_pn:name="Test_SPI_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform> </transform>
<transform xil_pn:end_ts="1600461373" xil_pn:in_ck="-3358899429776077154" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8724408846642916045" xil_pn:start_ts="1600461373"> <transform xil_pn:end_ts="1601146493" xil_pn:in_ck="-3358899429776077154" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1346610876870411377" xil_pn:start_ts="1601146493">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/> <outfile xil_pn:name="Test_SPI_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
</transform> </transform>
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600270761"> <transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600270761">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
@ -198,15 +243,16 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1600270761"> <transform xil_pn:end_ts="1601116205" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1601116205">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<status xil_pn:value="OutOfDateForOutputs"/> <outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
<status xil_pn:value="InputAdded"/> <outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
<status xil_pn:value="InputChanged"/> <outfile xil_pn:name="ipcore_dir/SinCosMult.ngc"/>
<status xil_pn:value="InputRemoved"/> <outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
<status xil_pn:value="OutputRemoved"/> <outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
</transform> </transform>
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600270761"> <transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600270761">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
@ -219,77 +265,88 @@
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1600270761"> <transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1600270761">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1600270761"> <transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1600270761">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1600362196" xil_pn:in_ck="-1505308035655400832" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600362176"> <transform xil_pn:end_ts="1601146735" xil_pn:in_ck="-4506597320363840754" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1601146716">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/> <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="top.lso"/>
<outfile xil_pn:name="top.ngc"/>
<outfile xil_pn:name="top.ngr"/>
<outfile xil_pn:name="top.prj"/>
<outfile xil_pn:name="top.stx"/>
<outfile xil_pn:name="top.syr"/>
<outfile xil_pn:name="top.xst"/>
<outfile xil_pn:name="top_xst.xrpt"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1600270780" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1600270780"> <transform xil_pn:end_ts="1601131743" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1601131743">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
</transform> </transform>
<transform xil_pn:end_ts="1600362202" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600362196"> <transform xil_pn:end_ts="1601146742" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1601146735">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <outfile xil_pn:name="_ngo"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<status xil_pn:value="OutOfDateForOutputs"/> <outfile xil_pn:name="top.bld"/>
<status xil_pn:value="InputAdded"/> <outfile xil_pn:name="top.ngd"/>
<status xil_pn:value="InputChanged"/> <outfile xil_pn:name="top_ngdbuild.xrpt"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1600362238" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600362202"> <transform xil_pn:end_ts="1601146779" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1601146742">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="NotReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <outfile xil_pn:name="top.pcf"/>
<status xil_pn:value="OutOfDateForOutputs"/> <outfile xil_pn:name="top_map.map"/>
<status xil_pn:value="InputRemoved"/> <outfile xil_pn:name="top_map.mrp"/>
<status xil_pn:value="OutputChanged"/> <outfile xil_pn:name="top_map.ncd"/>
<status xil_pn:value="OutputRemoved"/> <outfile xil_pn:name="top_map.ngm"/>
<outfile xil_pn:name="top_map.xrpt"/>
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1600362265" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600362238"> <transform xil_pn:end_ts="1601146806" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1601146779">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <outfile xil_pn:name="top.ncd"/>
<status xil_pn:value="OutOfDateForOutputs"/> <outfile xil_pn:name="top.pad"/>
<status xil_pn:value="InputRemoved"/> <outfile xil_pn:name="top.par"/>
<status xil_pn:value="OutputRemoved"/> <outfile xil_pn:name="top.ptwx"/>
<outfile xil_pn:name="top.unroutes"/>
<outfile xil_pn:name="top.xpi"/>
<outfile xil_pn:name="top_pad.csv"/>
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1600362278" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1600362265"> <transform xil_pn:end_ts="1601146819" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1601146806">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="NotReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <outfile xil_pn:name="top.bgn"/>
<status xil_pn:value="OutOfDateForOutputs"/> <outfile xil_pn:name="top.bin"/>
<status xil_pn:value="InputRemoved"/> <outfile xil_pn:name="top.bit"/>
<status xil_pn:value="OutputRemoved"/> <outfile xil_pn:name="top.drc"/>
<outfile xil_pn:name="top.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1591357065" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-2382555676865099342" xil_pn:start_ts="1591357065"> <transform xil_pn:end_ts="1591357065" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-2382555676865099342" xil_pn:start_ts="1591357065">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/> <status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
@ -298,9 +355,8 @@
</transform> </transform>
<transform xil_pn:end_ts="1591357024" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="-8856759851099153863" xil_pn:start_ts="1591357024"> <transform xil_pn:end_ts="1591357024" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="-8856759851099153863" xil_pn:start_ts="1591357024">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/> <status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
@ -310,9 +366,8 @@
</transform> </transform>
<transform xil_pn:end_ts="1591357058" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="7381105705363676227" xil_pn:start_ts="1591357058"> <transform xil_pn:end_ts="1591357058" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="7381105705363676227" xil_pn:start_ts="1591357058">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputAdded"/> <status xil_pn:value="InputAdded"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="InputChanged"/>
@ -320,14 +375,12 @@
<status xil_pn:value="OutputChanged"/> <status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/> <status xil_pn:value="OutputRemoved"/>
</transform> </transform>
<transform xil_pn:end_ts="1600362265" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600362259"> <transform xil_pn:end_ts="1601146806" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1601146800">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="NotReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<status xil_pn:value="OutOfDateForPredecessor"/> <outfile xil_pn:name="top.twr"/>
<status xil_pn:value="OutOfDateForOutputs"/> <outfile xil_pn:name="top.twx"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputRemoved"/>
</transform> </transform>
</transforms> </transforms>

14
FPGA/VNA/VNA.xise
View File

@ -59,7 +59,7 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
</file> </file>
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
@ -107,7 +107,7 @@
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="Test_SPI.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Test_SPI.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="133"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="133"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="133"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="133"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="133"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="133"/>
@ -128,7 +128,7 @@
</file> </file>
<file xil_pn:name="DFT.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="DFT.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="143"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="Test_DFT.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="Test_DFT.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -392,8 +392,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_SPI" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_SPI" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -411,7 +411,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_SPI" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -463,7 +463,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_DFT|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_SPI|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

26
FPGA/VNA/spi_slave.vhd
View File

@ -46,14 +46,14 @@ entity spi_slave is
end spi_slave; end spi_slave;
architecture Behavioral of spi_slave is architecture Behavioral of spi_slave is
signal miso_buffer : STD_LOGIC_VECTOR (W-1 downto 0); --signal miso_buffer : STD_LOGIC_VECTOR (W-1 downto 0);
signal mosi_buffer : STD_LOGIC_VECTOR (W-2 downto 0); signal mosi_buffer : STD_LOGIC_VECTOR (W-2 downto 0);
signal data_valid : STD_LOGIC_VECTOR(2 downto 0); signal data_valid : STD_LOGIC_VECTOR(2 downto 0);
signal data_synced : STD_LOGIC_VECTOR(2 downto 0); signal data_synced : STD_LOGIC_VECTOR(2 downto 0);
signal data : STD_LOGIC_VECTOR(W-1 downto 0); signal data : STD_LOGIC_VECTOR(W-1 downto 0);
signal bit_cnt : STD_LOGIC_VECTOR(W-2 downto 0); signal bit_cnt : integer range 0 to W-1;
begin begin
process(CLK) process(CLK)
@ -75,14 +75,14 @@ begin
end if; end if;
end process; end process;
MISO <= miso_buffer(W-1) when CS = '0' else 'Z'; MISO <= BUF_IN(W - 1 - bit_cnt);-- when bit_cnt = 0 else miso_buffer(W-2);
slave_in: process(SPI_CLK) slave_in: process(SPI_CLK)
begin begin
if rising_edge(SPI_CLK) then if rising_edge(SPI_CLK) then
-- FALLING_TOGGLE <= not FALLING_TOGGLE; -- FALLING_TOGGLE <= not FALLING_TOGGLE;
data_synced(2 downto 1) <= data_synced(1 downto 0); data_synced(2 downto 1) <= data_synced(1 downto 0);
if bit_cnt(W-2) = '1' then if bit_cnt = W-1 then
-- this was the last bit -- this was the last bit
data_valid(0) <= '1'; data_valid(0) <= '1';
data <= mosi_buffer(W-2 downto 0) & MOSI; data <= mosi_buffer(W-2 downto 0) & MOSI;
@ -98,15 +98,19 @@ begin
slave_out: process(SPI_CLK, CS, BUF_IN, bit_cnt) slave_out: process(SPI_CLK, CS, BUF_IN, bit_cnt)
begin begin
if CS = '1' then if CS = '1' then
bit_cnt <= (others => '0'); bit_cnt <= 0;
miso_buffer <= BUF_IN; --miso_buffer <= BUF_IN;
elsif falling_edge(SPI_CLK) then elsif falling_edge(SPI_CLK) then
if bit_cnt(W-2) = '0' then if bit_cnt < W-1 then
bit_cnt <= bit_cnt(W-3 downto 0) & '1'; bit_cnt <= bit_cnt + 1;
miso_buffer <= miso_buffer(W-2 downto 0) & '0'; if bit_cnt = 0 then
--miso_buffer <= BUF_IN;
else
--miso_buffer <= miso_buffer(W-2 downto 0) & '0';
end if;
else else
bit_cnt <= (others => '0'); bit_cnt <= 0;
miso_buffer <= BUF_IN; --miso_buffer <= BUF_IN;
end if; end if;
end if; end if;
end process; end process;

BIN
FPGA/VNA/top.bin
View File

Binary file not shown.

1
FPGA/VNA/top.ucf
View File

@ -1,5 +1,6 @@
CONFIG VCCAUX = 3.3; CONFIG VCCAUX = 3.3;
NET "CLK" PERIOD = 62.5 ns; NET "CLK" PERIOD = 62.5 ns;
NET "MCU_SCK" PERIOD = 31.25ns;
NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33; NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33;
NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33; NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33;

12
FPGA/VNA/top.vhd
View File

@ -112,8 +112,8 @@ architecture Behavioral of top is
RESET : IN std_logic; RESET : IN std_logic;
NPOINTS : IN std_logic_vector(12 downto 0); NPOINTS : IN std_logic_vector(12 downto 0);
CONFIG_DATA : IN std_logic_vector(95 downto 0); CONFIG_DATA : IN std_logic_vector(95 downto 0);
USER_NSAMPLES : in STD_LOGIC_VECTOR (9 downto 0); USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
NSAMPLES : out STD_LOGIC_VECTOR (9 downto 0); NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
SAMPLING_BUSY : in STD_LOGIC; SAMPLING_BUSY : in STD_LOGIC;
SAMPLING_DONE : IN std_logic; SAMPLING_DONE : IN std_logic;
MAX2871_DEF_4 : IN std_logic_vector(31 downto 0); MAX2871_DEF_4 : IN std_logic_vector(31 downto 0);
@ -156,7 +156,7 @@ architecture Behavioral of top is
REF : IN std_logic_vector(15 downto 0); REF : IN std_logic_vector(15 downto 0);
NEW_SAMPLE : IN std_logic; NEW_SAMPLE : IN std_logic;
START : IN std_logic; START : IN std_logic;
SAMPLES : IN std_logic_vector(9 downto 0); SAMPLES : IN std_logic_vector(12 downto 0);
WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0); WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
ADC_START : OUT std_logic; ADC_START : OUT std_logic;
DONE : OUT std_logic; DONE : OUT std_logic;
@ -224,7 +224,7 @@ architecture Behavioral of top is
SWEEP_ADDRESS : OUT std_logic_vector(12 downto 0); SWEEP_ADDRESS : OUT std_logic_vector(12 downto 0);
SWEEP_WRITE : OUT std_logic_vector(0 to 0); SWEEP_WRITE : OUT std_logic_vector(0 to 0);
SWEEP_POINTS : OUT std_logic_vector(12 downto 0); SWEEP_POINTS : OUT std_logic_vector(12 downto 0);
NSAMPLES : OUT std_logic_vector(9 downto 0); NSAMPLES : OUT std_logic_vector(12 downto 0);
EXCITE_PORT1 : out STD_LOGIC; EXCITE_PORT1 : out STD_LOGIC;
EXCITE_PORT2 : out STD_LOGIC; EXCITE_PORT2 : out STD_LOGIC;
PORT1_EN : out STD_LOGIC; PORT1_EN : out STD_LOGIC;
@ -305,8 +305,8 @@ architecture Behavioral of top is
signal sampling_busy : std_logic; signal sampling_busy : std_logic;
signal sampling_done : std_logic; signal sampling_done : std_logic;
signal sampling_start : std_logic; signal sampling_start : std_logic;
signal sampling_samples : std_logic_vector(9 downto 0); signal sampling_samples : std_logic_vector(12 downto 0);
signal sampling_user_samples : std_logic_vector(9 downto 0); signal sampling_user_samples : std_logic_vector(12 downto 0);
signal sampling_result : std_logic_vector(287 downto 0); signal sampling_result : std_logic_vector(287 downto 0);
signal sampling_window : std_logic_vector(1 downto 0); signal sampling_window : std_logic_vector(1 downto 0);
signal sampling_prescaler : std_logic_vector(7 downto 0); signal sampling_prescaler : std_logic_vector(7 downto 0);

22
Software/PC_Application/Device/device.cpp
View File

@ -105,6 +105,18 @@ uint8_t *USBInBuffer::getBuffer() const
return buffer; return buffer;
} }
static Protocol::DeviceLimits limits = {
.minFreq = 1000000,
.maxFreq = 6000000000,
.minIFBW = 10,
.maxIFBW = 10000,
.maxPoints = 4501,
.cdbm_min = -4000,
.cdbm_max = -1000,
.minRBW = 10,
.maxRBW = 10000,
};
Device::Device(QString serial) Device::Device(QString serial)
{ {
qDebug() << "Starting device connection..."; qDebug() << "Starting device connection...";
@ -162,6 +174,8 @@ Device::Device(QString serial)
connect(&transmissionTimer, &QTimer::timeout, this, &Device::transmissionTimeout); connect(&transmissionTimer, &QTimer::timeout, this, &Device::transmissionTimeout);
transmissionTimer.setSingleShot(true); transmissionTimer.setSingleShot(true);
transmissionActive = false; transmissionActive = false;
// got a new connection, request limits
SendCommandWithoutPayload(Protocol::PacketType::RequestDeviceLimits);
} }
Device::~Device() Device::~Device()
@ -251,6 +265,11 @@ std::set<QString> Device::GetDevices()
return serials; return serials;
} }
Protocol::DeviceLimits Device::Limits()
{
return limits;
}
void Device::USBHandleThread() void Device::USBHandleThread()
{ {
qInfo() << "Receive thread started" << flush; qInfo() << "Receive thread started" << flush;
@ -388,6 +407,9 @@ void Device::ReceivedData()
emit NackReceived(); emit NackReceived();
// transmissionFinished(TransmissionResult::Nack); // transmissionFinished(TransmissionResult::Nack);
break; break;
case Protocol::PacketType::DeviceLimits:
limits = packet.limits;
break;
default: default:
break; break;
} }

5
Software/PC_Application/Device/device.h
View File

@ -62,12 +62,13 @@ public:
bool SetManual(Protocol::ManualControl manual); bool SetManual(Protocol::ManualControl manual);
bool SendFirmwareChunk(Protocol::FirmwarePacket &fw); bool SendFirmwareChunk(Protocol::FirmwarePacket &fw);
bool SendCommandWithoutPayload(Protocol::PacketType type); bool SendCommandWithoutPayload(Protocol::PacketType type);
// Returns serial numbers of all connected devices
static std::set<QString> GetDevices();
QString serial() const; QString serial() const;
Protocol::DeviceInfo getLastInfo() const; Protocol::DeviceInfo getLastInfo() const;
QString getLastDeviceInfoString(); QString getLastDeviceInfoString();
// Returns serial numbers of all connected devices
static std::set<QString> GetDevices();
static Protocol::DeviceLimits Limits();
signals: signals:
void DatapointReceived(Protocol::Datapoint); void DatapointReceived(Protocol::Datapoint);
void ManualStatusReceived(Protocol::ManualStatus); void ManualStatusReceived(Protocol::ManualStatus);

9
Software/PC_Application/Generator/signalgenwidget.cpp
View File

@ -10,11 +10,10 @@ SignalgeneratorWidget::SignalgeneratorWidget(QWidget *parent) :
ui->frequency->setPrefixes(" kMG"); ui->frequency->setPrefixes(" kMG");
connect(ui->frequency, &SIUnitEdit::valueChanged, [=](double newval) { connect(ui->frequency, &SIUnitEdit::valueChanged, [=](double newval) {
// TODO centralize min/max values if(newval < Device::Limits().minFreq) {
if(newval < 9000) { newval = Device::Limits().minFreq;
newval = 9000; } else if (newval > Device::Limits().maxFreq) {
} else if (newval > 6000000000) { newval = Device::Limits().maxFreq;
newval = 6000000000;
} }
ui->frequency->setValueQuiet(newval); ui->frequency->setValueQuiet(newval);
emit SettingsChanged(); emit SettingsChanged();

17
Software/PC_Application/SpectrumAnalyzer/spectrumanalyzer.cpp
View File

@ -295,8 +295,8 @@ void SpectrumAnalyzer::SetSpan(double span)
void SpectrumAnalyzer::SetFullSpan() void SpectrumAnalyzer::SetFullSpan()
{ {
settings.f_start = 0; settings.f_start = Device::Limits().minFreq;
settings.f_stop = 6000000000; settings.f_stop = Device::Limits().maxFreq;
ConstrainAndUpdateFrequencies(); ConstrainAndUpdateFrequencies();
} }
@ -324,6 +324,11 @@ void SpectrumAnalyzer::SpanZoomOut()
void SpectrumAnalyzer::SetRBW(double bandwidth) void SpectrumAnalyzer::SetRBW(double bandwidth)
{ {
if(bandwidth > Device::Limits().maxRBW) {
bandwidth = Device::Limits().maxRBW;
} else if(bandwidth < Device::Limits().minRBW) {
bandwidth = Device::Limits().minRBW;
}
settings.RBW = bandwidth; settings.RBW = bandwidth;
emit RBWChanged(settings.RBW); emit RBWChanged(settings.RBW);
SettingsChanged(); SettingsChanged();
@ -339,13 +344,15 @@ void SpectrumAnalyzer::SetAveraging(unsigned int averages)
void SpectrumAnalyzer::ConstrainAndUpdateFrequencies() void SpectrumAnalyzer::ConstrainAndUpdateFrequencies()
{ {
// TODO central hardware limits if(settings.f_stop > Device::Limits().maxFreq) {
if(settings.f_stop > 6000000000) { settings.f_stop = Device::Limits().maxFreq;
settings.f_stop = 6000000000;
} }
if(settings.f_start > settings.f_stop) { if(settings.f_start > settings.f_stop) {
settings.f_start = settings.f_stop; settings.f_start = settings.f_stop;
} }
if(settings.f_start < Device::Limits().minFreq) {
settings.f_start = Device::Limits().minFreq;
}
emit startFreqChanged(settings.f_start); emit startFreqChanged(settings.f_start);
emit stopFreqChanged(settings.f_stop); emit stopFreqChanged(settings.f_stop);
emit spanChanged(settings.f_stop - settings.f_start); emit spanChanged(settings.f_stop - settings.f_start);

29
Software/PC_Application/VNA/vna.cpp
View File

@ -600,8 +600,8 @@ void VNA::SetSpan(double span)
void VNA::SetFullSpan() void VNA::SetFullSpan()
{ {
settings.f_start = 0; settings.f_start = Device::Limits().minFreq;
settings.f_stop = 6000000000; settings.f_stop = Device::Limits().maxFreq;
ConstrainAndUpdateFrequencies(); ConstrainAndUpdateFrequencies();
} }
@ -630,10 +630,10 @@ void VNA::SpanZoomOut()
void VNA::SetSourceLevel(double level) void VNA::SetSourceLevel(double level)
{ {
// TODO remove hardcoded limits // TODO remove hardcoded limits
if(level > -10.0) { if(level > Device::Limits().cdbm_max / 100.0) {
level = -10.0; level = Device::Limits().cdbm_max / 100.0;
} else if(level < -42.0) { } else if(level < Device::Limits().cdbm_min / 100.0) {
level = -42.0; level = Device::Limits().cdbm_min / 100.0;
} }
emit sourceLevelChanged(level); emit sourceLevelChanged(level);
settings.cdbm_excitation = level * 100; settings.cdbm_excitation = level * 100;
@ -645,8 +645,8 @@ void VNA::SetPoints(unsigned int points)
// TODO remove hardcoded limits // TODO remove hardcoded limits
if (points < 1) { if (points < 1) {
points = 1; points = 1;
} else if(points > 4501) { } else if(points > Device::Limits().maxPoints) {
points = 4501; points = Device::Limits().maxPoints;
} }
emit pointsChanged(points); emit pointsChanged(points);
settings.points = points; settings.points = points;
@ -655,6 +655,11 @@ void VNA::SetPoints(unsigned int points)
void VNA::SetIFBandwidth(double bandwidth) void VNA::SetIFBandwidth(double bandwidth)
{ {
if(bandwidth > Device::Limits().maxIFBW) {
bandwidth = Device::Limits().maxIFBW;
} else if(bandwidth < Device::Limits().minIFBW) {
bandwidth = Device::Limits().minIFBW;
}
settings.if_bandwidth = bandwidth; settings.if_bandwidth = bandwidth;
emit IFBandwidthChanged(bandwidth); emit IFBandwidthChanged(bandwidth);
SettingsChanged(); SettingsChanged();
@ -747,13 +752,15 @@ void VNA::StartCalibrationMeasurement(Calibration::Measurement m)
void VNA::ConstrainAndUpdateFrequencies() void VNA::ConstrainAndUpdateFrequencies()
{ {
// TODO central hardware limits if(settings.f_stop > Device::Limits().maxFreq) {
if(settings.f_stop > 6000000000) { settings.f_stop = Device::Limits().maxFreq;
settings.f_stop = 6000000000;
} }
if(settings.f_start > settings.f_stop) { if(settings.f_start > settings.f_stop) {
settings.f_start = settings.f_stop; settings.f_start = settings.f_stop;
} }
if(settings.f_start < Device::Limits().minFreq) {
settings.f_start = Device::Limits().minFreq;
}
emit startFreqChanged(settings.f_start); emit startFreqChanged(settings.f_start);
emit stopFreqChanged(settings.f_stop); emit stopFreqChanged(settings.f_stop);
emit spanChanged(settings.f_stop - settings.f_start); emit spanChanged(settings.f_stop - settings.f_start);

554
Software/VNA_embedded/.cproject
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File diff suppressed because it is too large Load Diff

2
Software/VNA_embedded/.mxproject
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File diff suppressed because one or more lines are too long

7
Software/VNA_embedded/Application/App.cpp
View File

@ -61,6 +61,7 @@ static void HardwareWorkRequired() {
} }
void App_Start() { void App_Start() {
STM::Init();
HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED); HAL_ADCEx_Calibration_Start(&hadc1, ADC_SINGLE_ENDED);
handle = xTaskGetCurrentTaskHandle(); handle = xTaskGetCurrentTaskHandle();
usb_init(communication_usb_input); usb_init(communication_usb_input);
@ -162,6 +163,12 @@ void App_Start() {
SA::Setup(packet.spectrumSettings); SA::Setup(packet.spectrumSettings);
Communication::SendWithoutPayload(Protocol::PacketType::Ack); Communication::SendWithoutPayload(Protocol::PacketType::Ack);
break; break;
case Protocol::PacketType::RequestDeviceLimits:
Protocol::PacketInfo p;
p.type = Protocol::PacketType::DeviceLimits;
p.limits = HW::Limits;
Communication::Send(p);
break;
#ifdef HAS_FLASH #ifdef HAS_FLASH
case Protocol::PacketType::ClearFlash: case Protocol::PacketType::ClearFlash:
HW::SetMode(HW::Mode::Idle); HW::SetMode(HW::Mode::Idle);

37
Software/VNA_embedded/Application/Communication/Protocol.cpp
View File

@ -404,6 +404,35 @@ static int16_t EncodeSpectrumAnalyzerResult(Protocol::SpectrumAnalyzerResult d,
return e.getSize(); return e.getSize();
} }
static Protocol::DeviceLimits DecodeDeviceLimits(uint8_t *buf) {
Protocol::DeviceLimits d;
Decoder e(buf);
e.get(d.minFreq);
e.get(d.maxFreq);
e.get(d.minIFBW);
e.get(d.maxIFBW);
e.get(d.maxPoints);
e.get(d.cdbm_min);
e.get(d.cdbm_max);
e.get(d.minRBW);
e.get(d.maxRBW);
return d;
}
static int16_t EncodeDeviceLimits(Protocol::DeviceLimits d, uint8_t *buf,
uint16_t bufSize) {
Encoder e(buf, bufSize);
e.add(d.minFreq);
e.add(d.maxFreq);
e.add(d.minIFBW);
e.add(d.maxIFBW);
e.add(d.maxPoints);
e.add(d.cdbm_min);
e.add(d.cdbm_max);
e.add(d.minRBW);
e.add(d.maxRBW);
return e.getSize();
}
static Protocol::FirmwarePacket DecodeFirmwarePacket(uint8_t *buf) { static Protocol::FirmwarePacket DecodeFirmwarePacket(uint8_t *buf) {
Protocol::FirmwarePacket d; Protocol::FirmwarePacket d;
// simple packet format, memcpy is faster than using the decoder // simple packet format, memcpy is faster than using the decoder
@ -498,10 +527,14 @@ uint16_t Protocol::DecodeBuffer(uint8_t *buf, uint16_t len, PacketInfo *info) {
case PacketType::SpectrumAnalyzerResult: case PacketType::SpectrumAnalyzerResult:
info->spectrumResult = DecodeSpectrumAnalyzerResult(&data[4]); info->spectrumResult = DecodeSpectrumAnalyzerResult(&data[4]);
break; break;
case PacketType::DeviceLimits:
info->limits = DecodeDeviceLimits(&data[4]);
break;
case PacketType::Ack: case PacketType::Ack:
case PacketType::PerformFirmwareUpdate: case PacketType::PerformFirmwareUpdate:
case PacketType::ClearFlash: case PacketType::ClearFlash:
case PacketType::Nack: case PacketType::Nack:
case PacketType::RequestDeviceLimits:
// no payload, nothing to do // no payload, nothing to do
break; break;
case PacketType::None: case PacketType::None:
@ -544,10 +577,14 @@ uint16_t Protocol::EncodePacket(PacketInfo packet, uint8_t *dest, uint16_t dests
case PacketType::SpectrumAnalyzerResult: case PacketType::SpectrumAnalyzerResult:
payload_size = EncodeSpectrumAnalyzerResult(packet.spectrumResult, &dest[4], destsize - 8); payload_size = EncodeSpectrumAnalyzerResult(packet.spectrumResult, &dest[4], destsize - 8);
break; break;
case PacketType::DeviceLimits:
payload_size = EncodeDeviceLimits(packet.limits, &dest[4], destsize - 8);
break;
case PacketType::Ack: case PacketType::Ack:
case PacketType::PerformFirmwareUpdate: case PacketType::PerformFirmwareUpdate:
case PacketType::ClearFlash: case PacketType::ClearFlash:
case PacketType::Nack: case PacketType::Nack:
case PacketType::RequestDeviceLimits:
// no payload, nothing to do // no payload, nothing to do
break; break;
case PacketType::None: case PacketType::None:

15
Software/VNA_embedded/Application/Communication/Protocol.hpp
View File

@ -116,6 +116,18 @@ using SpectrumAnalyzerResult = struct _spectrumAnalyzerResult {
uint16_t pointNum; uint16_t pointNum;
}; };
using DeviceLimits = struct _deviceLimits {
uint64_t minFreq;
uint64_t maxFreq;
uint32_t minIFBW;
uint32_t maxIFBW;
uint16_t maxPoints;
int16_t cdbm_min;
int16_t cdbm_max;
uint32_t minRBW;
uint32_t maxRBW;
};
static constexpr uint16_t FirmwareChunkSize = 256; static constexpr uint16_t FirmwareChunkSize = 256;
using FirmwarePacket = struct _firmwarePacket { using FirmwarePacket = struct _firmwarePacket {
uint32_t address; uint32_t address;
@ -138,6 +150,8 @@ enum class PacketType : uint8_t {
Generator = 12, Generator = 12,
SpectrumAnalyzerSettings = 13, SpectrumAnalyzerSettings = 13,
SpectrumAnalyzerResult = 14, SpectrumAnalyzerResult = 14,
RequestDeviceLimits = 15,
DeviceLimits = 16,
}; };
using PacketInfo = struct _packetinfo { using PacketInfo = struct _packetinfo {
@ -153,6 +167,7 @@ using PacketInfo = struct _packetinfo {
ManualStatus status; ManualStatus status;
SpectrumAnalyzerSettings spectrumSettings; SpectrumAnalyzerSettings spectrumSettings;
SpectrumAnalyzerResult spectrumResult; SpectrumAnalyzerResult spectrumResult;
DeviceLimits limits;
}; };
}; };

14
Software/VNA_embedded/Application/Drivers/Exti.cpp
View File

@ -11,13 +11,13 @@ static constexpr uint8_t MaxEntries = 16;
static Entry entries[MaxEntries]; static Entry entries[MaxEntries];
void Exti::Init() { void Exti::Init() {
HAL_NVIC_SetPriority(EXTI0_IRQn, 5, 0); HAL_NVIC_SetPriority(EXTI0_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI1_IRQn, 5, 0); HAL_NVIC_SetPriority(EXTI1_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI2_IRQn, 5, 0); HAL_NVIC_SetPriority(EXTI2_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI3_IRQn, 5, 0); HAL_NVIC_SetPriority(EXTI3_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI4_IRQn, 5, 0); HAL_NVIC_SetPriority(EXTI4_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI9_5_IRQn, 5, 0); HAL_NVIC_SetPriority(EXTI9_5_IRQn, 1, 0);
HAL_NVIC_SetPriority(EXTI15_10_IRQn, 5, 0); HAL_NVIC_SetPriority(EXTI15_10_IRQn, 1, 0);
HAL_NVIC_EnableIRQ(EXTI0_IRQn); HAL_NVIC_EnableIRQ(EXTI0_IRQn);
HAL_NVIC_EnableIRQ(EXTI1_IRQn); HAL_NVIC_EnableIRQ(EXTI1_IRQn);
HAL_NVIC_EnableIRQ(EXTI2_IRQn); HAL_NVIC_EnableIRQ(EXTI2_IRQn);

35
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
View File

@ -85,6 +85,7 @@ bool FPGA::Init(HaltedCallback cb) {
// Reset FPGA // Reset FPGA
High(FPGA_RESET); High(FPGA_RESET);
SetMode(Mode::FPGA); SetMode(Mode::FPGA);
AbortSweep();
Delay::us(1); Delay::us(1);
Low(FPGA_RESET); Low(FPGA_RESET);
Delay::ms(10); Delay::ms(10);
@ -114,11 +115,11 @@ void FPGA::SetNumberOfPoints(uint16_t npoints) {
} }
void FPGA::SetSamplesPerPoint(uint32_t nsamples) { void FPGA::SetSamplesPerPoint(uint32_t nsamples) {
// register is in multiples of 128 // register is in multiples of 16
nsamples /= 128; nsamples /= 16;
// constrain to maximum value // constrain to maximum value
if(nsamples >= 1024) { if(nsamples >= 8192) {
nsamples = 1023; nsamples = 8192;
} }
WriteRegister(Reg::SamplesPerPoint, nsamples); WriteRegister(Reg::SamplesPerPoint, nsamples);
} }
@ -238,8 +239,15 @@ static inline int64_t sign_extend_64(int64_t x, uint16_t bits) {
static FPGA::ReadCallback callback; static FPGA::ReadCallback callback;
static uint8_t raw[36]; static uint8_t raw[36];
static bool halted; static bool halted;
static bool new_sample;
static FPGA::SamplingResult result;
static bool busy_reading = false;
bool FPGA::InitiateSampleRead(ReadCallback cb) { bool FPGA::InitiateSampleRead(ReadCallback cb) {
if(busy_reading) {
LOG_ERR("ISR while still reading old data");
return false;
}
callback = cb; callback = cb;
uint8_t cmd[2] = {0xC0, 0x00}; uint8_t cmd[2] = {0xC0, 0x00};
uint16_t status; uint16_t status;
@ -260,8 +268,9 @@ bool FPGA::InitiateSampleRead(ReadCallback cb) {
High(CS); High(CS);
if (halted) { if (halted) {
if (halted_cb) { if (halted && halted_cb) {
halted_cb(); halted_cb();
halted = false;
} }
} else { } else {
LOG_WARN("ISR without new data, status: 0x%04x", status); LOG_WARN("ISR without new data, status: 0x%04x", status);
@ -270,6 +279,7 @@ bool FPGA::InitiateSampleRead(ReadCallback cb) {
} }
// Start data read // Start data read
busy_reading = true;
HAL_SPI_Receive_DMA(&FPGA_SPI, raw, 36); HAL_SPI_Receive_DMA(&FPGA_SPI, raw, 36);
return true; return true;
} }
@ -283,8 +293,6 @@ static int64_t assembleSampleResultValue(uint8_t *raw) {
extern "C" { extern "C" {
void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) { void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) {
FPGA::SamplingResult result;
High(CS);
// Assemble data from words // Assemble data from words
result.P1I = assembleSampleResultValue(&raw[30]); result.P1I = assembleSampleResultValue(&raw[30]);
result.P1Q = assembleSampleResultValue(&raw[24]); result.P1Q = assembleSampleResultValue(&raw[24]);
@ -292,11 +300,16 @@ void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) {
result.P2Q = assembleSampleResultValue(&raw[12]); result.P2Q = assembleSampleResultValue(&raw[12]);
result.RefI = assembleSampleResultValue(&raw[6]); result.RefI = assembleSampleResultValue(&raw[6]);
result.RefQ = assembleSampleResultValue(&raw[0]); result.RefQ = assembleSampleResultValue(&raw[0]);
if (callback) { High(CS);
busy_reading = false;
new_sample = true;
if (new_sample && callback) {
callback(result); callback(result);
new_sample = false;
} }
if (halted && halted_cb) { if (halted && halted_cb) {
halted_cb(); halted_cb();
halted = false;
} }
} }
} }
@ -319,18 +332,24 @@ void FPGA::SetMode(Mode mode) {
Low(AUX2); Low(AUX2);
Delay::us(1); Delay::us(1);
High(CS); High(CS);
// Configure SPI to use faster speed of 32MHz
FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_4;
break; break;
case Mode::SourcePLL: case Mode::SourcePLL:
Low(CS); Low(CS);
Low(AUX2); Low(AUX2);
Delay::us(1); Delay::us(1);
High(AUX1); High(AUX1);
// Configure SPI to use slower speed of 16MHz (MAX2871 is limited to 20MHz)
FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_8;
break; break;
case Mode::LOPLL: case Mode::LOPLL:
Low(CS); Low(CS);
Low(AUX1); Low(AUX1);
Delay::us(1); Delay::us(1);
High(AUX2); High(AUX2);
// Configure SPI to use slower speed of 16MHz (MAX2871 is limited to 20MHz)
FPGA_SPI.Instance->CR1 = (FPGA_SPI.Instance->CR1 & ~SPI_CR1_BR_Msk) | SPI_BAUDRATEPRESCALER_8;
break; break;
} }
Delay::us(1); Delay::us(1);

10
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
View File

@ -78,11 +78,11 @@ enum class SettlingTime {
enum class Samples { enum class Samples {
SPPRegister = 0x00, SPPRegister = 0x00,
S128 = 0x01, S96 = 0x01,
S384 = 0x02, S304 = 0x02,
S896 = 0x03, S912 = 0x03,
S3072 = 0x04, S3040 = 0x04,
S9088 = 0x05, S9136 = 0x05,
S30464 = 0x06, S30464 = 0x06,
S91392 = 0x07, S91392 = 0x07,
}; };

2
Software/VNA_embedded/Application/Drivers/Log.cpp
View File

@ -79,7 +79,7 @@ void Log_Init() {
#endif #endif
/* USART interrupt Init */ /* USART interrupt Init */
HAL_NVIC_SetPriority(NVIC_ISR, 5, 0); HAL_NVIC_SetPriority(NVIC_ISR, 0, 0);
HAL_NVIC_EnableIRQ(NVIC_ISR); HAL_NVIC_EnableIRQ(NVIC_ISR);
} }

4
Software/VNA_embedded/Application/Drivers/USB/usb.c
View File

@ -187,9 +187,9 @@ void usb_init(usbd_callback_t callback) {
USBD_Init(&hUsbDeviceFS, &FS_Desc, 0); USBD_Init(&hUsbDeviceFS, &FS_Desc, 0);
USBD_RegisterClass(&hUsbDeviceFS, &USBD_ClassDriver); USBD_RegisterClass(&hUsbDeviceFS, &USBD_ClassDriver);
USBD_Start(&hUsbDeviceFS); USBD_Start(&hUsbDeviceFS);
HAL_NVIC_SetPriority(USB_HP_IRQn, 6, 0); HAL_NVIC_SetPriority(USB_HP_IRQn, 7, 0);
HAL_NVIC_EnableIRQ(USB_HP_IRQn); HAL_NVIC_EnableIRQ(USB_HP_IRQn);
HAL_NVIC_SetPriority(USB_LP_IRQn, 6, 0); HAL_NVIC_SetPriority(USB_LP_IRQn, 7, 0);
HAL_NVIC_EnableIRQ(USB_LP_IRQn); HAL_NVIC_EnableIRQ(USB_LP_IRQn);
} }

50
Software/VNA_embedded/Application/Drivers/stm.cpp Normal file
View File

@ -0,0 +1,50 @@
#include "stm.hpp"
using Callback = void(*)(void);
static constexpr uint8_t numCallbacks = 10;
static Callback callbacks[numCallbacks];
uint8_t read_index, write_index;
static void increment(uint8_t &index) {
if(index < numCallbacks - 1) {
index++;
} else {
index = 0;
}
}
static uint8_t callbackFifoLevel() {
int8_t level = (int8_t) write_index - (int8_t) read_index;
if(level < 0) {
level += numCallbacks;
}
return (uint8_t) level;
}
void STM::Init() {
read_index = write_index = 0;
HAL_NVIC_SetPriority(COMP4_IRQn, 6, 0);
HAL_NVIC_EnableIRQ(COMP4_IRQn);
}
bool STM::DispatchToInterrupt(void (*cb)(void)) {
if(callbackFifoLevel() < numCallbacks - 1) {
callbacks[write_index] = cb;
increment(write_index);
HAL_NVIC_SetPendingIRQ(COMP4_IRQn);
return true;
} else {
// already at limit
return false;
}
}
extern "C" {
void COMP4_IRQHandler() {
while(callbackFifoLevel() > 0) {
if (callbacks[read_index]) {
callbacks[read_index]();
}
increment(read_index);
}
}
}

7
Software/VNA_embedded/Application/Drivers/stm.hpp
View File

@ -7,6 +7,13 @@ extern ADC_HandleTypeDef hadc1;
namespace STM { namespace STM {
void Init();
// No FreeRTOS function calls are allowed from interrupts with higher priorities than 5.
// Certain parts of the data acquisition need higher priorities (so they don't get interrupted by FreeRTOS)
// but they also need to trigger FreeRTOS functions. This can be achieved by dispatching a function-pointer
// to a lower priority interrupt. The passed function can then handle the FreeRTOS function call
bool DispatchToInterrupt(void (*cb)(void));
static inline bool InInterrupt() { static inline bool InInterrupt() {
return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0; return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk) != 0;
} }

6
Software/VNA_embedded/Application/Hardware.cpp
View File

@ -48,7 +48,7 @@ static void ReadComplete(FPGA::SamplingResult result) {
break; break;
} }
if(needs_work && requestWork) { if(needs_work && requestWork) {
requestWork(); STM::DispatchToInterrupt(requestWork);
} }
} }
@ -120,8 +120,8 @@ bool HW::Init(WorkRequest wr) {
} }
// Set default ADC samplerate // Set default ADC samplerate
FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, 112); FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, 128);
FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, 1120); FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, 1280);
// Enable new data and sweep halt interrupt // Enable new data and sweep halt interrupt
FPGA::EnableInterrupt(FPGA::Interrupt::NewData); FPGA::EnableInterrupt(FPGA::Interrupt::NewData);

16
Software/VNA_embedded/Application/Hardware.hpp
View File

@ -5,12 +5,26 @@
namespace HW { namespace HW {
static constexpr uint32_t ADCSamplerate = 914000; static constexpr uint32_t ADCSamplerate = 800000;
static constexpr uint32_t IF1 = 60000000; static constexpr uint32_t IF1 = 60000000;
static constexpr uint32_t IF2 = 250000; static constexpr uint32_t IF2 = 250000;
static constexpr uint32_t LO1_minFreq = 25000000; static constexpr uint32_t LO1_minFreq = 25000000;
static constexpr uint32_t MaxSamples = 130944; static constexpr uint32_t MaxSamples = 130944;
static constexpr uint32_t MinSamples = 16;
static constexpr uint32_t PLLRef = 100000000; static constexpr uint32_t PLLRef = 100000000;
static constexpr uint16_t MaxPoints = 4501;
static constexpr Protocol::DeviceLimits Limits = {
.minFreq = 1000000,
.maxFreq = 6000000000,
.minIFBW = ADCSamplerate / MaxSamples,
.maxIFBW = ADCSamplerate / MinSamples,
.maxPoints = MaxPoints,
.cdbm_min = -4000,
.cdbm_max = -1000,
.minRBW = (uint32_t) (ADCSamplerate * 2.23f / MaxSamples),
.maxRBW = (uint32_t) (ADCSamplerate * 2.23f / MinSamples),
};
enum class Mode { enum class Mode {
Idle, Idle,

12
Software/VNA_embedded/Application/SpectrumAnalyzer.cpp
View File

@ -4,6 +4,8 @@
#include <complex.h> #include <complex.h>
#include <limits> #include <limits>
#include "Communication.h" #include "Communication.h"
#include "FreeRTOS.h"
#include "task.h"
#define LOG_LEVEL LOG_LEVEL_DEBUG #define LOG_LEVEL LOG_LEVEL_DEBUG
#define LOG_MODULE "SA" #define LOG_MODULE "SA"
@ -104,9 +106,10 @@ static void StartNextSample() {
void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) { void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
LOG_DEBUG("Setting up..."); LOG_DEBUG("Setting up...");
SA::Stop();
vTaskDelay(5);
s = settings; s = settings;
HW::SetMode(HW::Mode::SA); HW::SetMode(HW::Mode::SA);
FPGA::AbortSweep();
FPGA::SetMode(FPGA::Mode::FPGA); FPGA::SetMode(FPGA::Mode::FPGA);
// in almost all cases a full sweep requires more points than the FPGA can handle at a time // in almost all cases a full sweep requires more points than the FPGA can handle at a time
// individually start each point and do the sweep in the uC // individually start each point and do the sweep in the uC
@ -115,8 +118,10 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
// see https://www.tek.com/blog/window-functions-spectrum-analyzers for window factors // see https://www.tek.com/blog/window-functions-spectrum-analyzers for window factors
constexpr float window_factors[4] = {0.89f, 2.23f, 1.44f, 3.77f}; constexpr float window_factors[4] = {0.89f, 2.23f, 1.44f, 3.77f};
sampleNum = HW::ADCSamplerate * window_factors[s.WindowType] / s.RBW; sampleNum = HW::ADCSamplerate * window_factors[s.WindowType] / s.RBW;
// round up to next multiple of 128 // round up to next multiple of 16
sampleNum += 128 - sampleNum%128; if(sampleNum%16) {
sampleNum += 16 - sampleNum%16;
}
if(sampleNum >= HW::MaxSamples) { if(sampleNum >= HW::MaxSamples) {
sampleNum = HW::MaxSamples; sampleNum = HW::MaxSamples;
} }
@ -148,6 +153,7 @@ bool SA::MeasurementDone(FPGA::SamplingResult result) {
if(!active) { if(!active) {
return false; return false;
} }
FPGA::AbortSweep();
float port1 = abs(std::complex<float>(result.P1I, result.P1Q))/sampleNum; float port1 = abs(std::complex<float>(result.P1I, result.P1Q))/sampleNum;
float port2 = abs(std::complex<float>(result.P2I, result.P2Q))/sampleNum; float port2 = abs(std::complex<float>(result.P2I, result.P2Q))/sampleNum;
if(port1 < port1Measurement) { if(port1 < port1Measurement) {

30
Software/VNA_embedded/Application/VNA.cpp
View File

@ -9,6 +9,8 @@
#include "Exti.hpp" #include "Exti.hpp"
#include "Hardware.hpp" #include "Hardware.hpp"
#include "Communication.h" #include "Communication.h"
#include "FreeRTOS.h"
#include "task.h"
#define LOG_LEVEL LOG_LEVEL_INFO #define LOG_LEVEL LOG_LEVEL_INFO
#define LOG_MODULE "VNA" #define LOG_MODULE "VNA"
@ -35,6 +37,8 @@ static constexpr uint32_t BandSwitchFrequency = 25000000;
using namespace HWHAL; using namespace HWHAL;
bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) { bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
VNA::Stop();
vTaskDelay(5);
HW::SetMode(HW::Mode::VNA); HW::SetMode(HW::Mode::VNA);
if(s.excitePort1 == 0 && s.excitePort2 == 0) { if(s.excitePort1 == 0 && s.excitePort2 == 0) {
// both ports disabled, nothing to do // both ports disabled, nothing to do
@ -45,14 +49,15 @@ bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
sweepCallback = cb; sweepCallback = cb;
settings = s; settings = s;
// Abort possible active sweep first // Abort possible active sweep first
FPGA::AbortSweep();
FPGA::SetMode(FPGA::Mode::FPGA); FPGA::SetMode(FPGA::Mode::FPGA);
uint16_t points = settings.points <= FPGA::MaxPoints ? settings.points : FPGA::MaxPoints; uint16_t points = settings.points <= FPGA::MaxPoints ? settings.points : FPGA::MaxPoints;
// Configure sweep // Configure sweep
FPGA::SetNumberOfPoints(points); FPGA::SetNumberOfPoints(points);
uint32_t samplesPerPoint = (HW::ADCSamplerate / s.if_bandwidth); uint32_t samplesPerPoint = (HW::ADCSamplerate / s.if_bandwidth);
// round up to next multiple of 128 (128 samples are spread across 35 IF2 periods) // round up to next multiple of 16 (16 samples are spread across 5 IF2 periods)
samplesPerPoint = ((uint32_t) ((samplesPerPoint + 127) / 128)) * 128; if(samplesPerPoint%16) {
samplesPerPoint += 16 - samplesPerPoint%16;
}
uint32_t actualBandwidth = HW::ADCSamplerate / samplesPerPoint; uint32_t actualBandwidth = HW::ADCSamplerate / samplesPerPoint;
// has to be one less than actual number of samples // has to be one less than actual number of samples
FPGA::SetSamplesPerPoint(samplesPerPoint); FPGA::SetSamplesPerPoint(samplesPerPoint);
@ -76,10 +81,8 @@ bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
bool last_lowband = false; bool last_lowband = false;
if(!s.suppressPeaks) { // invalidate first entry of IFTable, preventing switing of 2.LO in halted callback
// invalidate first entry of IFTable, preventing switing of 2.LO in halted callback IFTable[0].pointCnt = 0xFFFF;
IFTable[0].pointCnt = 0xFFFF;
}
// Transfer PLL configuration to FPGA // Transfer PLL configuration to FPGA
for (uint16_t i = 0; i < points; i++) { for (uint16_t i = 0; i < points; i++) {
@ -122,7 +125,7 @@ bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
Si5351.SetCLK(SiChannel::RefLO2, last_LO2, Si5351.SetCLK(SiChannel::RefLO2, last_LO2,
Si5351C::PLL::B, Si5351C::DriveStrength::mA2); Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
// store calculated clock configuration for later change // store calculated clock configuration for later change
Si5351.ReadRawCLKConfig(1, IFTable[IFTableIndexCnt].clkconfig); Si5351.ReadRawCLKConfig(SiChannel::RefLO2, IFTable[IFTableIndexCnt].clkconfig);
IFTableIndexCnt++; IFTableIndexCnt++;
needs_LO2_shift = false; needs_LO2_shift = false;
} }
@ -165,6 +168,12 @@ bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
return true; return true;
} }
static void PassOnData() {
if (sweepCallback) {
sweepCallback(data);
}
}
bool VNA::MeasurementDone(FPGA::SamplingResult result) { bool VNA::MeasurementDone(FPGA::SamplingResult result) {
if(!active) { if(!active) {
return false; return false;
@ -200,9 +209,7 @@ bool VNA::MeasurementDone(FPGA::SamplingResult result) {
pointComplete = true; pointComplete = true;
} }
if(pointComplete) { if(pointComplete) {
if (sweepCallback) { STM::DispatchToInterrupt(PassOnData);
sweepCallback(data);
}
pointCnt++; pointCnt++;
if (pointCnt >= settings.points) { if (pointCnt >= settings.points) {
// reached end of sweep, start again // reached end of sweep, start again
@ -258,6 +265,7 @@ void VNA::SweepHalted() {
// First point in sweep, enable CLK // First point in sweep, enable CLK
Si5351.Enable(SiChannel::LowbandSource); Si5351.Enable(SiChannel::LowbandSource);
FPGA::Disable(FPGA::Periphery::SourceRF); FPGA::Disable(FPGA::Periphery::SourceRF);
Delay::us(1300);
} }
} else if(!FPGA::IsEnabled(FPGA::Periphery::SourceRF)){ } else if(!FPGA::IsEnabled(FPGA::Periphery::SourceRF)){
// first sweep point in highband is also halted, disable lowband source // first sweep point in highband is also halted, disable lowband source

48
Software/VNA_embedded/Src/main.c
View File

@ -189,18 +189,19 @@ void SystemClock_Config(void)
/** Configure the main internal regulator output voltage /** Configure the main internal regulator output voltage
*/ */
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1); HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
/** Initializes the CPU, AHB and APB busses clocks /** Initializes the CPU, AHB and APB busses clocks
*/ */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI|RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSIState = RCC_HSI_ON; RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV2; RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
RCC_OscInitStruct.PLL.PLLN = 36; RCC_OscInitStruct.PLL.PLLN = 80;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV6; RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV4;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2; RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{ {
@ -225,7 +226,7 @@ void SystemClock_Config(void)
|RCC_PERIPHCLK_USB|RCC_PERIPHCLK_ADC12; |RCC_PERIPHCLK_USB|RCC_PERIPHCLK_ADC12;
PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1; PeriphClkInit.Usart3ClockSelection = RCC_USART3CLKSOURCE_PCLK1;
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1; PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL; PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK; PeriphClkInit.Adc12ClockSelection = RCC_ADC12CLKSOURCE_SYSCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{ {
@ -314,7 +315,7 @@ static void MX_I2C2_Init(void)
/* USER CODE END I2C2_Init 1 */ /* USER CODE END I2C2_Init 1 */
hi2c2.Instance = I2C2; hi2c2.Instance = I2C2;
hi2c2.Init.Timing = 0x00E057FD; hi2c2.Init.Timing = 0x00F07BFF;
hi2c2.Init.OwnAddress1 = 0; hi2c2.Init.OwnAddress1 = 0;
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
@ -367,7 +368,7 @@ static void MX_SPI1_Init(void)
hspi1.Init.CLKPolarity = SPI_POLARITY_LOW; hspi1.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi1.Init.CLKPhase = SPI_PHASE_1EDGE; hspi1.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi1.Init.NSS = SPI_NSS_SOFT; hspi1.Init.NSS = SPI_NSS_SOFT;
hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; hspi1.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB; hspi1.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi1.Init.TIMode = SPI_TIMODE_DISABLE; hspi1.Init.TIMode = SPI_TIMODE_DISABLE;
hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; hspi1.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@ -407,7 +408,7 @@ static void MX_SPI2_Init(void)
hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; hspi2.Init.CLKPolarity = SPI_POLARITY_LOW;
hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; hspi2.Init.CLKPhase = SPI_PHASE_1EDGE;
hspi2.Init.NSS = SPI_NSS_SOFT; hspi2.Init.NSS = SPI_NSS_SOFT;
hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_16; hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_4;
hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB;
hspi2.Init.TIMode = SPI_TIMODE_DISABLE; hspi2.Init.TIMode = SPI_TIMODE_DISABLE;
hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
@ -444,7 +445,7 @@ static void MX_TIM1_Init(void)
/* USER CODE END TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1; htim1.Instance = TIM1;
htim1.Init.Prescaler = 143; htim1.Init.Prescaler = 159;
htim1.Init.CounterMode = TIM_COUNTERMODE_UP; htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
htim1.Init.Period = 65535; htim1.Init.Period = 65535;
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
@ -589,7 +590,7 @@ static void MX_UCPD1_Init(void)
LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MDATAALIGN_BYTE); LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MDATAALIGN_BYTE);
/* UCPD1 interrupt Init */ /* UCPD1 interrupt Init */
NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),6, 0)); NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),7, 0));
NVIC_EnableIRQ(UCPD1_IRQn); NVIC_EnableIRQ(UCPD1_IRQn);
/* USER CODE BEGIN UCPD1_Init 1 */ /* USER CODE BEGIN UCPD1_Init 1 */
@ -693,16 +694,16 @@ static void MX_DMA_Init(void)
/* DMA interrupt init */ /* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */ /* DMA1_Channel1_IRQn interrupt configuration */
NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),6, 0)); NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),7, 0));
NVIC_EnableIRQ(DMA1_Channel1_IRQn); NVIC_EnableIRQ(DMA1_Channel1_IRQn);
/* DMA1_Channel2_IRQn interrupt configuration */ /* DMA1_Channel2_IRQn interrupt configuration */
NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),6, 0)); NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),7, 0));
NVIC_EnableIRQ(DMA1_Channel2_IRQn); NVIC_EnableIRQ(DMA1_Channel2_IRQn);
/* DMA1_Channel3_IRQn interrupt configuration */ /* DMA1_Channel3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 6, 0); HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn); HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
/* DMA1_Channel4_IRQn interrupt configuration */ /* DMA1_Channel4_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 6, 0); HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 2, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn); HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
} }
@ -744,15 +745,15 @@ static void MX_GPIO_Init(void)
GPIO_InitStruct.Pin = FPGA_AUX1_Pin|FPGA_AUX3_Pin|FPGA_AUX2_Pin|FPGA_CS_Pin; GPIO_InitStruct.Pin = FPGA_AUX1_Pin|FPGA_AUX3_Pin|FPGA_AUX2_Pin|FPGA_CS_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pins : FLASH_CS_Pin FPGA_PROGRAM_B_Pin EN_6V_Pin FPGA_RESET_Pin */ /*Configure GPIO pin : FLASH_CS_Pin */
GPIO_InitStruct.Pin = FLASH_CS_Pin|FPGA_PROGRAM_B_Pin|EN_6V_Pin|FPGA_RESET_Pin; GPIO_InitStruct.Pin = FLASH_CS_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(FLASH_CS_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pin : FPGA_INTR_Pin */ /*Configure GPIO pin : FPGA_INTR_Pin */
GPIO_InitStruct.Pin = FPGA_INTR_Pin; GPIO_InitStruct.Pin = FPGA_INTR_Pin;
@ -760,6 +761,13 @@ static void MX_GPIO_Init(void)
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(FPGA_INTR_GPIO_Port, &GPIO_InitStruct); HAL_GPIO_Init(FPGA_INTR_GPIO_Port, &GPIO_InitStruct);
/*Configure GPIO pins : FPGA_PROGRAM_B_Pin EN_6V_Pin FPGA_RESET_Pin */
GPIO_InitStruct.Pin = FPGA_PROGRAM_B_Pin|EN_6V_Pin|FPGA_RESET_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pin : FPGA_DONE_Pin */ /*Configure GPIO pin : FPGA_DONE_Pin */
GPIO_InitStruct.Pin = FPGA_DONE_Pin; GPIO_InitStruct.Pin = FPGA_DONE_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT; GPIO_InitStruct.Mode = GPIO_MODE_INPUT;

8
Software/VNA_embedded/Src/stm32g4xx_hal_msp.c
View File

@ -229,7 +229,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7; GPIO_InitStruct.Pin = GPIO_PIN_5|GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI1; GPIO_InitStruct.Alternate = GPIO_AF5_SPI1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
@ -243,7 +243,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_spi1_rx.Init.Mode = DMA_NORMAL; hdma_spi1_rx.Init.Mode = DMA_NORMAL;
hdma_spi1_rx.Init.Priority = DMA_PRIORITY_LOW; hdma_spi1_rx.Init.Priority = DMA_PRIORITY_VERY_HIGH;
if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK) if (HAL_DMA_Init(&hdma_spi1_rx) != HAL_OK)
{ {
Error_Handler(); Error_Handler();
@ -260,7 +260,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
hdma_spi1_tx.Init.Mode = DMA_NORMAL; hdma_spi1_tx.Init.Mode = DMA_NORMAL;
hdma_spi1_tx.Init.Priority = DMA_PRIORITY_LOW; hdma_spi1_tx.Init.Priority = DMA_PRIORITY_VERY_HIGH;
if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK) if (HAL_DMA_Init(&hdma_spi1_tx) != HAL_OK)
{ {
Error_Handler(); Error_Handler();
@ -288,7 +288,7 @@ void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi)
GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15; GPIO_InitStruct.Pin = GPIO_PIN_13|GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; GPIO_InitStruct.Alternate = GPIO_AF5_SPI2;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);

118
Software/VNA_embedded/VNA_embedded.ioc
View File

@ -20,7 +20,7 @@ Dma.SPI1_RX.2.Mode=DMA_NORMAL
Dma.SPI1_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.SPI1_RX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_RX.2.PeriphInc=DMA_PINC_DISABLE Dma.SPI1_RX.2.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_RX.2.Polarity=HAL_DMAMUX_REQ_GEN_RISING Dma.SPI1_RX.2.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.SPI1_RX.2.Priority=DMA_PRIORITY_LOW Dma.SPI1_RX.2.Priority=DMA_PRIORITY_VERY_HIGH
Dma.SPI1_RX.2.RequestNumber=1 Dma.SPI1_RX.2.RequestNumber=1
Dma.SPI1_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber Dma.SPI1_RX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.SPI1_RX.2.SignalID=NONE Dma.SPI1_RX.2.SignalID=NONE
@ -37,7 +37,7 @@ Dma.SPI1_TX.3.Mode=DMA_NORMAL
Dma.SPI1_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.SPI1_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_TX.3.PeriphInc=DMA_PINC_DISABLE Dma.SPI1_TX.3.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_TX.3.Polarity=HAL_DMAMUX_REQ_GEN_RISING Dma.SPI1_TX.3.Polarity=HAL_DMAMUX_REQ_GEN_RISING
Dma.SPI1_TX.3.Priority=DMA_PRIORITY_LOW Dma.SPI1_TX.3.Priority=DMA_PRIORITY_VERY_HIGH
Dma.SPI1_TX.3.RequestNumber=1 Dma.SPI1_TX.3.RequestNumber=1
Dma.SPI1_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber Dma.SPI1_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber
Dma.SPI1_TX.3.SignalID=NONE Dma.SPI1_TX.3.SignalID=NONE
@ -94,7 +94,7 @@ FREERTOS.configUSE_MUTEXES=1
File.Version=6 File.Version=6
I2C2.I2C_Speed_Mode=I2C_Fast I2C2.I2C_Speed_Mode=I2C_Fast
I2C2.IPParameters=Timing,I2C_Speed_Mode I2C2.IPParameters=Timing,I2C_Speed_Mode
I2C2.Timing=0x00E057FD I2C2.Timing=0x00F07BFF
KeepUserPlacement=false KeepUserPlacement=false
Mcu.Family=STM32G4 Mcu.Family=STM32G4
Mcu.IP0=ADC1 Mcu.IP0=ADC1
@ -158,10 +158,10 @@ Mcu.UserName=STM32G431CBUx
MxCube.Version=5.2.1 MxCube.Version=5.2.1
MxDb.Version=DB.5.0.21 MxDb.Version=DB.5.0.21
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DMA1_Channel1_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true NVIC.DMA1_Channel1_IRQn=true\:7\:0\:true\:false\:true\:true\:false\:true
NVIC.DMA1_Channel2_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true NVIC.DMA1_Channel2_IRQn=true\:7\:0\:true\:false\:true\:true\:false\:true
NVIC.DMA1_Channel3_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true NVIC.DMA1_Channel3_IRQn=true\:2\:0\:true\:false\:true\:false\:false\:true
NVIC.DMA1_Channel4_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true NVIC.DMA1_Channel4_IRQn=true\:2\:0\:true\:false\:true\:false\:false\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
@ -173,10 +173,11 @@ NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true
NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn
NVIC.TimeBaseIP=TIM17 NVIC.TimeBaseIP=TIM17
NVIC.UCPD1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:false NVIC.UCPD1_IRQn=true\:7\:0\:true\:false\:true\:true\:true\:false
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA1.GPIOParameters=GPIO_Label PA1.GPIOParameters=GPIO_Speed,GPIO_Label
PA1.GPIO_Label=FPGA_AUX1 PA1.GPIO_Label=FPGA_AUX1
PA1.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PA1.Locked=true PA1.Locked=true
PA1.Signal=GPIO_Output PA1.Signal=GPIO_Output
PA10.Locked=true PA10.Locked=true
@ -196,25 +197,34 @@ PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK PA14.Signal=SYS_JTCK-SWCLK
PA15.Locked=true PA15.Locked=true
PA15.Signal=S_TIM2_CH1 PA15.Signal=S_TIM2_CH1
PA2.GPIOParameters=GPIO_Label PA2.GPIOParameters=GPIO_Speed,GPIO_Label
PA2.GPIO_Label=FPGA_AUX3 PA2.GPIO_Label=FPGA_AUX3
PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PA2.Locked=true PA2.Locked=true
PA2.Signal=GPIO_Output PA2.Signal=GPIO_Output
PA3.GPIOParameters=GPIO_Label PA3.GPIOParameters=GPIO_Speed,GPIO_Label
PA3.GPIO_Label=FPGA_AUX2 PA3.GPIO_Label=FPGA_AUX2
PA3.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PA3.Locked=true PA3.Locked=true
PA3.Signal=GPIO_Output PA3.Signal=GPIO_Output
PA4.GPIOParameters=PinState,GPIO_Label PA4.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
PA4.GPIO_Label=FPGA_CS PA4.GPIO_Label=FPGA_CS
PA4.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PA4.Locked=true PA4.Locked=true
PA4.PinState=GPIO_PIN_SET PA4.PinState=GPIO_PIN_SET
PA4.Signal=GPIO_Output PA4.Signal=GPIO_Output
PA5.GPIOParameters=GPIO_Speed
PA5.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PA5.Locked=true PA5.Locked=true
PA5.Mode=Full_Duplex_Master PA5.Mode=Full_Duplex_Master
PA5.Signal=SPI1_SCK PA5.Signal=SPI1_SCK
PA6.GPIOParameters=GPIO_Speed
PA6.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PA6.Locked=true PA6.Locked=true
PA6.Mode=Full_Duplex_Master PA6.Mode=Full_Duplex_Master
PA6.Signal=SPI1_MISO PA6.Signal=SPI1_MISO
PA7.GPIOParameters=GPIO_Speed
PA7.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PA7.Locked=true PA7.Locked=true
PA7.Mode=Full_Duplex_Master PA7.Mode=Full_Duplex_Master
PA7.Signal=SPI1_MOSI PA7.Signal=SPI1_MOSI
@ -224,8 +234,9 @@ PA8.Signal=I2C2_SDA
PA9.Locked=true PA9.Locked=true
PA9.Mode=EnableDeadBattery PA9.Mode=EnableDeadBattery
PA9.Signal=UCPD1_DBCC1 PA9.Signal=UCPD1_DBCC1
PB0.GPIOParameters=PinState,GPIO_Label PB0.GPIOParameters=GPIO_Speed,PinState,GPIO_Label
PB0.GPIO_Label=FLASH_CS PB0.GPIO_Label=FLASH_CS
PB0.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PB0.Locked=true PB0.Locked=true
PB0.PinState=GPIO_PIN_SET PB0.PinState=GPIO_PIN_SET
PB0.Signal=GPIO_Output PB0.Signal=GPIO_Output
@ -239,9 +250,13 @@ PB12.GPIOParameters=GPIO_Label
PB12.GPIO_Label=EN_6V PB12.GPIO_Label=EN_6V
PB12.Locked=true PB12.Locked=true
PB12.Signal=GPIO_Output PB12.Signal=GPIO_Output
PB13.GPIOParameters=GPIO_Speed
PB13.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PB13.Locked=true PB13.Locked=true
PB13.Mode=TX_Only_Simplex_Unidirect_Master PB13.Mode=TX_Only_Simplex_Unidirect_Master
PB13.Signal=SPI2_SCK PB13.Signal=SPI2_SCK
PB15.GPIOParameters=GPIO_Speed
PB15.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
PB15.Locked=true PB15.Locked=true
PB15.Mode=TX_Only_Simplex_Unidirect_Master PB15.Mode=TX_Only_Simplex_Unidirect_Master
PB15.Signal=SPI2_MOSI PB15.Signal=SPI2_MOSI
@ -308,65 +323,66 @@ ProjectManager.StackSize=0x400
ProjectManager.TargetToolchain=SW4STM32 ProjectManager.TargetToolchain=SW4STM32
ProjectManager.ToolChainLocation= ProjectManager.ToolChainLocation=
ProjectManager.UnderRoot=true ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_I2C2_Init-I2C2-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_UCPD1_Init-UCPD1-false-LL-true,8-MX_USART3_UART_Init-USART3-false-HAL-true,9-MX_USB_PCD_Init-USB-false-HAL-true,10-MX_USBPD_Init-USBPD-false-HAL-true,11-MX_TIM1_Init-TIM1-false-HAL-true,12-MX_TIM2_Init-TIM2-false-HAL-true ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_I2C2_Init-I2C2-false-HAL-true,5-MX_SPI1_Init-SPI1-false-HAL-true,6-MX_SPI2_Init-SPI2-false-HAL-true,7-MX_UCPD1_Init-UCPD1-false-LL-true,8-MX_USART3_UART_Init-USART3-false-HAL-true,9-MX_USB_PCD_Init-USB-false-HAL-true,10-MX_USBPD_Init-USBPD-false-HAL-true,11-MX_TIM1_Init-TIM1-false-HAL-true,12-MX_TIM2_Init-TIM2-false-HAL-true,13-MX_ADC1_Init-ADC1-false-HAL-true
RCC.ADC12Freq_Value=144000000 RCC.ADC12Freq_Value=160000000
RCC.AHBFreq_Value=144000000 RCC.AHBFreq_Value=160000000
RCC.APB1Freq_Value=144000000 RCC.APB1Freq_Value=160000000
RCC.APB1TimFreq_Value=144000000 RCC.APB1TimFreq_Value=160000000
RCC.APB2Freq_Value=144000000 RCC.APB2Freq_Value=160000000
RCC.APB2TimFreq_Value=144000000 RCC.APB2TimFreq_Value=160000000
RCC.CK48CLockSelection=RCC_USBCLKSOURCE_HSI48
RCC.CRSFreq_Value=48000000 RCC.CRSFreq_Value=48000000
RCC.CortexFreq_Value=144000000 RCC.CortexFreq_Value=160000000
RCC.EXTERNAL_CLOCK_VALUE=12288000 RCC.EXTERNAL_CLOCK_VALUE=12288000
RCC.FCLKCortexFreq_Value=144000000 RCC.FCLKCortexFreq_Value=160000000
RCC.FDCANFreq_Value=144000000 RCC.FDCANFreq_Value=160000000
RCC.FamilyName=M RCC.FamilyName=M
RCC.HCLKFreq_Value=144000000 RCC.HCLKFreq_Value=160000000
RCC.HSE_VALUE=8000000 RCC.HSE_VALUE=8000000
RCC.HSI48_VALUE=48000000 RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000 RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=144000000 RCC.I2C1Freq_Value=160000000
RCC.I2C2Freq_Value=144000000 RCC.I2C2Freq_Value=160000000
RCC.I2C3Freq_Value=144000000 RCC.I2C3Freq_Value=160000000
RCC.I2SFreq_Value=144000000 RCC.I2SFreq_Value=160000000
RCC.IPParameters=ADC12Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value RCC.IPParameters=ADC12Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CK48CLockSelection,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQ,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PWRFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
RCC.LPTIM1Freq_Value=144000000 RCC.LPTIM1Freq_Value=160000000
RCC.LPUART1Freq_Value=144000000 RCC.LPUART1Freq_Value=160000000
RCC.LSCOPinFreq_Value=32000 RCC.LSCOPinFreq_Value=32000
RCC.LSE_VALUE=32768 RCC.LSE_VALUE=32768
RCC.LSI_VALUE=32000 RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=16000000 RCC.MCO1PinFreq_Value=16000000
RCC.PLLM=RCC_PLLM_DIV2 RCC.PLLM=RCC_PLLM_DIV4
RCC.PLLN=36 RCC.PLLN=80
RCC.PLLPoutputFreq_Value=144000000 RCC.PLLPoutputFreq_Value=160000000
RCC.PLLQ=RCC_PLLQ_DIV6 RCC.PLLQ=RCC_PLLQ_DIV4
RCC.PLLQoutputFreq_Value=48000000 RCC.PLLQoutputFreq_Value=80000000
RCC.PLLRCLKFreq_Value=144000000 RCC.PLLRCLKFreq_Value=160000000
RCC.PWRFreq_Value=144000000 RCC.PWRFreq_Value=160000000
RCC.RNGFreq_Value=48000000 RCC.RNGFreq_Value=48000000
RCC.SAI1Freq_Value=144000000 RCC.SAI1Freq_Value=160000000
RCC.SYSCLKFreq_VALUE=144000000 RCC.SYSCLKFreq_VALUE=160000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.UART4Freq_Value=144000000 RCC.UART4Freq_Value=160000000
RCC.USART1Freq_Value=144000000 RCC.USART1Freq_Value=160000000
RCC.USART2Freq_Value=144000000 RCC.USART2Freq_Value=160000000
RCC.USART3Freq_Value=144000000 RCC.USART3Freq_Value=160000000
RCC.USBFreq_Value=48000000 RCC.USBFreq_Value=48000000
RCC.VCOInputFreq_Value=8000000 RCC.VCOInputFreq_Value=4000000
RCC.VCOOutputFreq_Value=288000000 RCC.VCOOutputFreq_Value=320000000
SH.GPXTI1.0=GPIO_EXTI1 SH.GPXTI1.0=GPIO_EXTI1
SH.GPXTI1.ConfNb=1 SH.GPXTI1.ConfNb=1
SH.S_TIM2_CH1.0=TIM2_CH1,PWM Generation1 CH1 SH.S_TIM2_CH1.0=TIM2_CH1,PWM Generation1 CH1
SH.S_TIM2_CH1.ConfNb=1 SH.S_TIM2_CH1.ConfNb=1
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
SPI1.CalculateBaudRate=9.0 MBits/s SPI1.CalculateBaudRate=40.0 MBits/s
SPI1.DataSize=SPI_DATASIZE_8BIT SPI1.DataSize=SPI_DATASIZE_8BIT
SPI1.Direction=SPI_DIRECTION_2LINES SPI1.Direction=SPI_DIRECTION_2LINES
SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize SPI1.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize
SPI1.Mode=SPI_MODE_MASTER SPI1.Mode=SPI_MODE_MASTER
SPI1.VirtualType=VM_MASTER SPI1.VirtualType=VM_MASTER
SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_16 SPI2.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
SPI2.CalculateBaudRate=9.0 MBits/s SPI2.CalculateBaudRate=40.0 MBits/s
SPI2.DataSize=SPI_DATASIZE_8BIT SPI2.DataSize=SPI_DATASIZE_8BIT
SPI2.Direction=SPI_DIRECTION_2LINES SPI2.Direction=SPI_DIRECTION_2LINES
SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,BaudRatePrescaler,DataSize
@ -374,7 +390,7 @@ SPI2.Mode=SPI_MODE_MASTER
SPI2.VirtualType=VM_MASTER SPI2.VirtualType=VM_MASTER
TIM1.IPParameters=Prescaler,PeriodNoDither TIM1.IPParameters=Prescaler,PeriodNoDither
TIM1.PeriodNoDither=65535 TIM1.PeriodNoDither=65535
TIM1.Prescaler=143 TIM1.Prescaler=159
TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
TIM2.IPParameters=Channel-PWM Generation1 CH1,Prescaler,PeriodNoDither,OCMode_PWM-PWM Generation1 CH1 TIM2.IPParameters=Channel-PWM Generation1 CH1,Prescaler,PeriodNoDither,OCMode_PWM-PWM Generation1 CH1
TIM2.OCMode_PWM-PWM\ Generation1\ CH1=TIM_OCMODE_PWM2 TIM2.OCMode_PWM-PWM\ Generation1\ CH1=TIM_OCMODE_PWM2