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Possible reference output frequency fix?

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This commit is contained in:
Jan Käberich 2021-06-02 18:47:03 +02:00
parent 41b93daa87
commit a3d730e729
2 changed files with 27 additions and 10 deletions
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20
Software/VNA_embedded/Application/Hardware.cpp
View File

@ -92,10 +92,10 @@ bool HW::Init() {
Si5351.Init(); Si5351.Init();
// Use Si5351 to generate reference frequencies for other PLLs and ADC // Use Si5351 to generate reference frequencies for other PLLs and ADC
Si5351.SetPLL(Si5351C::PLL::A, 832000000, Si5351C::PLLSource::XTAL); Si5351.SetPLL(Si5351C::PLL::A, HW::SI5351CPLLConstantFrequency, Si5351C::PLLSource::XTAL);
while(!Si5351.Locked(Si5351C::PLL::A)); while(!Si5351.Locked(Si5351C::PLL::A));
Si5351.SetPLL(Si5351C::PLL::B, 832000000, Si5351C::PLLSource::XTAL); Si5351.SetPLL(Si5351C::PLL::B, HW::SI5351CPLLAlignedFrequency, Si5351C::PLLSource::XTAL);
while(!Si5351.Locked(Si5351C::PLL::B)); while(!Si5351.Locked(Si5351C::PLL::B));
extRefInUse = 0; extRefInUse = 0;
@ -104,13 +104,13 @@ bool HW::Init() {
// Both MAX2871 get a 100MHz reference // Both MAX2871 get a 100MHz reference
// Si5351.SetBypass(SiChannel::Source, Si5351C::PLLSource::XTAL); // Si5351.SetBypass(SiChannel::Source, Si5351C::PLLSource::XTAL);
Si5351.SetCLK(SiChannel::Source, HW::PLLRef, Si5351C::PLL::A, Si5351C::DriveStrength::mA2); Si5351.SetCLK(SiChannel::Source, HW::PLLRef, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
Si5351.Enable(SiChannel::Source); Si5351.Enable(SiChannel::Source);
// Si5351.SetBypass(SiChannel::LO1, Si5351C::PLLSource::XTAL); // Si5351.SetBypass(SiChannel::LO1, Si5351C::PLLSource::XTAL);
Si5351.SetCLK(SiChannel::LO1, HW::PLLRef, Si5351C::PLL::A, Si5351C::DriveStrength::mA2); Si5351.SetCLK(SiChannel::LO1, HW::PLLRef, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
Si5351.Enable(SiChannel::LO1); Si5351.Enable(SiChannel::LO1);
// 16MHz FPGA clock // 16MHz FPGA clock
Si5351.SetCLK(SiChannel::FPGA, 16000000, Si5351C::PLL::A, Si5351C::DriveStrength::mA2); Si5351.SetCLK(SiChannel::FPGA, HW::FPGAClkInFrequency, Si5351C::PLL::A, Si5351C::DriveStrength::mA2);
Si5351.Enable(SiChannel::FPGA); Si5351.Enable(SiChannel::FPGA);
// Generate second LO with Si5351 // Generate second LO with Si5351
@ -364,18 +364,18 @@ void HW::Ref::update() {
LOG_WARN("Forced switch to external reference but no signal detected"); LOG_WARN("Forced switch to external reference but no signal detected");
} }
Si5351.ConfigureCLKIn(10000000); Si5351.ConfigureCLKIn(10000000);
Si5351.SetPLL(Si5351C::PLL::A, 832000000, Si5351C::PLLSource::CLKIN); Si5351.SetPLL(Si5351C::PLL::A, HW::SI5351CPLLConstantFrequency, Si5351C::PLLSource::CLKIN);
Si5351.SetPLL(Si5351C::PLL::B, 832000000, Si5351C::PLLSource::CLKIN); Si5351.SetPLL(Si5351C::PLL::B, HW::SI5351CPLLAlignedFrequency, Si5351C::PLLSource::CLKIN);
LOG_INFO("Switched to external reference"); LOG_INFO("Switched to external reference");
FPGA::Enable(FPGA::Periphery::ExtRefLED); FPGA::Enable(FPGA::Periphery::ExtRefLED);
} else { } else {
Si5351.SetPLL(Si5351C::PLL::A, 832000000, Si5351C::PLLSource::XTAL); Si5351.SetPLL(Si5351C::PLL::A, HW::SI5351CPLLConstantFrequency, Si5351C::PLLSource::XTAL);
Si5351.SetPLL(Si5351C::PLL::B, 832000000, Si5351C::PLLSource::XTAL); Si5351.SetPLL(Si5351C::PLL::B, HW::SI5351CPLLAlignedFrequency, Si5351C::PLLSource::XTAL);
LOG_INFO("Switched to internal reference"); LOG_INFO("Switched to internal reference");
FPGA::Disable(FPGA::Periphery::ExtRefLED); FPGA::Disable(FPGA::Periphery::ExtRefLED);
} }
} }
constexpr uint32_t lock_timeout = 10; constexpr uint32_t lock_timeout = 100;
uint32_t start = HAL_GetTick(); uint32_t start = HAL_GetTick();
while(!Si5351.Locked(Si5351C::PLL::A) || !Si5351.Locked(Si5351C::PLL::A)) { while(!Si5351.Locked(Si5351C::PLL::A) || !Si5351.Locked(Si5351C::PLL::A)) {
if(HAL_GetTick() - start > lock_timeout) { if(HAL_GetTick() - start > lock_timeout) {

17
Software/VNA_embedded/Application/Hardware.hpp
View File

@ -28,6 +28,13 @@
namespace HW { namespace HW {
static constexpr uint32_t TCXOFrequency = 26000000;
static constexpr uint32_t ExtRefInFrequency = 10000000;
static constexpr uint32_t ExtRefOut1Frequency = 10000000;
static constexpr uint32_t ExtRefOut2Frequency = 10000000;
static constexpr uint32_t SI5351CPLLAlignedFrequency = 832000000;
static constexpr uint32_t SI5351CPLLConstantFrequency = 800000000;
static constexpr uint32_t FPGAClkInFrequency = 16000000;
static constexpr uint32_t ADCSamplerate = 800000; static constexpr uint32_t ADCSamplerate = 800000;
static constexpr uint32_t IF1 = 62000000; static constexpr uint32_t IF1 = 62000000;
static constexpr uint32_t IF2 = 250000; static constexpr uint32_t IF2 = 250000;
@ -42,6 +49,16 @@ static_assert(ADCprescaler * ADCSamplerate == FPGA::Clockrate, "ADCSamplerate ca
static constexpr uint16_t DFTphaseInc = 4096 * IF2 / ADCSamplerate; static constexpr uint16_t DFTphaseInc = 4096 * IF2 / ADCSamplerate;
static_assert(DFTphaseInc * ADCSamplerate == 4096 * IF2, "DFT can not be computed for 2.IF"); static_assert(DFTphaseInc * ADCSamplerate == 4096 * IF2, "DFT can not be computed for 2.IF");
static constexpr uint16_t _fpga_div = SI5351CPLLConstantFrequency / FPGAClkInFrequency;
static_assert(_fpga_div * FPGAClkInFrequency == SI5351CPLLConstantFrequency && _fpga_div >= 6 && _fpga_div <= 254 && (_fpga_div & 0x01) == 0, "Unable to generate FPGA clock input frequency");
static constexpr uint16_t _ref_out1_div = SI5351CPLLConstantFrequency / ExtRefOut1Frequency;
static_assert(_ref_out1_div * ExtRefOut1Frequency == SI5351CPLLConstantFrequency && _ref_out1_div >= 6 && _ref_out1_div <= 254 && (_ref_out1_div & 0x01) == 0, "Unable to generate first reference output frequency");
static constexpr uint16_t _ref_out2_div = SI5351CPLLConstantFrequency / ExtRefOut2Frequency;
static_assert(_ref_out2_div * ExtRefOut2Frequency == SI5351CPLLConstantFrequency && _ref_out2_div >= 6 && _ref_out2_div <= 254 && (_ref_out2_div & 0x01) == 0, "Unable to generate first reference output frequency");
// approximate output power at low frequencies with different source strength settings (attenuator = 0) in cdbm // approximate output power at low frequencies with different source strength settings (attenuator = 0) in cdbm
static constexpr int16_t LowBandMinPower = -1350; static constexpr int16_t LowBandMinPower = -1350;
static constexpr int16_t LowBandMaxPower = -190; static constexpr int16_t LowBandMaxPower = -190;