diff --git a/FPGA/.gitignore b/FPGA/.gitignore
index c853aaf..b8f80c0 100644
--- a/FPGA/.gitignore
+++ b/FPGA/.gitignore
@@ -4,7 +4,6 @@
!*.vhd
!*.ucf
!*.ipf
-*/ipcore_dir
!*.gise
!*.xise
!*.py
diff --git a/FPGA/VNA/ipcore_dir/.gitignore b/FPGA/VNA/ipcore_dir/.gitignore
new file mode 100644
index 0000000..68f8144
--- /dev/null
+++ b/FPGA/VNA/ipcore_dir/.gitignore
@@ -0,0 +1,6 @@
+*
+*/*
+!.gitignore
+!*.xco
+!*.xise
+
diff --git a/FPGA/VNA/ipcore_dir/PLL.xco b/FPGA/VNA/ipcore_dir/PLL.xco
new file mode 100644
index 0000000..709503d
--- /dev/null
+++ b/FPGA/VNA/ipcore_dir/PLL.xco
@@ -0,0 +1,269 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Thu May 14 06:56:00 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:clk_wiz:3.6
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Clocking_Wizard xilinx.com:ip:clk_wiz:3.6
+# END Select
+# BEGIN Parameters
+CSET calc_done=DONE
+CSET clk_in_sel_port=CLK_IN_SEL
+CSET clk_out1_port=CLK_OUT1
+CSET clk_out1_use_fine_ps_gui=false
+CSET clk_out2_port=CLK_OUT2
+CSET clk_out2_use_fine_ps_gui=false
+CSET clk_out3_port=CLK_OUT3
+CSET clk_out3_use_fine_ps_gui=false
+CSET clk_out4_port=CLK_OUT4
+CSET clk_out4_use_fine_ps_gui=false
+CSET clk_out5_port=CLK_OUT5
+CSET clk_out5_use_fine_ps_gui=false
+CSET clk_out6_port=CLK_OUT6
+CSET clk_out6_use_fine_ps_gui=false
+CSET clk_out7_port=CLK_OUT7
+CSET clk_out7_use_fine_ps_gui=false
+CSET clk_valid_port=CLK_VALID
+CSET clkfb_in_n_port=CLKFB_IN_N
+CSET clkfb_in_p_port=CLKFB_IN_P
+CSET clkfb_in_port=CLKFB_IN
+CSET clkfb_in_signaling=SINGLE
+CSET clkfb_out_n_port=CLKFB_OUT_N
+CSET clkfb_out_p_port=CLKFB_OUT_P
+CSET clkfb_out_port=CLKFB_OUT
+CSET clkfb_stopped_port=CLKFB_STOPPED
+CSET clkin1_jitter_ps=625.0
+CSET clkin1_ui_jitter=0.010
+CSET clkin2_jitter_ps=100.0
+CSET clkin2_ui_jitter=0.010
+CSET clkout1_drives=BUFG
+CSET clkout1_requested_duty_cycle=50.000
+CSET clkout1_requested_out_freq=102.4
+CSET clkout1_requested_phase=0.000
+CSET clkout2_drives=BUFG
+CSET clkout2_requested_duty_cycle=50.000
+CSET clkout2_requested_out_freq=100.000
+CSET clkout2_requested_phase=0.000
+CSET clkout2_used=false
+CSET clkout3_drives=BUFG
+CSET clkout3_requested_duty_cycle=50.000
+CSET clkout3_requested_out_freq=100.000
+CSET clkout3_requested_phase=0.000
+CSET clkout3_used=false
+CSET clkout4_drives=BUFG
+CSET clkout4_requested_duty_cycle=50.000
+CSET clkout4_requested_out_freq=100.000
+CSET clkout4_requested_phase=0.000
+CSET clkout4_used=false
+CSET clkout5_drives=BUFG
+CSET clkout5_requested_duty_cycle=50.000
+CSET clkout5_requested_out_freq=100.000
+CSET clkout5_requested_phase=0.000
+CSET clkout5_used=false
+CSET clkout6_drives=BUFG
+CSET clkout6_requested_duty_cycle=50.000
+CSET clkout6_requested_out_freq=100.000
+CSET clkout6_requested_phase=0.000
+CSET clkout6_used=false
+CSET clkout7_drives=BUFG
+CSET clkout7_requested_duty_cycle=50.000
+CSET clkout7_requested_out_freq=100.000
+CSET clkout7_requested_phase=0.000
+CSET clkout7_used=false
+CSET clock_mgr_type=AUTO
+CSET component_name=PLL
+CSET daddr_port=DADDR
+CSET dclk_port=DCLK
+CSET dcm_clk_feedback=1X
+CSET dcm_clk_out1_port=CLKFX
+CSET dcm_clk_out2_port=CLK0
+CSET dcm_clk_out3_port=CLK0
+CSET dcm_clk_out4_port=CLK0
+CSET dcm_clk_out5_port=CLK0
+CSET dcm_clk_out6_port=CLK0
+CSET dcm_clkdv_divide=2.0
+CSET dcm_clkfx_divide=5
+CSET dcm_clkfx_multiply=32
+CSET dcm_clkgen_clk_out1_port=CLKFX
+CSET dcm_clkgen_clk_out2_port=CLKFX
+CSET dcm_clkgen_clk_out3_port=CLKFX
+CSET dcm_clkgen_clkfx_divide=1
+CSET dcm_clkgen_clkfx_md_max=0.000
+CSET dcm_clkgen_clkfx_multiply=4
+CSET dcm_clkgen_clkfxdv_divide=2
+CSET dcm_clkgen_clkin_period=10.000
+CSET dcm_clkgen_notes=None
+CSET dcm_clkgen_spread_spectrum=NONE
+CSET dcm_clkgen_startup_wait=false
+CSET dcm_clkin_divide_by_2=false
+CSET dcm_clkin_period=62.500
+CSET dcm_clkout_phase_shift=NONE
+CSET dcm_deskew_adjust=SYSTEM_SYNCHRONOUS
+CSET dcm_notes=None
+CSET dcm_phase_shift=0
+CSET dcm_pll_cascade=NONE
+CSET dcm_startup_wait=false
+CSET den_port=DEN
+CSET din_port=DIN
+CSET dout_port=DOUT
+CSET drdy_port=DRDY
+CSET dwe_port=DWE
+CSET feedback_source=FDBK_AUTO
+CSET in_freq_units=Units_MHz
+CSET in_jitter_units=Units_UI
+CSET input_clk_stopped_port=INPUT_CLK_STOPPED
+CSET jitter_options=UI
+CSET jitter_sel=No_Jitter
+CSET locked_port=LOCKED
+CSET mmcm_bandwidth=OPTIMIZED
+CSET mmcm_clkfbout_mult_f=4.000
+CSET mmcm_clkfbout_phase=0.000
+CSET mmcm_clkfbout_use_fine_ps=false
+CSET mmcm_clkin1_period=10.000
+CSET mmcm_clkin2_period=10.000
+CSET mmcm_clkout0_divide_f=4.000
+CSET mmcm_clkout0_duty_cycle=0.500
+CSET mmcm_clkout0_phase=0.000
+CSET mmcm_clkout0_use_fine_ps=false
+CSET mmcm_clkout1_divide=1
+CSET mmcm_clkout1_duty_cycle=0.500
+CSET mmcm_clkout1_phase=0.000
+CSET mmcm_clkout1_use_fine_ps=false
+CSET mmcm_clkout2_divide=1
+CSET mmcm_clkout2_duty_cycle=0.500
+CSET mmcm_clkout2_phase=0.000
+CSET mmcm_clkout2_use_fine_ps=false
+CSET mmcm_clkout3_divide=1
+CSET mmcm_clkout3_duty_cycle=0.500
+CSET mmcm_clkout3_phase=0.000
+CSET mmcm_clkout3_use_fine_ps=false
+CSET mmcm_clkout4_cascade=false
+CSET mmcm_clkout4_divide=1
+CSET mmcm_clkout4_duty_cycle=0.500
+CSET mmcm_clkout4_phase=0.000
+CSET mmcm_clkout4_use_fine_ps=false
+CSET mmcm_clkout5_divide=1
+CSET mmcm_clkout5_duty_cycle=0.500
+CSET mmcm_clkout5_phase=0.000
+CSET mmcm_clkout5_use_fine_ps=false
+CSET mmcm_clkout6_divide=1
+CSET mmcm_clkout6_duty_cycle=0.500
+CSET mmcm_clkout6_phase=0.000
+CSET mmcm_clkout6_use_fine_ps=false
+CSET mmcm_clock_hold=false
+CSET mmcm_compensation=ZHOLD
+CSET mmcm_divclk_divide=1
+CSET mmcm_notes=None
+CSET mmcm_ref_jitter1=0.010
+CSET mmcm_ref_jitter2=0.010
+CSET mmcm_startup_wait=false
+CSET num_out_clks=1
+CSET override_dcm=false
+CSET override_dcm_clkgen=false
+CSET override_mmcm=false
+CSET override_pll=false
+CSET platform=lin64
+CSET pll_bandwidth=OPTIMIZED
+CSET pll_clk_feedback=CLKFBOUT
+CSET pll_clkfbout_mult=16
+CSET pll_clkfbout_phase=0.000
+CSET pll_clkin_period=31.250
+CSET pll_clkout0_divide=5
+CSET pll_clkout0_duty_cycle=0.500
+CSET pll_clkout0_phase=0.000
+CSET pll_clkout1_divide=1
+CSET pll_clkout1_duty_cycle=0.500
+CSET pll_clkout1_phase=0.000
+CSET pll_clkout2_divide=1
+CSET pll_clkout2_duty_cycle=0.500
+CSET pll_clkout2_phase=0.000
+CSET pll_clkout3_divide=1
+CSET pll_clkout3_duty_cycle=0.500
+CSET pll_clkout3_phase=0.000
+CSET pll_clkout4_divide=1
+CSET pll_clkout4_duty_cycle=0.500
+CSET pll_clkout4_phase=0.000
+CSET pll_clkout5_divide=1
+CSET pll_clkout5_duty_cycle=0.500
+CSET pll_clkout5_phase=0.000
+CSET pll_compensation=SYSTEM_SYNCHRONOUS
+CSET pll_divclk_divide=1
+CSET pll_notes=None
+CSET pll_ref_jitter=0.010
+CSET power_down_port=POWER_DOWN
+CSET prim_in_freq=16
+CSET prim_in_jitter=0.010
+CSET prim_source=Single_ended_clock_capable_pin
+CSET primary_port=CLK_IN1
+CSET primitive=MMCM
+CSET primtype_sel=PLL_BASE
+CSET psclk_port=PSCLK
+CSET psdone_port=PSDONE
+CSET psen_port=PSEN
+CSET psincdec_port=PSINCDEC
+CSET relative_inclk=REL_PRIMARY
+CSET reset_port=RESET
+CSET secondary_in_freq=100.000
+CSET secondary_in_jitter=0.010
+CSET secondary_port=CLK_IN2
+CSET secondary_source=Single_ended_clock_capable_pin
+CSET ss_mod_freq=250
+CSET ss_mode=CENTER_HIGH
+CSET status_port=STATUS
+CSET summary_strings=empty
+CSET use_clk_valid=false
+CSET use_clkfb_stopped=false
+CSET use_dyn_phase_shift=false
+CSET use_dyn_reconfig=false
+CSET use_freeze=false
+CSET use_freq_synth=true
+CSET use_inclk_stopped=false
+CSET use_inclk_switchover=false
+CSET use_locked=true
+CSET use_max_i_jitter=false
+CSET use_min_o_jitter=false
+CSET use_min_power=false
+CSET use_phase_alignment=true
+CSET use_power_down=false
+CSET use_reset=true
+CSET use_spread_spectrum=false
+CSET use_spread_spectrum_1=false
+CSET use_status=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-05-10T12:44:55Z
+# END Extra information
+GENERATE
+# CRC: 2c6bfa8c
diff --git a/FPGA/VNA/ipcore_dir/PLL.xise b/FPGA/VNA/ipcore_dir/PLL.xise
new file mode 100644
index 0000000..ceaa4a6
--- /dev/null
+++ b/FPGA/VNA/ipcore_dir/PLL.xise
@@ -0,0 +1,74 @@
+
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diff --git a/FPGA/VNA/ipcore_dir/SinCos.xco b/FPGA/VNA/ipcore_dir/SinCos.xco
new file mode 100644
index 0000000..2d9e926
--- /dev/null
+++ b/FPGA/VNA/ipcore_dir/SinCos.xco
@@ -0,0 +1,142 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Tue May 5 15:36:58 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:dds_compiler:4.0
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT DDS_Compiler xilinx.com:ip:dds_compiler:4.0
+# END Select
+# BEGIN Parameters
+CSET amplitude_mode=Full_Range
+CSET channel_pin=false
+CSET channels=1
+CSET clock_enable=false
+CSET component_name=SinCos
+CSET dds_clock_rate=100
+CSET dsp48_use=Minimal
+CSET explicit_period=false
+CSET frequency_resolution=0.4
+CSET gui_behaviour=Coregen
+CSET has_phase_out=false
+CSET latency=6
+CSET latency_configuration=Auto
+CSET memory_type=Auto
+CSET negative_cosine=false
+CSET negative_sine=false
+CSET noise_shaping=None
+CSET optimization_goal=Auto
+CSET output_frequency1=0
+CSET output_frequency10=0
+CSET output_frequency11=0
+CSET output_frequency12=0
+CSET output_frequency13=0
+CSET output_frequency14=0
+CSET output_frequency15=0
+CSET output_frequency16=0
+CSET output_frequency2=0
+CSET output_frequency3=0
+CSET output_frequency4=0
+CSET output_frequency5=0
+CSET output_frequency6=0
+CSET output_frequency7=0
+CSET output_frequency8=0
+CSET output_frequency9=0
+CSET output_selection=Sine_and_Cosine
+CSET output_width=16
+CSET parameter_entry=Hardware_Parameters
+CSET partspresent=SIN_COS_LUT_only
+CSET period=1
+CSET phase_increment=Fixed
+CSET phase_offset=None
+CSET phase_offset_angles1=0
+CSET phase_offset_angles10=0
+CSET phase_offset_angles11=0
+CSET phase_offset_angles12=0
+CSET phase_offset_angles13=0
+CSET phase_offset_angles14=0
+CSET phase_offset_angles15=0
+CSET phase_offset_angles16=0
+CSET phase_offset_angles2=0
+CSET phase_offset_angles3=0
+CSET phase_offset_angles4=0
+CSET phase_offset_angles5=0
+CSET phase_offset_angles6=0
+CSET phase_offset_angles7=0
+CSET phase_offset_angles8=0
+CSET phase_offset_angles9=0
+CSET phase_width=12
+CSET pinc1=0
+CSET pinc10=0
+CSET pinc11=0
+CSET pinc12=0
+CSET pinc13=0
+CSET pinc14=0
+CSET pinc15=0
+CSET pinc16=0
+CSET pinc2=0
+CSET pinc3=0
+CSET pinc4=0
+CSET pinc5=0
+CSET pinc6=0
+CSET pinc7=0
+CSET pinc8=0
+CSET pinc9=0
+CSET poff1=0
+CSET poff10=0
+CSET poff11=0
+CSET poff12=0
+CSET poff13=0
+CSET poff14=0
+CSET poff15=0
+CSET poff16=0
+CSET poff2=0
+CSET poff3=0
+CSET poff4=0
+CSET poff5=0
+CSET poff6=0
+CSET poff7=0
+CSET poff8=0
+CSET poff9=0
+CSET por_mode=false
+CSET rdy=false
+CSET rfd=false
+CSET sclr_pin=false
+CSET spurious_free_dynamic_range=36
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-08-28T14:48:35Z
+# END Extra information
+GENERATE
+# CRC: dc69a097
diff --git a/FPGA/VNA/ipcore_dir/SinCos.xise b/FPGA/VNA/ipcore_dir/SinCos.xise
new file mode 100644
index 0000000..423665e
--- /dev/null
+++ b/FPGA/VNA/ipcore_dir/SinCos.xise
@@ -0,0 +1,73 @@
+
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diff --git a/FPGA/VNA/ipcore_dir/SinCosMult.xco b/FPGA/VNA/ipcore_dir/SinCosMult.xco
new file mode 100644
index 0000000..bae637f
--- /dev/null
+++ b/FPGA/VNA/ipcore_dir/SinCosMult.xco
@@ -0,0 +1,68 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Tue May 5 15:41:30 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:mult_gen:11.2
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Multiplier xilinx.com:ip:mult_gen:11.2
+# END Select
+# BEGIN Parameters
+CSET ccmimp=Distributed_Memory
+CSET clockenable=false
+CSET component_name=SinCosMult
+CSET constvalue=129
+CSET internaluser=0
+CSET multiplier_construction=Use_Mults
+CSET multtype=Parallel_Multiplier
+CSET optgoal=Speed
+CSET outputwidthhigh=31
+CSET outputwidthlow=0
+CSET pipestages=2
+CSET portatype=Signed
+CSET portawidth=16
+CSET portbtype=Signed
+CSET portbwidth=16
+CSET roundpoint=0
+CSET sclrcepriority=SCLR_Overrides_CE
+CSET syncclear=false
+CSET use_custom_output_width=false
+CSET userounding=false
+CSET zerodetect=false
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-05T14:23:07Z
+# END Extra information
+GENERATE
+# CRC: 7fa795cb
diff --git a/FPGA/VNA/ipcore_dir/SinCosMult.xise b/FPGA/VNA/ipcore_dir/SinCosMult.xise
new file mode 100644
index 0000000..a9f8a31
--- /dev/null
+++ b/FPGA/VNA/ipcore_dir/SinCosMult.xise
@@ -0,0 +1,73 @@
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diff --git a/FPGA/VNA/ipcore_dir/SweepConfigMem.xco b/FPGA/VNA/ipcore_dir/SweepConfigMem.xco
new file mode 100644
index 0000000..2ee1c5a
--- /dev/null
+++ b/FPGA/VNA/ipcore_dir/SweepConfigMem.xco
@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Mon Sep 14 08:50:12 2020
+#
+##############################################################
+#
+# This file contains the customisation parameters for a
+# Xilinx CORE Generator IP GUI. It is strongly recommended
+# that you do not manually alter this file as it may cause
+# unexpected and unsupported behavior.
+#
+##############################################################
+#
+# Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=SweepConfigMem
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Use_ENA_Pin
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=96
+CSET read_width_b=96
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=4501
+CSET write_width_a=96
+CSET write_width_b=96
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC: e7b4a756
diff --git a/FPGA/VNA/ipcore_dir/SweepConfigMem.xise b/FPGA/VNA/ipcore_dir/SweepConfigMem.xise
new file mode 100644
index 0000000..e1d6091
--- /dev/null
+++ b/FPGA/VNA/ipcore_dir/SweepConfigMem.xise
@@ -0,0 +1,73 @@
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