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interrupt safe USB send function

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This commit is contained in:
Jan Käberich 2022-08-21 22:20:59 +02:00
parent 5137457545
commit c05d248f83
13 changed files with 38 additions and 73 deletions
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5
FPGA/VNA/Sweep.vhd
View File

@ -196,6 +196,7 @@ begin
end if;
end if;
when Settling =>
NEW_DATA <= '0';
source_active <= '0';
if std_logic_vector(stage_cnt) = PORT1_STAGE then
PORT1_ACTIVE <= '1';
@ -232,7 +233,6 @@ begin
-- wait for sampling to finish
START_SAMPLING <= '0';
if SAMPLING_BUSY = '0' then
NEW_DATA <= '1';
RESULT_INDEX <= std_logic_vector(stage_cnt) & std_logic_vector(point_cnt);
state <= WaitTriggerLow;
end if;
@ -246,7 +246,7 @@ begin
state <= SamplingDone;
end if;
when SamplingDone =>
NEW_DATA <= '0';
NEW_DATA <= '1';
if stage_cnt < unsigned(STAGES) then
stage_cnt <= stage_cnt + 1;
-- can go directly to preperation for next stage
@ -256,6 +256,7 @@ begin
end if;
settling_cnt <= settling_time;
when NextPoint =>
NEW_DATA <= '0';
if point_cnt < unsigned(NPOINTS) then
point_cnt <= point_cnt + 1;
stage_cnt <= (others => '0');

14
FPGA/VNA/VNA.gise
View File

@ -224,7 +224,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1659962405" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1659962405">
<transform xil_pn:end_ts="1661101063" xil_pn:in_ck="-4366097307991745463" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1661101062">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
@ -253,7 +253,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1659974081" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1659974072">
<transform xil_pn:end_ts="1661101072" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1661101063">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -275,7 +275,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1659974085" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1659974081">
<transform xil_pn:end_ts="1661101076" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1661101072">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
@ -284,7 +284,7 @@
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1659974193" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1659974085">
<transform xil_pn:end_ts="1661101188" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1661101076">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -298,7 +298,7 @@
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1659974205" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1659974193">
<transform xil_pn:end_ts="1661101201" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1661101188">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -312,7 +312,7 @@
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1659974213" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1659974205">
<transform xil_pn:end_ts="1661101208" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1661101201">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -366,7 +366,7 @@
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
</transform>
<transform xil_pn:end_ts="1659974205" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1659974202">
<transform xil_pn:end_ts="1661101201" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1661101197">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

BIN
FPGA/VNA/top.bin
View File

Binary file not shown.

6
Software/PC_Application/Device/device.cpp
View File

@ -581,16 +581,16 @@ void Device::transmissionFinished(TransmissionResult result)
// remove transmitted packet
// qDebug() << "Transmission finsished (" << result << "), queue at " << transmissionQueue.size() << " Outstanding ACKs:"<<outstandingAckCount;
if(transmissionQueue.empty()) {
qWarning() << "transmissionFinished with empty transmission queue, stray Ack?";
qWarning() << "transmissionFinished with empty transmission queue, stray Ack? Result:" << result;
return;
}
auto t = transmissionQueue.dequeue();
if(result == TransmissionResult::Timeout) {
qWarning() << "transmissionFinished with timeout";
qWarning() << "transmissionFinished with timeout, packettype:" << (int) t.packet.type << "Device:" << serial();
}
if(result == TransmissionResult::Nack) {
qWarning() << "transmissionFinished with NACK";
}
auto t = transmissionQueue.dequeue();
if(t.callback) {
t.callback(result);
}

3
Software/PC_Application/Device/device.h
View File

@ -118,7 +118,8 @@ private:
USBInBuffer *dataBuffer;
USBInBuffer *logBuffer;
using Transmission = struct {
class Transmission {
public:
Protocol::PacketInfo packet;
unsigned int timeout;
std::function<void(TransmissionResult)> callback;

1
Software/VNA_embedded/Application/App.cpp
View File

@ -119,6 +119,7 @@ inline void App_Init() {
inline void App_Process() {
while(1) {
uint32_t notification;
LED::Toggle();
if(xTaskNotifyWait(0x00, UINT32_MAX, &notification, 100) == pdPASS) {
// something happened
if(notification & FLAG_USB_PACKET) {

2
Software/VNA_embedded/Application/Communication/Communication.cpp
View File

@ -7,7 +7,6 @@
static uint8_t inputBuffer[1024];
uint16_t inputCnt = 0;
static uint8_t outputBuffer[1024];
static Communication::Callback callback = nullptr;
static uint8_t blockAcks = 0;
@ -45,6 +44,7 @@ void Communication::Input(const uint8_t *buf, uint16_t len) {
#include "Hardware.hpp"
bool Communication::Send(const Protocol::PacketInfo &packet) {
// DEBUG1_HIGH();
uint8_t outputBuffer[512];
uint16_t len = Protocol::EncodePacket(packet, outputBuffer,
sizeof(outputBuffer));
// DEBUG1_LOW();

6
Software/VNA_embedded/Application/Communication/Protocol.cpp
View File

@ -59,6 +59,12 @@ uint16_t Protocol::DecodeBuffer(uint8_t *buf, uint16_t len, PacketInfo *info) {
return data - buf;
}
if(length > sizeof(PacketInfo) * 2) {
// larger than twice the maximum expected packet size, probably an error, ignore
info->type = PacketType::None;
return 1;
}
/* The complete frame has been received, check checksum */
auto type = (PacketType) data[3];
uint32_t crc = *(uint32_t*) &data[length - 4];

11
Software/VNA_embedded/Application/Drivers/USB/usb.c
View File

@ -230,7 +230,6 @@ bool usb_transmit(const uint8_t *data, uint16_t length) {
// grab pointer to write position
__disable_irq();
uint16_t write_index = usb_transmit_read_index + usb_transmit_fifo_level;
__enable_irq();
write_index %= sizeof(usb_transmit_fifo);
// copy the data to the fifo
uint16_t continous_length = sizeof(usb_transmit_fifo) - write_index;
@ -243,21 +242,19 @@ bool usb_transmit(const uint8_t *data, uint16_t length) {
memcpy(&usb_transmit_fifo[0], data + continous_length, length - continous_length);
}
// increment fifo level
__disable_irq();
usb_transmit_fifo_level += length;
__enable_irq();
static bool first = true;
if(first) {
log_transmission_active = false;
first = false;
}
bool ret = true;
if(!data_transmission_active) {
return trigger_next_fifo_transmission();
} else {
// still transmitting, no need to trigger
return true;
ret = trigger_next_fifo_transmission();
}
__enable_irq();
return ret;
}
void usb_log(const char *log, uint16_t length) {

2
Software/VNA_embedded/Inc/main.h
View File

@ -61,8 +61,6 @@ extern "C" {
/* USER CODE END EM */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);

23
Software/VNA_embedded/Src/main.c
View File

@ -466,7 +466,6 @@ static void MX_TIM2_Init(void)
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
TIM_MasterConfigTypeDef sMasterConfig = {0};
TIM_OC_InitTypeDef sConfigOC = {0};
/* USER CODE BEGIN TIM2_Init 1 */
@ -486,28 +485,15 @@ static void MX_TIM2_Init(void)
{
Error_Handler();
}
if (HAL_TIM_PWM_Init(&htim2) != HAL_OK)
{
Error_Handler();
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
{
Error_Handler();
}
sConfigOC.OCMode = TIM_OCMODE_PWM2;
sConfigOC.Pulse = 0;
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN TIM2_Init 2 */
/* USER CODE END TIM2_Init 2 */
HAL_TIM_MspPostInit(&htim2);
}
@ -715,7 +701,7 @@ static void MX_GPIO_Init(void)
__HAL_RCC_GPIOB_CLK_ENABLE();
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOA, FPGA_AUX1_Pin|FPGA_AUX3_Pin|FPGA_AUX2_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GPIOA, FPGA_AUX1_Pin|FPGA_AUX3_Pin|FPGA_AUX2_Pin|GPIO_PIN_15, GPIO_PIN_RESET);
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(FPGA_CS_GPIO_Port, FPGA_CS_Pin, GPIO_PIN_SET);
@ -759,6 +745,13 @@ static void MX_GPIO_Init(void)
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/*Configure GPIO pin : PA15 */
GPIO_InitStruct.Pin = GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/*Configure GPIO pin : FPGA_TRIGGER_OUT_Pin */
GPIO_InitStruct.Pin = FPGA_TRIGGER_OUT_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_INPUT;

30
Software/VNA_embedded/Src/stm32g4xx_hal_msp.c
View File

@ -60,9 +60,7 @@ extern DMA_HandleTypeDef hdma_spi1_tx;
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
/**
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
@ -404,32 +402,6 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
}
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(htim->Instance==TIM2)
{
/* USER CODE BEGIN TIM2_MspPostInit 0 */
/* USER CODE END TIM2_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
/**TIM2 GPIO Configuration
PA15 ------> TIM2_CH1
*/
GPIO_InitStruct.Pin = GPIO_PIN_15;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN TIM2_MspPostInit 1 */
/* USER CODE END TIM2_MspPostInit 1 */
}
}
/**
* @brief TIM_Base MSP De-Initialization
* This function freeze the hardware resources used in this example

8
Software/VNA_embedded/VNA_embedded.ioc
View File

@ -204,7 +204,7 @@ PA14.Locked=true
PA14.Mode=Serial_Wire
PA14.Signal=SYS_JTCK-SWCLK
PA15.Locked=true
PA15.Signal=S_TIM2_CH1
PA15.Signal=GPIO_Output
PA2.GPIOParameters=GPIO_Speed,GPIO_Label
PA2.GPIO_Label=FPGA_AUX3
PA2.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH
@ -386,8 +386,6 @@ RCC.VCOInputFreq_Value=4000000
RCC.VCOOutputFreq_Value=320000000
SH.GPXTI1.0=GPIO_EXTI1
SH.GPXTI1.ConfNb=1
SH.S_TIM2_CH1.0=TIM2_CH1,PWM Generation1 CH1
SH.S_TIM2_CH1.ConfNb=1
SPI1.BaudRatePrescaler=SPI_BAUDRATEPRESCALER_4
SPI1.CalculateBaudRate=40.0 MBits/s
SPI1.DataSize=SPI_DATASIZE_8BIT
@ -404,9 +402,7 @@ SPI2.Mode=SPI_MODE_MASTER
SPI2.VirtualType=VM_MASTER
TIM1.IPParameters=Prescaler
TIM1.Prescaler=159
TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
TIM2.IPParameters=Prescaler,PeriodNoDither,Channel-PWM Generation1 CH1,OCMode_PWM-PWM Generation1 CH1
TIM2.OCMode_PWM-PWM\ Generation1\ CH1=TIM_OCMODE_PWM2
TIM2.IPParameters=Prescaler,PeriodNoDither
TIM2.PeriodNoDither=99
TIM2.Prescaler=143
USART3.IPParameters=WordLength,VirtualMode-Asynchronous