Basic DFT spectrum analysis working

Documentation/DeveloperInfo/FPGA_protocol.tex

@@ -448,30 +448,6 @@ In addition to the single bin DFT configured through the ADC prescaler and phase
 
 The DFT has a fixed number of bins (64), but the frequencies these bins correspond to can be changed.
 
-\subsubsection{Number of samples: 0x10}
-\label{reg:dft-nsamples}
-\begin{center}
-\begin{tikzpicture}
-\bitrect{16}{16-\bit}
-\rwbits{0}{16}{DFT\_SAMPLES[15:0]}
-\end{tikzpicture}
-\end{center}
-\begin{itemize}
-\item \textbf{DFT\_SAMPLES[15:0]:} Amount of samples the DFT should take. This should always match the number of samples configured with the Samples Per Point register (see~\ref{reg:spp}).
-\end{itemize}
-
-\subsubsection{Window increment: 0x11}
-\begin{center}
-\begin{tikzpicture}
-\bitrect{16}{16-\bit}
-\rwbits{0}{16}{DFT\_WINDOW\_INC[15:0]}
-\end{tikzpicture}
-\end{center}
-\begin{itemize}
-\item \textbf{DFT\_WINDOW\_INC[15:0]:} Window increment value after each sample. This should always be set in such a way, that the window is iterated over exactly once after all samples configured with DFT\_SAMPLES (see \ref{reg:dft-nsamples}) have been taken.
-$$ TODO: formula $$
-\end{itemize}
-
 \subsubsection{DFT\_FIRST\_BIN: 0x12}
 \begin{center}
 \begin{tikzpicture}

FPGA/VNA/DFT.vhd

@@ -36,11 +36,9 @@ entity DFT is
            PORT1 : in  STD_LOGIC_VECTOR (15 downto 0);
            PORT2 : in  STD_LOGIC_VECTOR (15 downto 0);
            NEW_SAMPLE : in  STD_LOGIC;
-			  NSAMPLES : in STD_LOGIC_VECTOR (15 downto 0);
+			  NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
            BIN1_PHASEINC : in  STD_LOGIC_VECTOR (15 downto 0);
            DIFFBIN_PHASEINC : in  STD_LOGIC_VECTOR (15 downto 0);
-			  WINDOW_INC : in STD_LOGIC_VECTOR (15 downto 0);
-			  WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
            RESULT_READY : out  STD_LOGIC;
            OUTPUT : out  STD_LOGIC_VECTOR (191 downto 0);
            NEXT_OUTPUT : in  STD_LOGIC);
@@ -85,6 +83,17 @@ COMPONENT SinCosMult
     p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
   );
 END COMPONENT;
+COMPONENT DSP_SLICE
+  PORT (
+    clk : IN STD_LOGIC;
+    ce : IN STD_LOGIC;
+    sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+    b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+    c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+    p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+  );
+END COMPONENT;
 COMPONENT window
 PORT(
 	CLK : IN std_logic;
@@ -105,7 +114,8 @@ END COMPONENT;
 	--signal port2_real_read : std_logic_vector(47 downto 0);
 	--signal port2_imag_read : std_logic_vector(47 downto 0);
 	
-	signal sample_cnt : integer range 0 to 65535;
+	signal sample_cnt : integer range 0 to 131072;
+	signal samples_to_take : integer range 0 to 131072;
 	signal bin_cnt : integer range 0 to BINS+2;
 	
 	signal read_address : integer range 0 to BINS-1;
@@ -116,35 +126,38 @@ END COMPONENT;
 	signal ram_in : std_logic_vector(191 downto 0);
 	signal ram_out : std_logic_vector(191 downto 0);
 	
-	type States is (WaitingForSample, WaitMult, WaitMult2, PhaseReady, WindowingReady, WaitSinCos, Busy, Ready);
+	type States is (WaitingForSample, WaitMult, WaitSinCos, Busy, Ready);
 	signal state : States;
 	signal port1_latch : std_logic_vector(15 downto 0);
 	signal port2_latch : std_logic_vector(15 downto 0);
 	
-	signal window_index : std_logic_vector(15 downto 0);
-
-	signal window_value : std_logic_vector(15 downto 0);
-	
 	signal phase : std_logic_vector(31 downto 0);
 	signal phase_inc : std_logic_vector(31 downto 0);
 	signal sine : std_logic_vector(15 downto 0);
 	signal cosine : std_logic_vector(15 downto 0);
 	
-	signal mult1_a : std_logic_vector(15 downto 0);
+	signal mult1_a : std_logic_vector(17 downto 0);
-	signal mult1_b : std_logic_vector(15 downto 0);
+	signal mult1_b : std_logic_vector(17 downto 0);
-	signal mult1_p : std_logic_vector(31 downto 0);
+	signal mult1_c : std_logic_vector(47 downto 0);
+	signal mult1_p : std_logic_vector(47 downto 0);
 	
-	signal mult2_a : std_logic_vector(15 downto 0);
+	signal mult2_a : std_logic_vector(17 downto 0);
-	signal mult2_b : std_logic_vector(15 downto 0);
+	signal mult2_b : std_logic_vector(17 downto 0);
-	signal mult2_p : std_logic_vector(31 downto 0);
+	signal mult2_c : std_logic_vector(47 downto 0);
+	signal mult2_p : std_logic_vector(47 downto 0);
 	
-	signal mult3_a : std_logic_vector(15 downto 0);
+	signal mult3_a : std_logic_vector(17 downto 0);
-	signal mult3_b : std_logic_vector(15 downto 0);
+	signal mult3_b : std_logic_vector(17 downto 0);
-	signal mult3_p : std_logic_vector(31 downto 0);
+	signal mult3_c : std_logic_vector(47 downto 0);
+	signal mult3_p : std_logic_vector(47 downto 0);
 	
-	signal mult4_a : std_logic_vector(15 downto 0);
+	signal mult4_a : std_logic_vector(17 downto 0);
-	signal mult4_b : std_logic_vector(15 downto 0);
+	signal mult4_b : std_logic_vector(17 downto 0);
-	signal mult4_p : std_logic_vector(31 downto 0);
+	signal mult4_c : std_logic_vector(47 downto 0);
+	signal mult4_p : std_logic_vector(47 downto 0);
+	
+	signal mult_enable : std_logic;
+	signal mult_accumulate : std_logic_vector(0 downto 0);
 begin
 
 	LookupTable : SinCos
@@ -154,53 +167,48 @@ begin
 		cosine => cosine,
 		sine => sine
 	);
-	Mult1 : SinCosMult
+	Mult1 : DSP_SLICE
 	PORT MAP (
 		clk => CLK,
+		ce => mult_enable,
+		sel => mult_accumulate,
 		a => mult1_a,
 		b => mult1_b,
+		c => mult1_c,
 		p => mult1_p
 	);
-	Mult2 : SinCosMult
+	Mult2 : DSP_SLICE
 	PORT MAP (
 		clk => CLK,
+		ce => mult_enable,
+		sel => mult_accumulate,
 		a => mult2_a,
 		b => mult2_b,
+		c => mult2_c,
 		p => mult2_p
 	);
-	Mult3 : SinCosMult
+	Mult3 : DSP_SLICE
 	PORT MAP (
 		clk => CLK,
+		ce => mult_enable,
+		sel => mult_accumulate,
 		a => mult3_a,
 		b => mult3_b,
+		c => mult3_c,
 		p => mult3_p
 	);
-	Mult4 : SinCosMult
+	Mult4 : DSP_SLICE
 	PORT MAP (
 		clk => CLK,
+		ce => mult_enable,
+		sel => mult_accumulate,
 		a => mult4_a,
 		b => mult4_b,
+		c => mult4_c,
 		p => mult4_p
 	);
-	WindowROM: window PORT MAP(
-		CLK => CLK,
-		INDEX => window_index(15 downto 9),
-		WINDOW_TYPE => WINDOW_TYPE,
-		VALUE => window_value
-	);
 	
---	result_ram: dft_result
+	result_ram: result_bram
---	GENERIC MAP(depth => BINS)
---	PORT MAP(
---		CLK => CLK,
---		READ_ADDRESS => read_address,
---		WRITE_ADDRESS => write_address,
---		DATA_IN => ram_in,
---		DATA_OUT => ram_out,
---		WE => we
---	);
-
-your_instance_name : result_bram
 	PORT MAP (
 		clka => CLK,
 		wea => we,
@@ -215,11 +223,19 @@ your_instance_name : result_bram
 	write_address_vector <= std_logic_vector(to_unsigned(write_address, 6));
 	OUTPUT <= ram_out;
 	
+	mult1_c <= ram_out(191 downto 144);
+	mult2_c <= ram_out(143 downto 96);
+	mult3_c <= ram_out(95 downto 48);
+	mult4_c <= ram_out(47 downto 0);
+	
+	ram_in <= mult1_p & mult2_p & mult3_p & mult4_p;
+	
 	process(CLK, RESET)
 	begin
 		if rising_edge(CLK) then
 			if RESET = '1' then
-				window_index <= (others => '0');
+				mult_enable <= '0';
+				mult_accumulate <= "0";
 				sample_cnt <= 0;
 				RESULT_READY <= '0';
 				read_address <= 0;
@@ -227,108 +243,124 @@ your_instance_name : result_bram
 				we <= "0";
 				state <= WaitingForSample;
 			else
+				samples_to_take <= to_integer(unsigned(NSAMPLES & "0000")) - 1;
 				case state is
 					when WaitingForSample =>
 						we <= "0";
+						mult_enable <= '0';
+						mult_accumulate <= "0";
+						read_address <= 0;
+						write_address <= 0;
 						if NEW_SAMPLE = '1' then
 							-- calculate phase for initial bin
-							-- TODO this should use unsigned multiplication
+							mult1_a <= std_logic_vector(to_unsigned(sample_cnt, 18));
-							mult1_a <= std_logic_vector(to_unsigned(sample_cnt, 16));
+							mult1_b <= "00" & BIN1_PHASEINC;
-							mult1_b <= BIN1_PHASEINC;
+							mult2_a <= std_logic_vector(to_unsigned(sample_cnt, 18));
-							mult2_a <= std_logic_vector(to_unsigned(sample_cnt, 16));
+							mult2_b <= "00" & DIFFBIN_PHASEINC;
-							mult2_b <= DIFFBIN_PHASEINC;
-							-- window ADC data
-							mult3_a <= PORT1;
-							mult3_b <= window_value;
-							mult4_a <= PORT2;
-							mult4_b <= window_value;
 							state <= WaitMult;
-							read_address <= 0;
+							bin_cnt <= 0;
+							mult_enable <= '1';
 						end if;
 					when WaitMult =>
 						RESULT_READY <= '0';
 						we <= "0";
-						state <= WaitMult2;
+						mult_enable <= '1';
-					when WaitMult2 =>
+						mult_accumulate <= "0";
-						RESULT_READY <= '0';
+						read_address <= 0;
-						we <= "0";
+						write_address <= 0;
-						state <= PhaseReady;							
-					when PhaseReady =>
-						RESULT_READY <= '0';
-						we <= "0";
-						-- initial phase is ready
-						phase <= mult1_p(15 downto 0) & "0000000000000000";
-						phase_inc <= mult2_p(23 downto 0) & "00000000";
-						state <= WindowingReady;
-					when WindowingReady =>
-						RESULT_READY <= '0';
-						we <= "0";
-						phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
-						port1_latch <= mult3_p(31 downto 16);
-						port2_latch <= mult4_p(31 downto 16);
-						bin_cnt <= 0;
-						state <= WaitSinCos;
-					when WaitSinCos =>
-						phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
-						RESULT_READY <= '0';
-						we <= "0";
 						if bin_cnt < 4 then
 							bin_cnt <= bin_cnt + 1;
 						else
 							bin_cnt <= 0;
+							mult_enable <= '0';
+							state <= WaitSinCos;
+							phase <= mult1_p(15 downto 0) & "0000000000000000";
+							phase_inc <= mult2_p(23 downto 0) & "00000000";
+							port1_latch <= PORT1;
+							port2_latch <= PORT2;
+						end if;
+					when WaitSinCos =>
+						phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
+						RESULT_READY <= '0';
+						we <= "0";
+						mult_enable <= '0';
+						mult_accumulate <= "0";
+						read_address <= 0;
+						write_address <= 0;
+						if bin_cnt < 6 then
+							bin_cnt <= bin_cnt + 1;
+						else
+							bin_cnt <= 0;
+							mult_enable <= '1';
+							read_address <= 1;
+							-- sign extended multiplication
+							mult1_a <= port1_latch(15) & port1_latch(15) & port1_latch;
+							mult1_b <= sine(15) & sine(15) & sine;
+							mult2_a <= port1_latch(15) & port1_latch(15) & port1_latch;
+							mult2_b <= cosine(15) & cosine(15) & cosine;
+							mult3_a <= port2_latch(15) & port2_latch(15) & port2_latch;
+							mult3_b <= sine(15) & sine(15) & sine;
+							mult4_a <= port2_latch(15) & port2_latch(15) & port2_latch;
+							mult4_b <= cosine(15) & cosine(15) & cosine;
 							state <= BUSY;
+							if sample_cnt = 0 then
+								mult_accumulate <= "0";
+							else
+								mult_accumulate <= "1";
+							end if;
 						end if;
 					when BUSY =>
+						mult_enable <= '1';
+						if sample_cnt = 0 then
+							mult_accumulate <= "0";
+						else
+							mult_accumulate <= "1";
+						end if;
 						RESULT_READY <= '0';
 						phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
-						mult1_a <= port1_latch;
+						-- sign extended multiplication
-						mult1_b <= sine;
+						mult1_a <= port1_latch(15) & port1_latch(15) & port1_latch;
-						mult2_a <= port1_latch;
+						mult1_b <= sine(15) & sine(15) & sine;
-						mult2_b <= cosine;
+						mult2_a <= port1_latch(15) & port1_latch(15) & port1_latch;
-						mult3_a <= port2_latch;
+						mult2_b <= cosine(15) & cosine(15) & cosine;
-						mult3_b <= sine;
+						mult3_a <= port2_latch(15) & port2_latch(15) & port2_latch;
-						mult4_a <= port2_latch;
+						mult3_b <= sine(15) & sine(15) & sine;
-						mult4_b <= cosine;
+						mult4_a <= port2_latch(15) & port2_latch(15) & port2_latch;
+						mult4_b <= cosine(15) & cosine(15) & cosine;
 						if bin_cnt >= 3 then
-							-- multiplier result is available, accumulate
+							-- multiplier result is available, advance write address
 							we <= "1";
 							write_address <= bin_cnt - 3;
-							ram_in <= std_logic_vector(signed(ram_out(191 downto 144))+signed(mult1_p))
-										& std_logic_vector(signed(ram_out(143 downto 96))+signed(mult2_p))
-										& std_logic_vector(signed(ram_out(95 downto 48))+signed(mult3_p))
-										& std_logic_vector(signed(ram_out(47 downto 0))+signed(mult4_p));
 						else
 							we <= "0";
+							write_address <= 0;
 						end if;
 						if bin_cnt >= BINS+2 then
 							read_address <= 0;
-							if sample_cnt < unsigned(NSAMPLES) then
+							if sample_cnt < samples_to_take then
 								sample_cnt <= sample_cnt + 1;
 								state <= WaitingForSample;
-								window_index <= std_logic_vector(unsigned(window_index)+unsigned(WINDOW_INC));
 							else
 								state <= Ready;
 							end if;
 						else
 							bin_cnt <= bin_cnt + 1;
-							if bin_cnt >= 1 then
+							if bin_cnt < BINS - 2 then
-								read_address <= bin_cnt - 1;
+								read_address <= bin_cnt + 2;
 							end if;
 						end if;
 					when Ready =>
 						we <= "0";
 						RESULT_READY <= '1';
+						write_address <= 0;
 						if NEXT_OUTPUT = '1' then
-							-- reset last entry to prepare for next DFT
-							write_address <= read_address;
-							ram_in <= (others => '0');
-							we <= "1";
 							-- fetch next entry from RAM
 							if read_address < BINS - 1 then
 								read_address <= read_address + 1;
 							else
 								RESULT_READY <= '0';
 								sample_cnt <= 0;
+								mult_enable <= '0';
 								state <= WaitingForSample;
 								read_address <= 0;
 							end if;

FPGA/VNA/ResetDelay.vhd

@@ -40,16 +40,17 @@ architecture Behavioral of ResetDelay is
 	signal clk_cnt : integer range 0 to CLK_DELAY-1;
 begin
 
-	OUT_RESET <= '1' when IN_RESET = '1' or clk_cnt < CLK_DELAY-1 else '0';
-
 	process(CLK, IN_RESET)
 	begin
 		if rising_edge(CLK) then
 			if IN_RESET = '1' then
 				clk_cnt <= 0;
+				OUT_RESET <= '1';
 			else
 				if clk_cnt < CLK_DELAY-1 then
 					clk_cnt <= clk_cnt + 1;
+				else
+					OUT_RESET <= '0';
 				end if;
 			end if;
 		end if;

FPGA/VNA/SPIConfig.vhd

@@ -71,10 +71,8 @@ entity SPICommands is
 			  SWEEP_RESUME : out STD_LOGIC;
 			  
 			  -- DFT signals
-			  DFT_NSAMPLES : out STD_LOGIC_VECTOR (15 downto 0);
 			  DFT_BIN1_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
            DFT_DIFFBIN_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
-			  DFT_WINDOW_INC : out STD_LOGIC_VECTOR (15 downto 0);
 			  DFT_RESULT_READY : in  STD_LOGIC;
            DFT_OUTPUT : in  STD_LOGIC_VECTOR (191 downto 0);
            DFT_NEXT_OUTPUT : out  STD_LOGIC;
@@ -103,7 +101,7 @@ architecture Behavioral of SPICommands is
 	signal spi_buf_in : std_logic_vector(15 downto 0);
 	signal spi_complete : std_logic;
 	signal word_cnt : integer range 0 to 19;
-	type SPI_states is (Invalid, WriteSweepConfig, ReadResult, WriteRegister, ReadTest);
+	type SPI_states is (FirstWord, WriteSweepConfig, ReadResult, WriteRegister);
 	signal state : SPI_states;
 	signal selected_register : integer range 0 to 31;
 	
@@ -166,11 +164,10 @@ begin
 				ADC_PHASEINC <= std_logic_vector(to_unsigned(1120, 12));
 				RESET_MINMAX <= '0';
 				INTERRUPT_ASSERTED <= '0';
+				latched_result <= (others => '0');
 				
-				DFT_NSAMPLES <= (others => '0');
 				DFT_BIN1_PHASEINC <= (others => '0');
 				DFT_DIFFBIN_PHASEINC <= (others => '0');
-				DFT_WINDOW_INC <= (others => '0');
 				dft_next <= '0';
 				last_NSS <= '1';
 			else
@@ -198,19 +195,21 @@ begin
 				if NSS = '0' and last_NSS = '1' then
 					word_cnt <= 0;
 					spi_buf_in <= interrupt_status;
+					state <= FirstWord;
 				elsif spi_complete = '1' then
 					word_cnt <= word_cnt + 1;
-					if word_cnt = 0 then
+					case state is
+					when FirstWord =>
 						-- initial word determines action
 						case spi_buf_out(15 downto 13) is
 							when "000" => state <= WriteSweepConfig;
 											-- also extract the point number
 											SWEEP_ADDRESS <= spi_buf_out(12 downto 0);
-							when "001" => state <= Invalid;
+							when "001" => state <= FirstWord;
 											SWEEP_RESUME <= '1';
-							when "010" => state <= ReadTest;
+							when "010" => state <= FirstWord;
 											spi_buf_in <= "1111000010100101";
-							when "011" => state <= Invalid;
+							when "011" => state <= FirstWord;
 											RESET_MINMAX <= '1';
 							when "100" => state <= WriteRegister;
 											selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0)));
@@ -225,10 +224,9 @@ begin
 							when "111" => state <= ReadResult; -- can use same state as read result, but the latched data will contain the min/max ADC values
 											latched_result(79 downto 0) <= ADC_MINMAX(95 downto 16);
 											spi_buf_in <= ADC_MINMAX(15 downto 0);
-							when others => state <= Invalid;
+							when others => state <= FirstWord;
 						end case;
-					else
+					when WriteRegister =>
-						if state = WriteRegister then
 						-- write received data into previously selected register
 						case selected_register is
 							when 0 => interrupt_mask <= spi_buf_out;
@@ -257,14 +255,12 @@ begin
 							when 13 => MAX2871_DEF_3(31 downto 16) <= spi_buf_out;
 							when 14 => MAX2871_DEF_4(15 downto 0) <= spi_buf_out;
 							when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
-								when 16 => DFT_NSAMPLES <= spi_buf_out;
-								when 17 => DFT_WINDOW_INC <= spi_buf_out;
 							when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
 							when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
 							when others => 
 						end case;
 						selected_register <= selected_register + 1;
-						elsif state = WriteSweepConfig then
+					when WriteSweepConfig =>
 						if word_cnt = 6 then
 							-- Sweep config data is complete pass on
 							SWEEP_DATA <= sweepconfig_buffer & spi_buf_out;
@@ -273,12 +269,11 @@ begin
 							-- shift next word into buffer
 							sweepconfig_buffer <= sweepconfig_buffer(63 downto 0) & spi_buf_out;
 						end if;
-						elsif state = ReadResult then
+					when ReadResult =>
 						-- pass on next word of latched result
 						spi_buf_in <= latched_result(15 downto 0);
 						latched_result <= "0000000000000000" & latched_result(287 downto 16);
-						end if;
+					end case;
-					end if;
 				end if;
 			end if;
 		end if;

FPGA/VNA/Sampling.vhd

@@ -44,7 +44,6 @@ entity Sampling is
            PRE_DONE : out  STD_LOGIC;
            START : in  STD_LOGIC;
            SAMPLES : in  STD_LOGIC_VECTOR (12 downto 0);
-			  WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
            PORT1_I : out  STD_LOGIC_VECTOR (47 downto 0);
            PORT1_Q : out  STD_LOGIC_VECTOR (47 downto 0);
            PORT2_I : out  STD_LOGIC_VECTOR (47 downto 0);
@@ -94,16 +93,6 @@ END COMPONENT;
 	signal sine : std_logic_vector(15 downto 0);
 	signal cosine : std_logic_vector(15 downto 0);
 	
-	signal windowed_sine : std_logic_vector(31 downto 0);
-	signal windowed_cosine : std_logic_vector(31 downto 0);
-	
-	signal window_index : std_logic_vector(6 downto 0);
-	signal window_value : std_logic_vector(15 downto 0);
-	signal window_sample_cnt : integer range 0 to 8191;
-	signal window_index_inc : integer range 0 to 8;
-	signal window_sample_compare : integer range 0 to 8191;
-	signal window_sample_cnt_inc : integer range 0 to 8;
-	
 	signal mult1_I : std_logic_vector(31 downto 0);
 	signal mult1_Q : std_logic_vector(31 downto 0);
 	signal mult2_I : std_logic_vector(31 downto 0);
@@ -132,64 +121,43 @@ begin
 	PORT MAP (
 		clk => CLK,
 		a => PORT1,
-		b => windowed_cosine(31 downto 16),
+		b => cosine,
 		p => mult1_I
 	);
 	Port1_Q_Mult : SinCosMult
 	PORT MAP (
 		clk => CLK,
 		a => PORT1,
-		b => windowed_sine(31 downto 16),
+		b => sine,
 		p => mult1_Q
 	);
 	Port2_I_Mult : SinCosMult
 	PORT MAP (
 		clk => CLK,
 		a => PORT2,
-		b => windowed_cosine(31 downto 16),
+		b => cosine,
 		p => mult2_I
 	);
 	Port2_Q_Mult : SinCosMult
 	PORT MAP (
 		clk => CLK,
 		a => PORT2,
-		b => windowed_sine(31 downto 16),
+		b => sine,
 		p => mult2_Q
 	);
 	Ref_I_Mult : SinCosMult
 	PORT MAP (
 		clk => CLK,
 		a => REF,
-		b => windowed_cosine(31 downto 16),
+		b => cosine,
 		p => multR_I
 	);
 	Ref_Q_Mult : SinCosMult
 	PORT MAP (
 		clk => CLK,
 		a => REF,
-		b => windowed_sine(31 downto 16),
-		p => multR_Q
-	);
-	
-	Sine_Mult : SinCosMult
-	PORT MAP (
-		clk => CLK,
-		a => window_value,
 		b => sine,
-		p => windowed_sine
+		p => multR_Q
-	);
-	Cosine_Mult : SinCosMult
-	PORT MAP (
-		clk => CLK,
-		a => window_value,
-		b => cosine,
-		p => windowed_cosine
-	);
-	WindowROM: window PORT MAP(
-		CLK => CLK,
-		INDEX => window_index,
-		WINDOW_TYPE => WINDOW_TYPE,
-		VALUE => window_value
 	);
 	
 	process(CLK, RESET)
@@ -203,8 +171,6 @@ begin
 				ACTIVE <= '0';
 				clk_cnt <= 0;
 				sample_cnt <= 0;
-				window_sample_cnt <= 0;
-				window_index <= (others => '0');
 				phase <= (others => '0');
 			else
 				-- when not idle, generate pulses for ADCs
@@ -244,25 +210,6 @@ begin
 						if START = '1' then
 							state <= Sampling;
 							samples_to_take <= to_integer(unsigned(SAMPLES & "0000") - 1);
-							window_sample_compare <= to_integer(unsigned(SAMPLES) - 1);
-							case SAMPLES is
-								when "0000000000001" =>
-									-- 16 samples, increment on every sample by 8
-									window_sample_cnt_inc <= 1;
-									window_index_inc <= 8;
-								when "0000000000010" | "0000000000011" =>
-									-- 32-48 samples, increment by 4
-									window_sample_cnt_inc <= 2;
-									window_index_inc <= 4;
-								when "0000000000100" | "0000000000101" | "0000000000110" | "0000000000111"=>
-									-- 64-112 samples, increment by 2
-									window_sample_cnt_inc <= 4;
-									window_index_inc <= 2;									
-								when others =>
-									-- 128 or more samples, increment by 1
-									window_sample_cnt_inc <= 8;
-									window_index_inc <= 1;
-								end case;
 						end if;
 					when Sampling =>
 						DONE <= '0';
@@ -294,13 +241,6 @@ begin
 						else
 							state <= Ready;
 						end if;
-						-- keep track of window index
-						if window_sample_cnt < window_sample_compare then
-							window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc;
-						else
-							window_sample_cnt <= window_sample_cnt - window_sample_compare;
-							window_index <= std_logic_vector( unsigned(window_index) + window_index_inc );
-						end if;
 					when Ready =>
 						ACTIVE <= '1';
 						DONE <= '1';

FPGA/VNA/Sweep.vhd

@@ -82,45 +82,41 @@ architecture Behavioral of Sweep is
 	signal state : Point_states;
 	signal settling_cnt : unsigned(15 downto 0);
 	signal settling_time : unsigned(15 downto 0);
+	signal config_reg : std_logic_vector(95 downto 0);
 begin
 	
 	CONFIG_ADDRESS <= std_logic_vector(point_cnt);
 	
 	-- assemble registers
 	-- source register 0: N divider and fractional division value
-	SOURCE_REG_0 <= MAX2871_DEF_0(31) & "000000000" & CONFIG_DATA(6 downto 0) & CONFIG_DATA(27 downto 16) & "000";
+	SOURCE_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(6 downto 0) & config_reg(27 downto 16) & "000";
 	-- source register 1: Modulus value
-	SOURCE_REG_1 <= MAX2871_DEF_1(31 downto 15) & CONFIG_DATA(39 downto 28) & "001";
+	SOURCE_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(39 downto 28) & "001";
 	-- source register 3: VCO selection
-	SOURCE_REG_3 <= CONFIG_DATA(12 downto 7) & MAX2871_DEF_3(25 downto 3) & "011";
+	SOURCE_REG_3 <= config_reg(12 downto 7) & MAX2871_DEF_3(25 downto 3) & "011";
 	-- output power A passed on from default registers, output B disabled
-	SOURCE_REG_4 <= MAX2871_DEF_4(31 downto 23) & CONFIG_DATA(15 downto 13) & MAX2871_DEF_4(19 downto 9) & "000" & MAX2871_DEF_4(5 downto 3) & "100";
+	SOURCE_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(15 downto 13) & MAX2871_DEF_4(19 downto 9) & "000" & MAX2871_DEF_4(5 downto 3) & "100";
 	
 	-- LO register 0: N divider and fractional division value
-	LO_REG_0 <= MAX2871_DEF_0(31) & "000000000" & CONFIG_DATA(54 downto 48) & CONFIG_DATA(75 downto 64) & "000";
+	LO_REG_0 <= MAX2871_DEF_0(31) & "000000000" & config_reg(54 downto 48) & config_reg(75 downto 64) & "000";
 	-- LO register 1: Modulus value
-	LO_REG_1 <= MAX2871_DEF_1(31 downto 15) & CONFIG_DATA(87 downto 76) & "001";
+	LO_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(87 downto 76) & "001";
 	-- LO register 3: VCO selection
-	LO_REG_3 <= CONFIG_DATA(60 downto 55) & MAX2871_DEF_3(25 downto 3) & "011";
+	LO_REG_3 <= config_reg(60 downto 55) & MAX2871_DEF_3(25 downto 3) & "011";
 	-- both outputs enabled at +5dbm
-	LO_REG_4 <= MAX2871_DEF_4(31 downto 23) & CONFIG_DATA(63 downto 61) & MAX2871_DEF_4(19 downto 9) & "111111100";
+	LO_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(63 downto 61) & MAX2871_DEF_4(19 downto 9) & "111111100";
 	
-	ATTENUATOR <= CONFIG_DATA(46 downto 40);
+	ATTENUATOR <= config_reg(46 downto 40);
-	SOURCE_FILTER <= CONFIG_DATA(89 downto 88);
+	SOURCE_FILTER <= config_reg(89 downto 88);
-	BAND_SELECT <= CONFIG_DATA(47);
+	BAND_SELECT <= config_reg(47);
 							
-	settling_time <= 	to_unsigned(2048, 16) when CONFIG_DATA(94 downto 93) = "00" else -- 20us
+	NSAMPLES <= USER_NSAMPLES when config_reg(92 downto 90) = "000" else
-							to_unsigned(6144, 16) when CONFIG_DATA(94 downto 93) = "01" else -- 60us
+					std_logic_vector(to_unsigned(6, 13)) when config_reg(92 downto 90) = "001" else
-							to_unsigned(18432, 16) when CONFIG_DATA(94 downto 93) = "10" else -- 180us
+					std_logic_vector(to_unsigned(19, 13)) when config_reg(92 downto 90) = "010" else
-							to_unsigned(55296, 16); -- 540us
+					std_logic_vector(to_unsigned(57, 13)) when config_reg(92 downto 90) = "011" else
-							
+					std_logic_vector(to_unsigned(190, 13)) when config_reg(92 downto 90) = "100" else
-	NSAMPLES <= USER_NSAMPLES when CONFIG_DATA(92 downto 90) = "000" else
+					std_logic_vector(to_unsigned(571, 13)) when config_reg(92 downto 90) = "101" else
-					std_logic_vector(to_unsigned(6, 13)) when CONFIG_DATA(92 downto 90) = "001" else
+					std_logic_vector(to_unsigned(1904, 13)) when config_reg(92 downto 90) = "110" else
-					std_logic_vector(to_unsigned(19, 13)) when CONFIG_DATA(92 downto 90) = "010" else
-					std_logic_vector(to_unsigned(57, 13)) when CONFIG_DATA(92 downto 90) = "011" else
-					std_logic_vector(to_unsigned(190, 13)) when CONFIG_DATA(92 downto 90) = "100" else
-					std_logic_vector(to_unsigned(571, 13)) when CONFIG_DATA(92 downto 90) = "101" else
-					std_logic_vector(to_unsigned(1904, 13)) when CONFIG_DATA(92 downto 90) = "110" else
 					std_logic_vector(to_unsigned(5712, 13));
 	
 	DEBUG_STATUS(10 downto 8) <= "000" when state = TriggerSetup else
@@ -136,6 +132,8 @@ begin
 	DEBUG_STATUS(5) <= SAMPLING_BUSY;
 	DEBUG_STATUS(4 downto 0) <= (others => '1');
 
+	config_reg <= CONFIG_DATA;
+
 	process(CLK, RESET)
 	begin
 		if rising_edge(CLK) then
@@ -154,21 +152,25 @@ begin
 							state <= SettingUp;
 						end if;
 					when SettingUp =>
-						-- highest bit in CONFIG_DATA determines whether the sweep should be halted prior to sampling
+						-- highest bit in config_reg determines whether the sweep should be halted prior to sampling
-						SWEEP_HALTED <= CONFIG_DATA(95);
+						SWEEP_HALTED <= config_reg(95);
 						RELOAD_PLL_REGS <= '0';
+						case config_reg(94 downto 93) is 
+							when "00" => settling_time <= to_unsigned(2048, 16); -- 20us
+							when "01" => settling_time <= to_unsigned(6144, 16); -- 60us
+							when "10" => settling_time <= to_unsigned(18432, 16); -- 180us
+							when others => settling_time <= to_unsigned(55296, 16); -- 540us
+						end case;
+						settling_cnt <= settling_time;
 						if PLL_RELOAD_DONE = '1' and PLL_LOCKED = '1' then
 							-- check if halted sweep is resumed
-							if CONFIG_DATA(95) = '0' or SWEEP_RESUME = '1' then
+							if config_reg(95) = '0' or SWEEP_RESUME = '1' then
 								SWEEP_HALTED <= '0';
 								if EXCITE_PORT1 = '1' then
 									state <= SettlingPort1;
-								elsif EXCITE_PORT2 = '1' then
-									state <= SettlingPort2;
 								else
-									state <= Done;
+									state <= SettlingPort2;
 								end if;
-								settling_cnt <= settling_time;
 							end if;
 						end if;
 					when SettlingPort1 =>
@@ -192,7 +194,7 @@ begin
 							else
 								state <= NextPoint;
 							end if;
-							settling_cnt <= unsigned(SETTLING_TIME);
+							settling_cnt <= settling_time;
 						end if;
 					when SettlingPort2 =>
 						PORT_SELECT <= '0';

FPGA/VNA/Test_DFT.vhd

@@ -47,11 +47,9 @@ ARCHITECTURE behavior OF Test_DFT IS
          PORT1 : IN  std_logic_vector(15 downto 0);
          PORT2 : IN  std_logic_vector(15 downto 0);
          NEW_SAMPLE : IN  std_logic;
-			NSAMPLES : in STD_LOGIC_VECTOR (15 downto 0);
+			NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
          BIN1_PHASEINC : IN  std_logic_vector(15 downto 0);
          DIFFBIN_PHASEINC : IN  std_logic_vector(15 downto 0);
-         WINDOW_INC : IN  std_logic_vector(15 downto 0);
-         WINDOW_TYPE : IN  std_logic_vector(1 downto 0);
          RESULT_READY : OUT  std_logic;
          OUTPUT : out  STD_LOGIC_VECTOR (191 downto 0);
          NEXT_OUTPUT : IN  std_logic
@@ -67,10 +65,8 @@ ARCHITECTURE behavior OF Test_DFT IS
    signal NEW_SAMPLE : std_logic := '0';
    signal BIN1_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
    signal DIFFBIN_PHASEINC : std_logic_vector(15 downto 0) := (others => '0');
-   signal WINDOW_INC : std_logic_vector(15 downto 0) := (others => '0');
-   signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0');
    signal NEXT_OUTPUT : std_logic := '0';
-	signal NSAMPLES : STD_LOGIC_VECTOR (15 downto 0);
+	signal NSAMPLES : STD_LOGIC_VECTOR (12 downto 0);
 
  	--Outputs
    signal RESULT_READY : std_logic;
@@ -93,8 +89,6 @@ BEGIN
 			 NSAMPLES => NSAMPLES,
           BIN1_PHASEINC => BIN1_PHASEINC,
           DIFFBIN_PHASEINC => DIFFBIN_PHASEINC,
-          WINDOW_INC => WINDOW_INC,
-          WINDOW_TYPE => WINDOW_TYPE,
           RESULT_READY => RESULT_READY,
           OUTPUT => OUTPUT,
           NEXT_OUTPUT => NEXT_OUTPUT
@@ -119,7 +113,6 @@ BEGIN
 		PORT2 <= "0100000000000000";
 		BIN1_PHASEINC <= "0100000000000000";
 		DIFFBIN_PHASEINC <= "0010000000000000";
-		WINDOW_INC <= "0000100000000000";
 		NSAMPLES <= "0000000000000011";
       wait for 100 ns;	
 		RESET <= '0';
@@ -128,7 +121,7 @@ BEGIN
 		wait for CLK_period;
 		NEW_SAMPLE <= '0';
 		while True loop
-			wait for CLK_period * 111;
+			wait for CLK_period * 79;
 			NEW_SAMPLE <= '1';
 			wait for CLK_period;
 			NEW_SAMPLE <= '0';

FPGA/VNA/Test_Windowing.vhd

@@ -0,0 +1,135 @@
+--------------------------------------------------------------------------------
+-- Company: 
+-- Engineer:
+--
+-- Create Date:   18:37:51 11/06/2020
+-- Design Name:   
+-- Module Name:   /home/jan/Projekte/VNA2/FPGA/VNA/Test_Windowing.vhd
+-- Project Name:  VNA
+-- Target Device:  
+-- Tool versions:  
+-- Description:   
+-- 
+-- VHDL Test Bench Created by ISE for module: Windowing
+-- 
+-- Dependencies:
+-- 
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes: 
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation 
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY Test_Windowing IS
+END Test_Windowing;
+ 
+ARCHITECTURE behavior OF Test_Windowing IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT Windowing
+    PORT(
+         CLK : IN  std_logic;
+         RESET : IN  std_logic;
+         WINDOW_TYPE : IN  std_logic_vector(1 downto 0);
+         PORT1_RAW : IN  std_logic_vector(15 downto 0);
+         PORT2_RAW : IN  std_logic_vector(15 downto 0);
+         REF_RAW : IN  std_logic_vector(15 downto 0);
+         ADC_READY : IN  std_logic;
+         PORT1_WINDOWED : OUT  std_logic_vector(15 downto 0);
+         PORT2_WINDOWED : OUT  std_logic_vector(15 downto 0);
+         REF_WINDOWED : OUT  std_logic_vector(15 downto 0);
+         WINDOWING_DONE : OUT  std_logic;
+         NSAMPLES : IN  std_logic_vector(12 downto 0)
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal CLK : std_logic := '0';
+   signal RESET : std_logic := '0';
+   signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0');
+   signal PORT1_RAW : std_logic_vector(15 downto 0) := (others => '0');
+   signal PORT2_RAW : std_logic_vector(15 downto 0) := (others => '0');
+   signal REF_RAW : std_logic_vector(15 downto 0) := (others => '0');
+   signal ADC_READY : std_logic := '0';
+   signal NSAMPLES : std_logic_vector(12 downto 0) := (others => '0');
+
+ 	--Outputs
+   signal PORT1_WINDOWED : std_logic_vector(15 downto 0);
+   signal PORT2_WINDOWED : std_logic_vector(15 downto 0);
+   signal REF_WINDOWED : std_logic_vector(15 downto 0);
+   signal WINDOWING_DONE : std_logic;
+
+   -- Clock period definitions
+   constant CLK_period : time := 10 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: Windowing PORT MAP (
+          CLK => CLK,
+          RESET => RESET,
+          WINDOW_TYPE => WINDOW_TYPE,
+          PORT1_RAW => PORT1_RAW,
+          PORT2_RAW => PORT2_RAW,
+          REF_RAW => REF_RAW,
+          ADC_READY => ADC_READY,
+          PORT1_WINDOWED => PORT1_WINDOWED,
+          PORT2_WINDOWED => PORT2_WINDOWED,
+          REF_WINDOWED => REF_WINDOWED,
+          WINDOWING_DONE => WINDOWING_DONE,
+          NSAMPLES => NSAMPLES
+        );
+
+   -- Clock process definitions
+   CLK_process :process
+   begin
+		CLK <= '0';
+		wait for CLK_period/2;
+		CLK <= '1';
+		wait for CLK_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state for 100 ns.
+      wait for 100 ns;	
+
+      wait for CLK_period*10;
+
+      -- insert stimulus here 
+		WINDOW_TYPE <= "10";
+		NSAMPLES <= "0000000010001";
+		PORT1_RAW <= "0000000010000000";
+		PORT2_RAW <= "0000000100000000";
+		REF_RAW <= "0000001000000000";
+		ADC_READY <= '0';
+		RESET <= '1';
+		wait for CLK_period;
+		RESET <= '0';
+		for i in 0 to 271	loop
+			wait for CLK_period*111;
+			ADC_READY <= '1';
+			wait for CLK_period;
+			ADC_READY <= '0';
+		end loop;
+
+      wait;
+   end process;
+
+END;

FPGA/VNA/VNA.gise

@@ -39,9 +39,7 @@
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="Sampling_xst.xrpt"/>
     <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Sweep.vhi"/>
     <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
-    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_DFT_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_DFT_isim_beh.wdb"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
@@ -51,7 +49,12 @@
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Window_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Windowing_beh.prj"/>
+    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Windowing_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Windowing_isim_beh.wdb"/>
+    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Windowing_stx_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_top_isim_beh.exe"/>
+    <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Windowing.vhi"/>
     <file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
@@ -68,7 +71,6 @@
     <file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
-    <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
@@ -129,7 +131,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604520805" xil_pn:in_ck="2193033869104949559" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1604520805">
+    <transform xil_pn:end_ts="1604688338" xil_pn:in_ck="7920041737510621142" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1604688338">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -154,22 +156,25 @@
       <outfile xil_pn:name="Test_SinCos.vhd"/>
       <outfile xil_pn:name="Test_Sync.vhd"/>
       <outfile xil_pn:name="Test_Window.vhd"/>
-      <outfile xil_pn:name="dft_result.vhd"/>
+      <outfile xil_pn:name="Test_Windowing.vhd"/>
+      <outfile xil_pn:name="Windowing.vhd"/>
       <outfile xil_pn:name="spi_slave.vhd"/>
       <outfile xil_pn:name="top.vhd"/>
       <outfile xil_pn:name="window.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1604520805" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5354180755060525133" xil_pn:start_ts="1604520805">
+    <transform xil_pn:end_ts="1604684486" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="1671761620692912459" xil_pn:start_ts="1604684486">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604520805" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4601062479098204721" xil_pn:start_ts="1604520805">
+    <transform xil_pn:end_ts="1604684486" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="6847665263640105929" xil_pn:start_ts="1604684486">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604498987" xil_pn:in_ck="-1881940375859338364" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604498987">
+    <transform xil_pn:end_ts="1604671666" xil_pn:in_ck="6306144844996157057" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604671665">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
+      <outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
       <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
       <outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
@@ -180,7 +185,7 @@
       <outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
       <outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1604520805" xil_pn:in_ck="3333396920699583347" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1604520805">
+    <transform xil_pn:end_ts="1604684548" xil_pn:in_ck="2301248572745587975" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1604684548">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -206,7 +211,9 @@
       <outfile xil_pn:name="Test_SinCos.vhd"/>
       <outfile xil_pn:name="Test_Sync.vhd"/>
       <outfile xil_pn:name="Test_Window.vhd"/>
-      <outfile xil_pn:name="dft_result.vhd"/>
+      <outfile xil_pn:name="Test_Windowing.vhd"/>
+      <outfile xil_pn:name="Windowing.vhd"/>
+      <outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
       <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
@@ -216,7 +223,7 @@
       <outfile xil_pn:name="top.vhd"/>
       <outfile xil_pn:name="window.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1604520811" xil_pn:in_ck="3333396920699583347" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-5642200015192194106" xil_pn:start_ts="1604520805">
+    <transform xil_pn:end_ts="1604684552" xil_pn:in_ck="2301248572745587975" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="7968903525862259638" xil_pn:start_ts="1604684548">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -224,22 +231,20 @@
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_DFT_beh.prj"/>
+      <outfile xil_pn:name="Test_Windowing_beh.prj"/>
-      <outfile xil_pn:name="Test_DFT_isim_beh.exe"/>
+      <outfile xil_pn:name="Test_Windowing_isim_beh.exe"/>
       <outfile xil_pn:name="fuse.log"/>
       <outfile xil_pn:name="isim"/>
-      <outfile xil_pn:name="isim.log"/>
       <outfile xil_pn:name="xilinxsim.ini"/>
     </transform>
-    <transform xil_pn:end_ts="1604520811" xil_pn:in_ck="-3358899429776077154" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8724408846642916045" xil_pn:start_ts="1604520811">
+    <transform xil_pn:end_ts="1604684553" xil_pn:in_ck="-2626831050236864990" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-4828419273139430045" xil_pn:start_ts="1604684552">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_DFT_isim_beh.wdb"/>
+      <outfile xil_pn:name="Test_Windowing_isim_beh.wdb"/>
       <outfile xil_pn:name="isim.cmd"/>
-      <outfile xil_pn:name="isim.log"/>
     </transform>
     <transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1600270761">
       <status xil_pn:value="SuccessfullyRun"/>
@@ -249,9 +254,11 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604440718" xil_pn:in_ck="-1881940375859338364" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604440718">
+    <transform xil_pn:end_ts="1604675434" xil_pn:in_ck="6306144844996157057" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604675434">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="ipcore_dir/DSP_SLICE.ngc"/>
+      <outfile xil_pn:name="ipcore_dir/DSP_SLICE.vhd"/>
       <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
       <outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
@@ -278,8 +285,9 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604523374" xil_pn:in_ck="-7635529597152014087" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1604523352">
+    <transform xil_pn:end_ts="1604704764" xil_pn:in_ck="-480514955089580632" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1604704739">
       <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
@@ -295,11 +303,11 @@
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1604436130" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1604436130">
+    <transform xil_pn:end_ts="1604691275" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1604691275">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1604523381" xil_pn:in_ck="-3571942932097917307" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1604523374">
+    <transform xil_pn:end_ts="1604704771" xil_pn:in_ck="-614491687805493712" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1604704764">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_ngo"/>
@@ -308,7 +316,7 @@
       <outfile xil_pn:name="top.ngd"/>
       <outfile xil_pn:name="top_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1604523453" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-7036854207931970956" xil_pn:start_ts="1604523381">
+    <transform xil_pn:end_ts="1604704833" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1604704771">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -322,7 +330,7 @@
       <outfile xil_pn:name="top_summary.xml"/>
       <outfile xil_pn:name="top_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1604523487" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1604523453">
+    <transform xil_pn:end_ts="1604704864" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1604704833">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@@ -336,7 +344,7 @@
       <outfile xil_pn:name="top_pad.txt"/>
       <outfile xil_pn:name="top_par.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1604523501" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1604523487">
+    <transform xil_pn:end_ts="1604704879" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1604704864">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -390,7 +398,7 @@
       <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="InputRemoved"/>
     </transform>
-    <transform xil_pn:end_ts="1604523487" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1604523479">
+    <transform xil_pn:end_ts="1604704864" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1604704856">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

FPGA/VNA/VNA.xise

@@ -17,14 +17,14 @@
   <files>
     <file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -34,22 +34,22 @@
     </file>
     <file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="ipcore_dir/SweepConfigMem.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="ipcore_dir/SinCosMult.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="Test_Sampling.vhd" xil_pn:type="FILE_VHDL">
@@ -64,15 +64,15 @@
     </file>
     <file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -100,7 +100,7 @@
     </file>
     <file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -114,7 +114,7 @@
     </file>
     <file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="window.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
@@ -127,23 +127,33 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="139"/>
     </file>
     <file xil_pn:name="DFT.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="Test_DFT.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="144"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="144"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="144"/>
     </file>
-    <file xil_pn:name="dft_result.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
-    </file>
     <file xil_pn:name="ipcore_dir/result_bram.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
+    <file xil_pn:name="ipcore_dir/DSP_SLICE.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+    </file>
+    <file xil_pn:name="Windowing.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+    </file>
+    <file xil_pn:name="Test_Windowing.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="176"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="176"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="176"/>
+    </file>
     <file xil_pn:name="ipcore_dir/SweepConfigMem.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
@@ -159,6 +169,9 @@
     <file xil_pn:name="ipcore_dir/result_bram.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="ipcore_dir/DSP_SLICE.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
   </files>
 
   <properties>
@@ -226,8 +239,8 @@
     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="4" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -345,7 +358,7 @@
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -403,8 +416,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_DFT" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_Windowing" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_Windowing" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -422,7 +435,7 @@
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_Windowing" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -454,7 +467,7 @@
     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="For Packing Only" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -474,7 +487,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_DFT|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_Windowing|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

FPGA/VNA/Windowing.vhd

@@ -0,0 +1,201 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    18:18:17 11/06/2020 
+-- Design Name: 
+-- Module Name:    Windowing - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity Windowing is
+    Port ( CLK : in  STD_LOGIC;
+           RESET : in  STD_LOGIC;
+           WINDOW_TYPE : in  STD_LOGIC_VECTOR (1 downto 0);
+           PORT1_RAW : in  STD_LOGIC_VECTOR (15 downto 0);
+           PORT2_RAW : in  STD_LOGIC_VECTOR (15 downto 0);
+           REF_RAW : in  STD_LOGIC_VECTOR (15 downto 0);
+           ADC_READY : in  STD_LOGIC;
+           PORT1_WINDOWED : out  STD_LOGIC_VECTOR (15 downto 0);
+           PORT2_WINDOWED : out  STD_LOGIC_VECTOR (15 downto 0);
+           REF_WINDOWED : out  STD_LOGIC_VECTOR (15 downto 0);
+           WINDOWING_DONE : out  STD_LOGIC;
+           NSAMPLES : in  STD_LOGIC_VECTOR (12 downto 0));
+end Windowing;
+
+architecture Behavioral of Windowing is
+COMPONENT window
+PORT(
+	CLK : IN std_logic;
+	INDEX : IN std_logic_vector(6 downto 0);
+	WINDOW_TYPE : IN std_logic_vector(1 downto 0);          
+	VALUE : OUT std_logic_vector(15 downto 0)
+	);
+END COMPONENT;
+COMPONENT DSP_SLICE
+  PORT (
+    clk : IN STD_LOGIC;
+    ce : IN STD_LOGIC;
+    sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+    b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
+    c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
+    p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
+  );
+END COMPONENT;
+	signal window_index : std_logic_vector(6 downto 0);
+	signal window_value : std_logic_vector(15 downto 0);
+	signal window_sample_cnt : integer range -8 to 8191;
+	signal window_index_inc : integer range 0 to 8;
+	signal window_sample_compare : integer range 0 to 8191;
+	signal window_sample_cnt_inc : integer range 0 to 8;
+	
+	signal mult_a : std_logic_vector(17 downto 0);
+	signal mult_b : std_logic_vector(17 downto 0);
+	signal mult_p : std_logic_vector(47 downto 0);
+	signal mult_enable : std_logic;
+	
+	type states is (CalcWindowInc, WaitingForADC, CalcPort1, CalcPort2, CalcRef, MultDelay1, MultDelay2, StorePort1, StorePort2, StoreRef);
+	signal state : states;
+begin
+
+	Mult : DSP_SLICE
+	PORT MAP (
+		clk => CLK,
+		ce => mult_enable,
+		sel => "0",
+		a => mult_a,
+		b => mult_b,
+		c => (others => '0'),
+		p => mult_p
+	);
+	WindowROM: window PORT MAP(
+		CLK => CLK,
+		INDEX => window_index,
+		WINDOW_TYPE => WINDOW_TYPE,
+		VALUE => window_value
+	);
+	-- sign extend multiplier inputs
+	mult_a(17 downto 16) <= mult_a(15) & mult_a(15);
+	mult_b(17 downto 16) <= mult_b(15) & mult_b(15);
+	
+	mult_a(15 downto 0) <= window_value;
+
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			if RESET = '1' then
+				WINDOWING_DONE <= '0';
+				state <= CalcWindowInc;
+				mult_enable <= '0';
+				mult_b(15 downto 0) <= (others => '0');
+				window_index <= (others => '0');
+				window_sample_cnt <= 0;
+				window_sample_compare <= to_integer(unsigned(NSAMPLES));
+			else
+				case state is
+					when CalcWindowInc =>
+						case window_sample_compare is
+						when 1 =>
+							-- 16 samples, increment on every sample by 8
+							window_sample_cnt_inc <= 1;
+							window_index_inc <= 8;
+						when 2 to 3 =>
+							-- 32-48 samples, increment by 4
+							window_sample_cnt_inc <= 2;
+							window_index_inc <= 4;
+						when 4 to 7 =>
+							-- 64-112 samples, increment by 2
+							window_sample_cnt_inc <= 4;
+							window_index_inc <= 2;									
+						when others =>
+							-- 128 or more samples, increment by 1
+							window_sample_cnt_inc <= 8;
+							window_index_inc <= 1;
+					end case;
+					state <= WaitingForADC;
+				when WaitingForADC =>
+					WINDOWING_DONE <= '0';
+					mult_enable <= '0';
+					mult_b(15 downto 0) <= (others => '0');
+					if ADC_READY = '1' then
+						state <= CalcPort1;
+					end if;
+				when CalcPort1 =>
+					WINDOWING_DONE <= '0';
+					mult_enable <= '1';
+					mult_b(15 downto 0) <= PORT1_RAW;
+					state <= CalcPort2;
+				when CalcPort2 =>
+					WINDOWING_DONE <= '0';
+					mult_enable <= '1';
+					mult_b(15 downto 0) <= PORT2_RAW;
+					state <= CalcRef;
+				when CalcRef =>
+					WINDOWING_DONE <= '0';
+					mult_enable <= '1';
+					mult_b(15 downto 0) <= REF_RAW;
+					state <= MultDelay1;
+				when MultDelay1 =>
+					WINDOWING_DONE <= '0';
+					mult_enable <= '1';
+					mult_b(15 downto 0) <= (others => '0');
+					state <= MultDelay2;
+				when MultDelay2 =>
+					WINDOWING_DONE <= '0';
+					mult_enable <= '1';
+					mult_b(15 downto 0) <= (others => '0');
+					state <= StorePort1;
+				when StorePort1 =>
+					WINDOWING_DONE <= '0';
+					mult_enable <= '1';
+					mult_b(15 downto 0) <= (others => '0');
+					PORT1_WINDOWED <= mult_p(30 downto 15); 
+					state <= StorePort2;
+				when StorePort2 =>
+					WINDOWING_DONE <= '0';
+					mult_enable <= '1';
+					mult_b(15 downto 0) <= (others => '0');
+					PORT2_WINDOWED <= mult_p(30 downto 15);
+					state <= StoreRef;
+				when StoreRef =>
+					WINDOWING_DONE <= '1';
+					mult_enable <= '0';
+					mult_b(15 downto 0) <= (others => '0');
+					REF_WINDOWED <= mult_p(30 downto 15);
+					-- update window increment
+					if window_sample_cnt + window_sample_cnt_inc < window_sample_compare then
+						window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc;
+					else
+						window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc - window_sample_compare;
+						window_index <= std_logic_vector( unsigned(window_index) + window_index_inc );
+					end if;					
+					state <= WaitingForADC;
+				end case;
+			end if;
+		end if;
+	end process;
+
+end Behavioral;
+

FPGA/VNA/dft_result.vhd

@@ -1,56 +0,0 @@
-----------------------------------------------------------------------------------
--- Company: 
--- Engineer: 
--- 
--- Create Date:    22:01:17 11/03/2020 
--- Design Name: 
--- Module Name:    dft_result - Behavioral 
--- Project Name: 
--- Target Devices: 
--- Tool versions: 
--- Description: 
---
--- Dependencies: 
---
--- Revision: 
--- Revision 0.01 - File Created
--- Additional Comments: 
---
-----------------------------------------------------------------------------------
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
-use IEEE.NUMERIC_STD.ALL;
-
--- Uncomment the following library declaration if instantiating
--- any Xilinx primitives in this code.
---library UNISIM;
---use UNISIM.VComponents.all;
-
-entity dft_result is
-	 Generic (depth : integer);
-    Port ( CLK : in  STD_LOGIC;
-           READ_ADDRESS : in integer range 0 to depth-1;
-           WRITE_ADDRESS : in integer range 0 to depth-1;
-           DATA_IN : in  STD_LOGIC_VECTOR (191 downto 0);
-           DATA_OUT : out  STD_LOGIC_VECTOR (191 downto 0);
-           WE : in  STD_LOGIC);
-end dft_result;
-
-architecture rtl of dft_result is
-	type memory is array(depth-1 downto 0) of std_logic_vector(191 downto 0);
-	signal ram : memory;
-begin
-	process(CLK)
-	begin
-		if rising_edge(CLK) then
-			DATA_OUT <= ram(READ_ADDRESS);
-			if(WE = '1') then
-				ram(WRITE_ADDRESS) <= DATA_IN;
-			end if;
-		end if;
-	end process;
-end rtl;
-

FPGA/VNA/ipcore_dir/DSP48.xco

@@ -0,0 +1,136 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Fri Nov  6 13:56:17 2020
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:xbip_dsp48_macro:2.1
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT DSP48_Macro xilinx.com:ip:xbip_dsp48_macro:2.1
+# END Select
+# BEGIN Parameters
+CSET a_binarywidth=0
+CSET a_width=18
+CSET areg_1=false
+CSET areg_2=false
+CSET areg_3=true
+CSET areg_4=true
+CSET b_binarywidth=0
+CSET b_width=18
+CSET breg_1=false
+CSET breg_2=false
+CSET breg_3=true
+CSET breg_4=true
+CSET c_binarywidth=0
+CSET c_width=48
+CSET cinreg_1=false
+CSET cinreg_2=false
+CSET cinreg_3=false
+CSET cinreg_4=false
+CSET cinreg_5=false
+CSET component_name=DSP48
+CSET concat_binarywidth=0
+CSET concat_width=48
+CSET concatreg_3=false
+CSET concatreg_4=false
+CSET concatreg_5=false
+CSET creg_1=false
+CSET creg_2=false
+CSET creg_3=true
+CSET creg_4=true
+CSET creg_5=true
+CSET d_binarywidth=0
+CSET d_width=18
+CSET dreg_1=false
+CSET dreg_2=false
+CSET dreg_3=false
+CSET gui_behaviour=Coregen
+CSET has_a_ce=false
+CSET has_a_sclr=false
+CSET has_acout=false
+CSET has_b_ce=false
+CSET has_b_sclr=false
+CSET has_bcout=false
+CSET has_c_ce=false
+CSET has_c_sclr=false
+CSET has_carrycascout=false
+CSET has_carryout=false
+CSET has_ce=true
+CSET has_concat_ce=false
+CSET has_concat_sclr=false
+CSET has_d_ce=false
+CSET has_d_sclr=false
+CSET has_m_ce=false
+CSET has_m_sclr=false
+CSET has_p_ce=false
+CSET has_p_sclr=false
+CSET has_pcout=false
+CSET has_sclr=false
+CSET has_sel_ce=false
+CSET has_sel_sclr=false
+CSET instruction1=A*B
+CSET instruction2=A*B+C
+CSET instruction3=#
+CSET instruction4=#
+CSET instruction5=#
+CSET instruction6=#
+CSET instruction7=#
+CSET instruction8=#
+CSET instruction_list=#
+CSET mreg_5=true
+CSET opreg_1=false
+CSET opreg_2=false
+CSET opreg_3=true
+CSET opreg_4=true
+CSET opreg_5=true
+CSET output_properties=Full_Precision
+CSET p_binarywidth=0
+CSET p_full_width=48
+CSET p_width=48
+CSET pcin_binarywidth=0
+CSET pipeline_options=Automatic
+CSET preg_6=true
+CSET show_filtered=false
+CSET tier_1=false
+CSET tier_2=false
+CSET tier_3=false
+CSET tier_4=false
+CSET tier_5=false
+CSET tier_6=false
+CSET use_dsp48=true
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-05T14:23:53Z
+# END Extra information
+GENERATE
+# CRC: 2ca4f824

FPGA/VNA/ipcore_dir/DSP48.xise

@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="DSP48.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="DSP48.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DSP48|DSP48_a" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="DSP48.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DSP48" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="DSP48" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-11-06T14:56:38" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="134E6A8E8B8A97C235E2A00FC956CC90" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>

FPGA/VNA/ipcore_dir/DSP_SLICE.xco

@@ -0,0 +1,136 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Fri Nov  6 13:57:46 2020
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:xbip_dsp48_macro:2.1
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT DSP48_Macro xilinx.com:ip:xbip_dsp48_macro:2.1
+# END Select
+# BEGIN Parameters
+CSET a_binarywidth=0
+CSET a_width=18
+CSET areg_1=false
+CSET areg_2=false
+CSET areg_3=true
+CSET areg_4=true
+CSET b_binarywidth=0
+CSET b_width=18
+CSET breg_1=false
+CSET breg_2=false
+CSET breg_3=true
+CSET breg_4=true
+CSET c_binarywidth=0
+CSET c_width=48
+CSET cinreg_1=false
+CSET cinreg_2=false
+CSET cinreg_3=false
+CSET cinreg_4=false
+CSET cinreg_5=false
+CSET component_name=DSP_SLICE
+CSET concat_binarywidth=0
+CSET concat_width=48
+CSET concatreg_3=false
+CSET concatreg_4=false
+CSET concatreg_5=false
+CSET creg_1=false
+CSET creg_2=false
+CSET creg_3=true
+CSET creg_4=true
+CSET creg_5=true
+CSET d_binarywidth=0
+CSET d_width=18
+CSET dreg_1=false
+CSET dreg_2=false
+CSET dreg_3=false
+CSET gui_behaviour=Coregen
+CSET has_a_ce=false
+CSET has_a_sclr=false
+CSET has_acout=false
+CSET has_b_ce=false
+CSET has_b_sclr=false
+CSET has_bcout=false
+CSET has_c_ce=false
+CSET has_c_sclr=false
+CSET has_carrycascout=false
+CSET has_carryout=false
+CSET has_ce=true
+CSET has_concat_ce=false
+CSET has_concat_sclr=false
+CSET has_d_ce=false
+CSET has_d_sclr=false
+CSET has_m_ce=false
+CSET has_m_sclr=false
+CSET has_p_ce=false
+CSET has_p_sclr=false
+CSET has_pcout=false
+CSET has_sclr=false
+CSET has_sel_ce=false
+CSET has_sel_sclr=false
+CSET instruction1=A*B
+CSET instruction2=A*B+C
+CSET instruction3=#
+CSET instruction4=#
+CSET instruction5=#
+CSET instruction6=#
+CSET instruction7=#
+CSET instruction8=#
+CSET instruction_list=#
+CSET mreg_5=true
+CSET opreg_1=false
+CSET opreg_2=false
+CSET opreg_3=true
+CSET opreg_4=true
+CSET opreg_5=true
+CSET output_properties=Full_Precision
+CSET p_binarywidth=0
+CSET p_full_width=48
+CSET p_width=48
+CSET pcin_binarywidth=0
+CSET pipeline_options=Automatic
+CSET preg_6=true
+CSET show_filtered=false
+CSET tier_1=false
+CSET tier_2=false
+CSET tier_3=false
+CSET tier_4=false
+CSET tier_5=false
+CSET tier_6=false
+CSET use_dsp48=true
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-05T14:23:53Z
+# END Extra information
+GENERATE
+# CRC: 57648294

FPGA/VNA/ipcore_dir/DSP_SLICE.xise

@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="DSP_SLICE.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="DSP_SLICE.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|DSP_SLICE|DSP_SLICE_a" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="DSP_SLICE.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/DSP_SLICE" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="DSP_SLICE" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-11-06T14:58:06" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="E54C6A9B0DFD393EEACC284C7E05AF9E" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>

FPGA/VNA/top.vhd

@@ -145,6 +145,24 @@ architecture Behavioral of top is
 		DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0)
 		);
 	END COMPONENT;
+	
+	COMPONENT Windowing
+	PORT(
+		CLK : IN std_logic;
+		RESET : IN std_logic;
+		WINDOW_TYPE : IN std_logic_vector(1 downto 0);
+		PORT1_RAW : IN std_logic_vector(15 downto 0);
+		PORT2_RAW : IN std_logic_vector(15 downto 0);
+		REF_RAW : IN std_logic_vector(15 downto 0);
+		ADC_READY : IN std_logic;
+		NSAMPLES : IN std_logic_vector(12 downto 0);          
+		PORT1_WINDOWED : OUT std_logic_vector(15 downto 0);
+		PORT2_WINDOWED : OUT std_logic_vector(15 downto 0);
+		REF_WINDOWED : OUT std_logic_vector(15 downto 0);
+		WINDOWING_DONE : OUT std_logic
+		);
+	END COMPONENT;
+	
 	COMPONENT Sampling
 	Generic(CLK_CYCLES_PRE_DONE : integer);
 	PORT(
@@ -158,7 +176,6 @@ architecture Behavioral of top is
 		NEW_SAMPLE : IN std_logic;
 		START : IN std_logic;
 		SAMPLES : IN std_logic_vector(12 downto 0);
-		WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);		
 		ADC_START : OUT std_logic;
 		DONE : OUT std_logic;
 		PRE_DONE : OUT std_logic;
@@ -245,10 +262,8 @@ architecture Behavioral of top is
 		RESET_MINMAX : out STD_LOGIC;
 		SWEEP_HALTED : in STD_LOGIC;
 		SWEEP_RESUME : out STD_LOGIC;
-		DFT_NSAMPLES : out STD_LOGIC_VECTOR (15 downto 0);
 		DFT_BIN1_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
 		DFT_DIFFBIN_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
-		DFT_WINDOW_INC : out STD_LOGIC_VECTOR (15 downto 0);
 		DFT_RESULT_READY : in  STD_LOGIC;
 		DFT_OUTPUT : in  STD_LOGIC_VECTOR (191 downto 0);
 		DFT_NEXT_OUTPUT : out  STD_LOGIC;
@@ -265,11 +280,9 @@ architecture Behavioral of top is
 		PORT1 : IN std_logic_vector(15 downto 0);
 		PORT2 : IN std_logic_vector(15 downto 0);
 		NEW_SAMPLE : IN std_logic;
-		NSAMPLES : IN std_logic_vector(15 downto 0);
+		NSAMPLES : IN std_logic_vector(12 downto 0);
 		BIN1_PHASEINC : IN std_logic_vector(15 downto 0);
 		DIFFBIN_PHASEINC : IN std_logic_vector(15 downto 0);
-		WINDOW_INC : IN std_logic_vector(15 downto 0);
-		WINDOW_TYPE : IN std_logic_vector(1 downto 0);
 		NEXT_OUTPUT : IN std_logic;          
 		RESULT_READY : OUT std_logic;
 		OUTPUT : OUT std_logic_vector(191 downto 0)
@@ -329,6 +342,11 @@ architecture Behavioral of top is
 	signal adc_minmax : std_logic_vector(95 downto 0);
 	signal adc_reset_minmax : std_logic;
 	
+	signal port1_windowed : std_logic_vector(15 downto 0);
+	signal port2_windowed : std_logic_vector(15 downto 0);
+	signal ref_windowed : std_logic_vector(15 downto 0);
+	signal windowing_ready : std_logic;
+	
 	-- Sampling signals
 	signal sampling_busy : std_logic;
 	signal sampling_done : std_logic;
@@ -394,10 +412,8 @@ architecture Behavioral of top is
 	signal intr : std_logic;
 	
 	-- DFT signals
-	signal dft_nsamples : std_logic_vector (15 downto 0);
 	signal dft_bin1_phaseinc : std_logic_vector (15 downto 0);
 	signal dft_diffbin_phaseinc : std_logic_vector (15 downto 0);
-	signal dft_window_inc : std_logic_vector (15 downto 0);
 	signal dft_ready : std_logic;
 	signal dft_output : std_logic_vector (191 downto 0);
 	signal dft_next_output : std_logic;
@@ -579,6 +595,22 @@ begin
 		SCLK => REF_SCLK
 	);
 	
+	
+	Windower: Windowing PORT MAP(
+		CLK => clk160,
+		RESET => sampling_start,
+		WINDOW_TYPE => sampling_window,
+		PORT1_RAW => adc_port1_data,
+		PORT2_RAW => adc_port2_data,
+		REF_RAW => adc_ref_data,
+		ADC_READY => adc_port1_ready,
+		PORT1_WINDOWED => port1_windowed,
+		PORT2_WINDOWED => port2_windowed,
+		REF_WINDOWED => ref_windowed,
+		WINDOWING_DONE => windowing_ready,
+		NSAMPLES => sampling_samples
+	);
+	
 	Sampler: Sampling
 	GENERIC MAP(CLK_CYCLES_PRE_DONE => 0)
 	PORT MAP(
@@ -586,16 +618,15 @@ begin
 		RESET => sweep_reset,
 		ADC_PRESCALER => sampling_prescaler,
 		PHASEINC => sampling_phaseinc,
-		PORT1 => adc_port1_data,
+		PORT1 => port1_windowed,
-		PORT2 => adc_port2_data,
+		PORT2 => port2_windowed,
-		REF => adc_ref_data,
+		REF => ref_windowed,
 		ADC_START => adc_trigger_sample,
-		NEW_SAMPLE => adc_port1_ready,
+		NEW_SAMPLE => windowing_ready,
 		DONE => sampling_done,
 		PRE_DONE => open,
 		START => sampling_start,
 		SAMPLES => sampling_samples,
-		WINDOW_TYPE => sampling_window,
 		PORT1_I => sampling_result(287 downto 240),
 		PORT1_Q => sampling_result(239 downto 192),
 		PORT2_I => sampling_result(191 downto 144),
@@ -614,7 +645,7 @@ begin
 		CONFIG_ADDRESS => sweep_config_address,
 		CONFIG_DATA => sweep_config_data,
 		USER_NSAMPLES => sampling_user_samples,
-		NSAMPLES => sampling_user_samples,
+		NSAMPLES => sampling_samples,
 		SAMPLING_BUSY => sampling_busy,
 		SAMPLING_DONE => sampling_done,
 		START_SAMPLING => sampling_start,
@@ -691,7 +722,7 @@ begin
 		SWEEP_ADDRESS => sweep_config_write_address,
 		SWEEP_WRITE => sweep_config_write,
 		SWEEP_POINTS => sweep_points,
-		NSAMPLES => sampling_samples,
+		NSAMPLES => sampling_user_samples,
 		PORT1_EN => port1mix_en,
 		PORT2_EN => port2mix_en,
 		REF_EN => refmix_en,
@@ -711,10 +742,8 @@ begin
 		SWEEP_RESUME => sweep_resume,
 		EXCITE_PORT1 => sweep_excite_port1,
 		EXCITE_PORT2 => sweep_excite_port2,
-		DFT_NSAMPLES => dft_nsamples,
 		DFT_BIN1_PHASEINC => dft_bin1_phaseinc,
 		DFT_DIFFBIN_PHASEINC => dft_diffbin_phaseinc,
-		DFT_WINDOW_INC => dft_window_inc,
 		DFT_RESULT_READY => dft_ready,
 		DFT_OUTPUT => dft_output,
 		DFT_NEXT_OUTPUT => dft_next_output,
@@ -728,14 +757,12 @@ begin
 	PORT MAP(
 		CLK => clk160,
 		RESET => dft_reset,
-		PORT1 => adc_port1_data,
+		PORT1 => port1_windowed,
-		PORT2 => adc_port2_data,
+		PORT2 => port2_windowed,
-		NEW_SAMPLE => adc_port1_ready,
+		NEW_SAMPLE => windowing_ready,
-		NSAMPLES => dft_nsamples,
+		NSAMPLES => sampling_samples,
 		BIN1_PHASEINC => dft_bin1_phaseinc,
 		DIFFBIN_PHASEINC => dft_diffbin_phaseinc,
-		WINDOW_INC => dft_window_inc,
-		WINDOW_TYPE => sampling_window,
 		RESULT_READY => dft_ready,
 		OUTPUT => dft_output,
 		NEXT_OUTPUT => dft_next_output

Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp

@@ -12,6 +12,7 @@
 static FPGA::HaltedCallback halted_cb;
 static uint16_t SysCtrlReg = 0x0000;
 static uint16_t ISRMaskReg = 0x0000;
+static uint32_t ADC_samplerate;
 
 using namespace FPGAHAL;
 
@@ -27,6 +28,9 @@ void FPGA::WriteRegister(FPGA::Reg reg, uint16_t value) {
 	Low(CS);
 	HAL_SPI_Transmit(&FPGA_SPI, (uint8_t*) cmd, 4, 100);
 	High(CS);
+	if(reg == Reg::ADCPrescaler) {
+		ADC_samplerate = Clockrate / value;
+	}
 }
 
 bool FPGA::Configure(Flash *f, uint32_t start_address, uint32_t bitstream_size) {
@@ -371,6 +375,23 @@ void FPGA::ResumeHaltedSweep() {
 	High(CS);
 }
 
+void FPGA::SetupDFT(uint32_t f_firstBin, uint32_t f_binSpacing) {
+	// see FPGA protocol for formulas
+	uint16_t firstBin = f_firstBin * (1ULL << 16) / ADC_samplerate;
+	uint16_t binSpacing = f_binSpacing * (1ULL << 24) / ADC_samplerate;
+	WriteRegister(Reg::DFTFirstBin, firstBin);
+	WriteRegister(Reg::DFTFreqSpacing, binSpacing);
+}
+
+void FPGA::StopDFT() {
+	DisableInterrupt(Interrupt::DFTReady);
+}
+
+void FPGA::StartDFT() {
+	StopDFT();
+	EnableInterrupt(Interrupt::DFTReady);
+}
+
 FPGA::DFTResult FPGA::ReadDFTResult() {
 	uint8_t cmd[2] = {0xA0, 0x00};
 	uint8_t recv[24];

Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp

@@ -7,6 +7,7 @@ namespace FPGA {
 
 static constexpr uint16_t MaxPoints = 4501;
 static constexpr uint16_t DFTbins = 64;
+static constexpr uint32_t Clockrate = 102400000UL;
 
 enum class Reg {
 	InterruptMask = 0x00,
@@ -23,8 +24,6 @@ enum class Reg {
 	MAX2871Def3MSB = 0x0D,
 	MAX2871Def4LSB = 0x0E,
 	MAX2871Def4MSB = 0x0F,
-	DFTSamples = 0x10,
-	DFTWindowInc = 0x11,
 	DFTFirstBin = 0x12,
 	DFTFreqSpacing = 0x13,
 };
@@ -124,6 +123,9 @@ void WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceRegs, uin
 		uint8_t attenuation, uint64_t frequency, SettlingTime settling, Samples samples, bool halt = false, LowpassFilter filter = LowpassFilter::Auto);
 using ReadCallback = void(*)(const SamplingResult &result);
 bool InitiateSampleRead(ReadCallback cb);
+void SetupDFT(uint32_t f_firstBin, uint32_t f_binSpacing);
+void StopDFT();
+void StartDFT();
 DFTResult ReadDFTResult();
 ADCLimits GetADCLimits();
 void ResetADCLimits();

Software/VNA_embedded/Application/Drivers/Si5351C.cpp

@@ -315,29 +315,31 @@ void Si5351C::FindOptimalDivider(uint32_t f_pll, uint32_t f, uint32_t &P1,
 	// see https://www.silabs.com/documents/public/application-notes/AN619.pdf (page 3/6)
 	uint32_t a = f_pll / f;
 	int32_t f_rem = f_pll - f * a;
-	uint32_t best_b, best_c;
+	// always using the highest modulus divider results in less than 1Hz deviation for all frequencies, that is good enough
-	uint32_t best_deviation = UINT32_MAX;
+	uint32_t best_c = (1UL << 20) - 1;
-	for (uint32_t c = (1UL << 20) - 1; c >= (1UL << 19); c--) {
+	uint32_t best_b = (uint64_t) f_rem * best_c / f;
-		uint32_t guess_b = (uint64_t) f_rem * c / f;
+//	uint32_t best_deviation = UINT32_MAX;
-		for (uint32_t b = guess_b; b <= guess_b + 1; b++) {
+//	for (uint32_t c = (1UL << 20) - 1; c >= (1UL << 19); c--) {
-			int32_t f_div = (uint64_t) f * b / c;
+//		uint32_t guess_b = (uint64_t) f_rem * c / f;
-			uint32_t deviation = abs(f_rem - f_div);
+//		for (uint32_t b = guess_b; b <= guess_b + 1; b++) {
-			if (deviation < best_deviation) {
+//			int32_t f_div = (uint64_t) f * b / c;
-				best_b = b;
+//			uint32_t deviation = abs(f_rem - f_div);
-				best_c = c;
+//			if (deviation < best_deviation) {
-				best_deviation = deviation;
+//				best_b = b;
-				if (deviation == 0) {
+//				best_c = c;
-					break;
+//				best_deviation = deviation;
-				}
+//				if (deviation <= 3) {
-			}
+//					break;
-		}
+//				}
-		if (best_deviation == 0) {
+//			}
-			break;
+//		}
-		}
+//		if (best_deviation <= 3) {
-	}
+//			break;
-	LOG_DEBUG(
+//		}
-			"Optimal divider for %luHz/%luHz is: a=%lu, b=%lu, c=%lu (%luHz deviation)",
+//	}
-			f_pll, f, a, best_b, best_c, best_deviation);
+//	LOG_DEBUG(
+//			"Optimal divider for %luHz/%luHz is: a=%lu, b=%lu, c=%lu (%luHz deviation)",
+//			f_pll, f, a, best_b, best_c, best_deviation);
 	// convert to Si5351C parameters
 	uint32_t floor = 128 * best_b / best_c;
 	P1 = 128 * a + floor - 512;

Software/VNA_embedded/Application/Hardware.cpp

@@ -131,10 +131,6 @@ bool HW::Init() {
 	// Set phase increment according to
 	FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, HW::DFTphaseInc);
 
-	// Enable new data and sweep halt interrupt
-	FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
-	FPGA::EnableInterrupt(FPGA::Interrupt::SweepHalted);
-
 	Exti::SetCallback(FPGA_INTR_GPIO_Port, FPGA_INTR_Pin, Exti::EdgeType::Rising, Exti::Pull::Down, FPGA_Interrupt);
 
 	// Initialize PLLs and build VCO maps

Software/VNA_embedded/Application/Hardware.hpp

@@ -2,6 +2,7 @@
 
 #include <cstdint>
 #include "Protocol.hpp"
+#include "FPGA/FPGA.hpp"
 
 #define USE_DEBUG_PINS
 
@@ -31,10 +32,9 @@ static constexpr uint32_t LO1_minFreq = 25000000;
 static constexpr uint32_t MaxSamples = 130944;
 static constexpr uint32_t MinSamples = 16;
 static constexpr uint32_t PLLRef = 100000000;
-static constexpr uint16_t MaxPoints = 4501;
 
-static constexpr uint8_t ADCprescaler = 102400000UL / ADCSamplerate;
+static constexpr uint8_t ADCprescaler = FPGA::Clockrate / ADCSamplerate;
-static_assert(ADCprescaler * ADCSamplerate == 102400000UL, "ADCSamplerate can not be reached exactly");
+static_assert(ADCprescaler * ADCSamplerate == FPGA::Clockrate, "ADCSamplerate can not be reached exactly");
 static constexpr uint16_t DFTphaseInc = 4096 * IF2 / ADCSamplerate;
 static_assert(DFTphaseInc * ADCSamplerate == 4096 * IF2, "DFT can not be computed for 2.IF");
 
@@ -43,7 +43,7 @@ static constexpr Protocol::DeviceLimits Limits = {
 		.maxFreq = 6000000000,
 		.minIFBW = ADCSamplerate / MaxSamples,
 		.maxIFBW = ADCSamplerate / MinSamples,
-		.maxPoints = MaxPoints,
+		.maxPoints = FPGA::MaxPoints,
 		.cdbm_min = -4000,
 		.cdbm_max = 0,
 		.minRBW = (uint32_t) (ADCSamplerate * 2.23f / MaxSamples),

Software/VNA_embedded/Application/Manual.cpp

@@ -73,6 +73,9 @@ void Manual::Setup(Protocol::ManualControl m) {
 	FPGA::Enable(FPGA::Periphery::ExcitePort2, m.PortSwitch == 1);
 	FPGA::Enable(FPGA::Periphery::PortSwitch);
 
+	// Enable new data and sweep halt interrupt
+	FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
+
 	active = true;
 	FPGA::StartSweep();
 }

Software/VNA_embedded/Application/SpectrumAnalyzer.cpp

@@ -11,6 +11,8 @@
 #define LOG_MODULE	"SA"
 #include "Log.h"
 
+using namespace HWHAL;
+
 static Protocol::SpectrumAnalyzerSettings s;
 static uint32_t pointCnt;
 static uint32_t points;
@@ -21,10 +23,11 @@ static Protocol::PacketInfo p;
 static bool active = false;
 static uint32_t lastLO2;
 static uint32_t actualRBW;
+static bool usingDFT;
+static uint16_t DFTpoints;
+static bool negativeDFT; // if true, a positive frequency shift at input results in a negative shift at the 2.IF. Handle DFT accordingly
 
-static float port1Measurement, port2Measurement;
+static float port1Measurement[FPGA::DFTbins], port2Measurement[FPGA::DFTbins];
-
-using namespace HWHAL;
 
 static void StartNextSample() {
 	uint64_t freq = s.f_start + (s.f_stop - s.f_start) * pointCnt / (points - 1);
@@ -34,16 +37,20 @@ static void StartNextSample() {
 	case 0:
 	default:
 		// reset minimum amplitudes in first signal ID step
-		port1Measurement = std::numeric_limits<float>::max();
+		for (uint16_t i = 0; i < DFTpoints; i++) {
-		port2Measurement = std::numeric_limits<float>::max();
+			port1Measurement[i] = std::numeric_limits<float>::max();
+			port2Measurement[i] = std::numeric_limits<float>::max();
+		}
 		// Use default LO frequencies
 		LO1freq = freq + HW::IF1;
 		LO2freq = HW::IF1 - HW::IF2;
 		FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, 112);
 		FPGA::WriteRegister(FPGA::Reg::PhaseIncrement, 1120);
+		negativeDFT = true;
 		break;
 	case 1:
 		LO2freq = HW::IF1 - HW::IF2;
+		negativeDFT = false;
 		// Shift first LO to other side
 		// depending on the measurement frequency this is not possible or additive mixing has to be used
 		if(freq >= HW::IF1 + HW::LO1_minFreq) {
@@ -59,13 +66,15 @@ static void StartNextSample() {
 		signalIDstep++;
 		/* no break */
 	case 2:
-		// Shift both LOs to other side
+		// Shift second LOs to other side
 		LO1freq = freq + HW::IF1;
 		LO2freq = HW::IF1 + HW::IF2;
+		negativeDFT = false;
 		break;
 	case 3:
+		// Shift both LO to other side
 		LO2freq = HW::IF1 + HW::IF2;
-		// Shift second LO to other side
+		negativeDFT = true;
 		// depending on the measurement frequency this is not possible or additive mixing has to be used
 		if(freq >= HW::IF1 + HW::LO1_minFreq) {
 			// frequency is high enough to shift 1.LO below measurement frequency
@@ -81,6 +90,7 @@ static void StartNextSample() {
 		/* no break */
 	case 4:
 		// Use default frequencies with different ADC samplerate to remove images in final IF
+		negativeDFT = true;
 		LO1freq = freq + HW::IF1;
 		LO2freq = HW::IF1 - HW::IF2;
 		FPGA::WriteRegister(FPGA::Reg::ADCPrescaler, 120);
@@ -96,6 +106,17 @@ static void StartNextSample() {
 		Si5351.SetCLK(SiChannel::Port2LO2, LO2freq, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
 		lastLO2 = LO2freq;
 	}
+	if (usingDFT) {
+		uint32_t spacing = (s.f_stop - s.f_start) / (points - 1);
+		uint32_t start = HW::IF2;
+		if(negativeDFT) {
+			// needs to look below the start frequency, shift start
+			start -= spacing * (DFTpoints - 1);
+		}
+		FPGA::SetupDFT(start, spacing);
+		FPGA::StartDFT();
+	}
+
 	// Configure the sampling in the FPGA
 	FPGA::WriteSweepConfig(0, 0, Source.GetRegisters(), LO1.GetRegisters(), 0,
 			0, FPGA::SettlingTime::us20, FPGA::Samples::SPPRegister, 0,
@@ -111,9 +132,6 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
 	s = settings;
 	HW::SetMode(HW::Mode::SA);
 	FPGA::SetMode(FPGA::Mode::FPGA);
-	FPGA::DisableInterrupt(FPGA::Interrupt::NewData);
-	FPGA::DisableInterrupt(FPGA::Interrupt::SweepHalted);
-	FPGA::EnableInterrupt(FPGA::Interrupt::DFTReady);
 	// in almost all cases a full sweep requires more points than the FPGA can handle at a time
 	// individually start each point and do the sweep in the uC
 	FPGA::SetNumberOfPoints(1);
@@ -148,12 +166,17 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
 	FPGA::Enable(FPGA::Periphery::Port1Mixer);
 	FPGA::Enable(FPGA::Periphery::Port2Mixer);
 
-	// Configure DFT
+	// automatically select DFT mode for lower RBWs
-	LOG_INFO("DFT samples: %lu", sampleNum);
+	usingDFT = actualRBW <= 1000;
-	FPGA::WriteRegister(FPGA::Reg::DFTSamples, sampleNum - 1);
+
-	FPGA::WriteRegister(FPGA::Reg::DFTWindowInc, 65536 / sampleNum);
+	if (usingDFT) {
-	FPGA::WriteRegister(FPGA::Reg::DFTFirstBin, 17920);
+		DFTpoints = FPGA::DFTbins; // use full DFT in FPGA
-	FPGA::WriteRegister(FPGA::Reg::DFTFreqSpacing, 1147);
+		FPGA::DisableInterrupt(FPGA::Interrupt::NewData);
+	} else {
+		DFTpoints = 1; // can only measure one point at a time
+		FPGA::StopDFT();
+		FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
+	}
 
 	lastLO2 = 0;
 	active = true;
@@ -166,26 +189,39 @@ bool SA::MeasurementDone(const FPGA::SamplingResult &result) {
 	}
 	FPGA::AbortSweep();
 
-	uint16_t i=0;
+	for(uint16_t i=0;i<DFTpoints;i++) {
-	while(FPGA::GetStatus() & (uint16_t) FPGA::Interrupt::DFTReady) {
+		float port1, port2;
+		if (usingDFT) {
+			// use DFT result
 			auto dft = FPGA::ReadDFTResult();
-		dft.P1 /= sampleNum;
+			port1 = dft.P1;
-		dft.P2 /= sampleNum;
+			port2 = dft.P2;
-		LOG_INFO("DFT %d: %lu, %lu", i, (uint32_t) dft.P1, (uint32_t) dft.P2);
+		} else {
-		Log_Flush();
+			port1 = abs(std::complex<float>(result.P1I, result.P1Q));
-		i++;
+			port2 = abs(std::complex<float>(result.P2I, result.P2Q));
 		}
-	FPGA::DisableInterrupt(FPGA::Interrupt::DFTReady);
+		port1 /= sampleNum;
-	FPGA::EnableInterrupt(FPGA::Interrupt::DFTReady);
+		port2 /= sampleNum;
 
-	float port1 = abs(std::complex<float>(result.P1I, result.P1Q))/sampleNum;
+		uint16_t index = i;
-	float port2 = abs(std::complex<float>(result.P2I, result.P2Q))/sampleNum;
+		if (negativeDFT) {
-	if(port1 < port1Measurement) {
+			// bin order is reversed
-		port1Measurement = port1;
+			index = DFTpoints - i - 1;
 		}
-	if(port2 < port2Measurement) {
+
-		port2Measurement = port2;
+		if(port1 < port1Measurement[index]) {
+			port1Measurement[index] = port1;
 		}
+		if(port2 < port2Measurement[index]) {
+			port2Measurement[index] = port2;
+		}
+	}
+
+	if (usingDFT) {
+		FPGA::StopDFT();
+		// will be started again in StartNextSample
+	}
+
 	// trigger work function
 	return true;
 }
@@ -196,8 +232,9 @@ void SA::Work() {
 	}
 	if(!s.SignalID || signalIDstep >= 4) {
 		// this measurement point is done, handle result according to detector
-		uint16_t binIndex = pointCnt / binSize;
+		for(uint16_t i=0;i<DFTpoints;i++) {
-		uint32_t pointInBin = pointCnt % binSize;
+			uint16_t binIndex = (pointCnt + i) / binSize;
+			uint32_t pointInBin = (pointCnt + i) % binSize;
 			bool lastPointInBin = pointInBin >= binSize - 1;
 			auto det = (Detector) s.Detector;
 			if(det == Detector::Normal) {
@@ -209,11 +246,11 @@ void SA::Work() {
 					p.spectrumResult.port1 = std::numeric_limits<float>::min();
 					p.spectrumResult.port2 = std::numeric_limits<float>::min();
 				}
-			if(port1Measurement > p.spectrumResult.port1) {
+				if(port1Measurement[i] > p.spectrumResult.port1) {
-				p.spectrumResult.port1 = port1Measurement;
+					p.spectrumResult.port1 = port1Measurement[i];
 				}
-			if(port2Measurement > p.spectrumResult.port2) {
+				if(port2Measurement[i] > p.spectrumResult.port2) {
-				p.spectrumResult.port2 = port2Measurement;
+					p.spectrumResult.port2 = port2Measurement[i];
 				}
 				break;
 			case Detector::NegPeak:
@@ -221,18 +258,18 @@ void SA::Work() {
 					p.spectrumResult.port1 = std::numeric_limits<float>::max();
 					p.spectrumResult.port2 = std::numeric_limits<float>::max();
 				}
-			if(port1Measurement < p.spectrumResult.port1) {
+				if(port1Measurement[i] < p.spectrumResult.port1) {
-				p.spectrumResult.port1 = port1Measurement;
+					p.spectrumResult.port1 = port1Measurement[i];
 				}
-			if(port2Measurement < p.spectrumResult.port2) {
+				if(port2Measurement[i] < p.spectrumResult.port2) {
-				p.spectrumResult.port2 = port2Measurement;
+					p.spectrumResult.port2 = port2Measurement[i];
 				}
 				break;
 			case Detector::Sample:
 				if(pointInBin <= binSize / 2) {
 					// still in first half of bin, simply overwrite
-				p.spectrumResult.port1 = port1Measurement;
+					p.spectrumResult.port1 = port1Measurement[i];
-				p.spectrumResult.port2 = port2Measurement;
+					p.spectrumResult.port2 = port2Measurement[i];
 				}
 				break;
 			case Detector::Average:
@@ -240,8 +277,8 @@ void SA::Work() {
 					p.spectrumResult.port1 = 0;
 					p.spectrumResult.port2 = 0;
 				}
-			p.spectrumResult.port1 += port1Measurement;
+				p.spectrumResult.port1 += port1Measurement[i];
-			p.spectrumResult.port2 += port2Measurement;
+				p.spectrumResult.port2 += port2Measurement[i];
 				if(lastPointInBin) {
 					// calculate average
 					p.spectrumResult.port1 /= binSize;
@@ -260,10 +297,11 @@ void SA::Work() {
 				p.spectrumResult.frequency = s.f_start + (s.f_stop - s.f_start) * binIndex / (s.pointNum - 1);
 				Communication::Send(p);
 			}
+		}
 		// setup for next step
 		signalIDstep = 0;
-		if(pointCnt < points - 1) {
+		if(pointCnt < points - DFTpoints) {
-			pointCnt++;
+			pointCnt += DFTpoints;
 		} else {
 			pointCnt = 0;
 		}

Software/VNA_embedded/Application/VNA.cpp

@@ -187,6 +187,9 @@ bool VNA::Setup(Protocol::SweepSettings s, SweepCallback cb) {
 	IFTableIndexCnt = 0;
 	adcShifted = false;
 	active = true;
+	// Enable new data and sweep halt interrupt
+	FPGA::EnableInterrupt(FPGA::Interrupt::NewData);
+	FPGA::EnableInterrupt(FPGA::Interrupt::SweepHalted);
 	// Start the sweep
 	FPGA::StartSweep();
 	return true;