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Windowing option added to sampling

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This commit is contained in:
Jan Käberich 2020-09-16 16:13:06 +02:00
parent de8761545d
commit d9d00b8c71
23 changed files with 1267 additions and 493 deletions
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57
FPGA/VNA/Sampling.vhd
View File

@ -45,6 +45,7 @@ entity Sampling is
PRE_DONE : out STD_LOGIC;
START : in STD_LOGIC;
SAMPLES : in STD_LOGIC_VECTOR (9 downto 0);
WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
PORT1_I : out STD_LOGIC_VECTOR (47 downto 0);
PORT1_Q : out STD_LOGIC_VECTOR (47 downto 0);
PORT2_I : out STD_LOGIC_VECTOR (47 downto 0);
@ -71,6 +72,14 @@ COMPONENT SinCosMult
p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
COMPONENT window
PORT(
CLK : IN std_logic;
INDEX : IN std_logic_vector(6 downto 0);
WINDOW_TYPE : IN std_logic_vector(1 downto 0);
VALUE : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
signal p1_I : signed(47 downto 0);
signal p1_Q : signed(47 downto 0);
@ -87,6 +96,13 @@ END COMPONENT;
signal sine : std_logic_vector(15 downto 0);
signal cosine : std_logic_vector(15 downto 0);
signal windowed_sine : std_logic_vector(31 downto 0);
signal windowed_cosine : std_logic_vector(31 downto 0);
signal window_index : std_logic_vector(6 downto 0);
signal window_value : std_logic_vector(15 downto 0);
signal window_sample_cnt : integer range 0 to 1023;
signal mult1_I : std_logic_vector(31 downto 0);
signal mult1_Q : std_logic_vector(31 downto 0);
signal mult2_I : std_logic_vector(31 downto 0);
@ -113,44 +129,65 @@ begin
PORT MAP (
clk => CLK,
a => PORT1,
b => cosine,
b => windowed_cosine(31 downto 16),
p => mult1_I
);
Port1_Q_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => PORT1,
b => sine,
b => windowed_sine(31 downto 16),
p => mult1_Q
);
Port2_I_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => PORT2,
b => cosine,
b => windowed_cosine(31 downto 16),
p => mult2_I
);
Port2_Q_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => PORT2,
b => sine,
b => windowed_sine(31 downto 16),
p => mult2_Q
);
Ref_I_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => REF,
b => cosine,
b => windowed_cosine(31 downto 16),
p => multR_I
);
Ref_Q_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => REF,
b => sine,
b => windowed_sine(31 downto 16),
p => multR_Q
);
Sine_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => window_value,
b => sine,
p => windowed_sine
);
Cosine_Mult : SinCosMult
PORT MAP (
clk => CLK,
a => window_value,
b => cosine,
p => windowed_cosine
);
WindowROM: window PORT MAP(
CLK => CLK,
INDEX => window_index,
WINDOW_TYPE => WINDOW_TYPE,
VALUE => window_value
);
process(CLK, RESET)
begin
@ -163,6 +200,7 @@ begin
ACTIVE <= '0';
clk_cnt <= 0;
sample_cnt <= 0;
window_sample_cnt <= 0;
phase <= (others => '0');
else
-- when not idle, generate pulses for ADCs
@ -228,6 +266,13 @@ begin
else
state <= Ready;
end if;
-- keep track of window index
if window_sample_cnt < unsigned(SAMPLES) - 1 then
window_sample_cnt <= window_sample_cnt + 1;
else
window_sample_cnt <= 0;
window_index <= std_logic_vector( unsigned(window_index) + 1 );
end if;
when Ready =>
ACTIVE <= '1';
DONE <= '1';

106
FPGA/VNA/Test_Window.vhd Normal file
View File

@ -0,0 +1,106 @@
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:39:25 09/16/2020
-- Design Name:
-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_Window.vhd
-- Project Name: VNA
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: window
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY Test_Window IS
END Test_Window;
ARCHITECTURE behavior OF Test_Window IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT window
PORT(
CLK : IN std_logic;
INDEX : IN std_logic_vector(6 downto 0);
WINDOW : IN std_logic_vector(1 downto 0);
VALUE : OUT std_logic_vector(15 downto 0)
);
END COMPONENT;
--Inputs
signal CLK : std_logic := '0';
signal INDEX : std_logic_vector(6 downto 0) := (others => '0');
signal WINDOW2 : std_logic_vector(1 downto 0) := (others => '0');
--Outputs
signal VALUE : std_logic_vector(15 downto 0);
-- Clock period definitions
constant CLK_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: window PORT MAP (
CLK => CLK,
INDEX => INDEX,
WINDOW => WINDOW2,
VALUE => VALUE
);
-- Clock process definitions
CLK_process :process
begin
CLK <= '0';
wait for CLK_period/2;
CLK <= '1';
wait for CLK_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
WINDOW2 <= "00";
INDEX <= "0000000";
wait for CLK_period*10;
WINDOW2 <= "10";
-- insert stimulus here
wait for CLK_period*10;
INDEX <= "0000001";
wait for CLK_period*10;
INDEX <= "0000010";
wait for CLK_period*10;
INDEX <= "0000011";
wait for CLK_period*10;
INDEX <= "0000100";
wait;
end process;
END;

113
FPGA/VNA/VNA.gise
View File

@ -47,6 +47,9 @@
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Window_beh.prj"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Window_isim_beh.exe"/>
<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Window_isim_beh.wdb"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_top_isim_beh.exe"/>
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
@ -63,6 +66,7 @@
<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
@ -111,6 +115,7 @@
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="window.vhi"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
@ -121,31 +126,44 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1590511156" xil_pn:in_ck="766507318003862528" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1590511156">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1590511022" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-1206566934435318832" xil_pn:start_ts="1590511022">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1590511022" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-273551377395144626" xil_pn:start_ts="1590511022">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1589440643" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1589440643">
<transform xil_pn:end_ts="1600256580" xil_pn:in_ck="6180625018917402544" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1600256580">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="MAX2871.vhd"/>
<outfile xil_pn:name="MCP33131.vhd"/>
<outfile xil_pn:name="ResetDelay.vhd"/>
<outfile xil_pn:name="SPIConfig.vhd"/>
<outfile xil_pn:name="Sampling.vhd"/>
<outfile xil_pn:name="Sweep.vhd"/>
<outfile xil_pn:name="Synchronizer.vhd"/>
<outfile xil_pn:name="Test_MAX2871.vhd"/>
<outfile xil_pn:name="Test_MCP33131.vhd"/>
<outfile xil_pn:name="Test_PLL.vhd"/>
<outfile xil_pn:name="Test_SPI.vhd"/>
<outfile xil_pn:name="Test_SPICommands.vhd"/>
<outfile xil_pn:name="Test_Sampling.vhd"/>
<outfile xil_pn:name="Test_SinCos.vhd"/>
<outfile xil_pn:name="Test_Sync.vhd"/>
<outfile xil_pn:name="Test_Window.vhd"/>
<outfile xil_pn:name="spi_slave.vhd"/>
<outfile xil_pn:name="top.vhd"/>
<outfile xil_pn:name="window.vhd"/>
</transform>
<transform xil_pn:end_ts="1600256454" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="7911631781232912461" xil_pn:start_ts="1600256454">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600256454" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-8348183349870037301" xil_pn:start_ts="1600256454">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600256363" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1600256363">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
@ -154,18 +172,39 @@
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
</transform>
<transform xil_pn:end_ts="1590511156" xil_pn:in_ck="766507318003862528" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1590511156">
<transform xil_pn:end_ts="1600256580" xil_pn:in_ck="3204048457877733613" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1600256580">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="MAX2871.vhd"/>
<outfile xil_pn:name="MCP33131.vhd"/>
<outfile xil_pn:name="ResetDelay.vhd"/>
<outfile xil_pn:name="SPIConfig.vhd"/>
<outfile xil_pn:name="Sampling.vhd"/>
<outfile xil_pn:name="Sweep.vhd"/>
<outfile xil_pn:name="Synchronizer.vhd"/>
<outfile xil_pn:name="Test_MAX2871.vhd"/>
<outfile xil_pn:name="Test_MCP33131.vhd"/>
<outfile xil_pn:name="Test_PLL.vhd"/>
<outfile xil_pn:name="Test_SPI.vhd"/>
<outfile xil_pn:name="Test_SPICommands.vhd"/>
<outfile xil_pn:name="Test_Sampling.vhd"/>
<outfile xil_pn:name="Test_SinCos.vhd"/>
<outfile xil_pn:name="Test_Sync.vhd"/>
<outfile xil_pn:name="Test_Window.vhd"/>
<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
<outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
<outfile xil_pn:name="spi_slave.vhd"/>
<outfile xil_pn:name="top.vhd"/>
<outfile xil_pn:name="window.vhd"/>
</transform>
<transform xil_pn:end_ts="1590511158" xil_pn:in_ck="4178816336447958013" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-3530939538078141760" xil_pn:start_ts="1590511156">
<transform xil_pn:end_ts="1600256582" xil_pn:in_ck="3204048457877733613" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-7714428255597766630" xil_pn:start_ts="1600256580">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
@ -173,20 +212,24 @@
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="Test_Window_beh.prj"/>
<outfile xil_pn:name="Test_Window_isim_beh.exe"/>
<outfile xil_pn:name="fuse.log"/>
<outfile xil_pn:name="isim"/>
<outfile xil_pn:name="isim.log"/>
<outfile xil_pn:name="xilinxsim.ini"/>
</transform>
<transform xil_pn:end_ts="1590511159" xil_pn:in_ck="6047462992229066111" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="6352116336892055917" xil_pn:start_ts="1590511158">
<transform xil_pn:end_ts="1600256582" xil_pn:in_ck="-6256802959996678011" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-2271436731750578457" xil_pn:start_ts="1600256582">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForProperties"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputRemoved"/>
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
<outfile xil_pn:name="Test_Window_isim_beh.wdb"/>
<outfile xil_pn:name="isim.cmd"/>
<outfile xil_pn:name="isim.log"/>
</transform>
<transform xil_pn:end_ts="1588686459" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1588686459">
<status xil_pn:value="SuccessfullyRun"/>
@ -223,7 +266,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600202513" xil_pn:in_ck="-94812602667091528" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600202496">
<transform xil_pn:end_ts="1600263408" xil_pn:in_ck="-1505308035655400832" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600263388">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -245,7 +288,7 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1600202519" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600202513">
<transform xil_pn:end_ts="1600263414" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600263408">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
@ -254,7 +297,7 @@
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1600202564" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600202519">
<transform xil_pn:end_ts="1600263452" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600263414">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -268,7 +311,7 @@
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1600202589" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600202564">
<transform xil_pn:end_ts="1600263480" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600263452">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@ -282,7 +325,7 @@
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1600202602" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1600202589">
<transform xil_pn:end_ts="1600263493" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1600263480">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
@ -328,7 +371,7 @@
<status xil_pn:value="OutputChanged"/>
<status xil_pn:value="OutputRemoved"/>
</transform>
<transform xil_pn:end_ts="1600202589" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600202583">
<transform xil_pn:end_ts="1600263480" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600263473">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

48
FPGA/VNA/VNA.xise
View File

@ -17,40 +17,40 @@
<files>
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="ipcore_dir/SweepConfigMem.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="ipcore_dir/SinCosMult.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="Test_Sampling.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -60,19 +60,19 @@
</file>
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -100,7 +100,7 @@
</file>
<file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@ -114,7 +114,17 @@
</file>
<file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="window.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="139"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="139"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="139"/>
</file>
<file xil_pn:name="ipcore_dir/SweepConfigMem.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
@ -372,8 +382,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_top" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_Window/uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.window" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@ -391,7 +401,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_top" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.window" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@ -443,7 +453,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MCP33131|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_Window|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

7
FPGA/VNA/top.vhd
View File

@ -157,7 +157,8 @@ architecture Behavioral of top is
REF : IN std_logic_vector(15 downto 0);
NEW_SAMPLE : IN std_logic;
START : IN std_logic;
SAMPLES : IN std_logic_vector(9 downto 0);
SAMPLES : IN std_logic_vector(9 downto 0);
WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
ADC_START : OUT std_logic;
DONE : OUT std_logic;
PRE_DONE : OUT std_logic;
@ -305,6 +306,7 @@ architecture Behavioral of top is
signal sampling_samples : std_logic_vector(9 downto 0);
signal sampling_user_samples : std_logic_vector(9 downto 0);
signal sampling_result : std_logic_vector(287 downto 0);
signal sampling_window : std_logic_vector(1 downto 0);
-- Sweep signals
signal sweep_points : std_logic_vector(12 downto 0);
@ -542,6 +544,7 @@ begin
PRE_DONE => open,
START => sampling_start,
SAMPLES => sampling_samples,
WINDOW_TYPE => sampling_window,
PORT1_I => sampling_result(287 downto 240),
PORT1_Q => sampling_result(239 downto 192),
PORT2_I => sampling_result(191 downto 144),
@ -646,7 +649,7 @@ begin
SOURCE_CE_EN => SOURCE_CE,
LO_CE_EN => LO1_CE,
LEDS => user_leds,
WINDOW_SETTING => open,
WINDOW_SETTING => sampling_window,
INTERRUPT_ASSERTED => intr,
RESET_MINMAX => adc_reset_minmax,
SWEEP_HALTED => sweep_halted,

77
FPGA/VNA/window.vhd Normal file
View File

@ -0,0 +1,77 @@
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:28:54 09/16/2020
-- Design Name:
-- Module Name: window - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use std.textio.all;
use ieee.std_logic_textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity window is
Port ( CLK : in STD_LOGIC;
INDEX : in STD_LOGIC_VECTOR (6 downto 0);
WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
VALUE : out STD_LOGIC_VECTOR (15 downto 0));
end window;
architecture Behavioral of window is
type window_data is array(127 downto 0) of std_logic_vector(15 downto 0);
impure function InitWindowDataFromFile (RomFileName : in string) return window_data is
FILE romfile : text is in RomFileName;
variable RomFileLine : line;
variable rom : window_data;
begin
for i in window_data'range loop
readline(romfile, RomFileLine);
read(RomFileLine, rom(i));
end loop;
return rom;
end function;
constant hann : window_data := InitWindowDataFromFile("Hann.dat");
constant kaiser : window_data := InitWindowDataFromFile("Kaiser.dat");
constant flattop : window_data := InitWindowDataFromFile("Flattop.dat");
signal i : integer range 0 to 127;
begin
i <= to_integer(unsigned(INDEX));
process(CLK)
begin
if rising_edge(CLK) then
case WINDOW_TYPE is
when "00" => VALUE <= "0001000000000000";
when "01" => VALUE <= kaiser(i);
when "10" => VALUE <= hann(i);
when "11" => VALUE <= flattop(i);
when others => VALUE <= (others => '0');
end case;
end if;
end process;
end Behavioral;

25
FPGA/WindowCoefficientGenerator.py
View File

@ -1,6 +1,7 @@
#!/usr/bin/env python3
import math
import numpy as np
# Adapt these constants to your window requirements
NUMBER_OF_COEFFICIENTS = 128
@ -12,6 +13,10 @@ INCLUDE_AMPLITUDE_CORRECTION = True
# Don't change anything below this line
def bindigits(n, bits):
s = bin(n & int("1"*bits, 2))[2:]
return ("{0:0>%s}" % (bits)).format(s)
class Window:
def __init__(self, name, function, correction):
self.name = name
@ -19,7 +24,7 @@ class Window:
self.correction = correction
def StartFile(self):
self.file = open(self.name+".txt", "w")
self.file = open(self.name+".dat", "w")
def AddCoefficient(self, normalized_index):
if not hasattr(self, 'file'):
@ -31,14 +36,28 @@ class Window:
# prevent overflow
if value >= (2 ** (BITS_PER_COEFFICIENT-1)):
value = value - 1
output = "{0:b}".format(value)
self.file.write(output.zfill(BITS_PER_COEFFICIENT)+"\n")
output = bindigits(value, BITS_PER_COEFFICIENT)
self.file.write(output+"\n")
def calc_hann(i):
return math.sin(math.pi * i) ** 2
def calc_kaiser(i):
return np.kaiser(NUMBER_OF_COEFFICIENTS, 9.4)[int(i * NUMBER_OF_COEFFICIENTS)]
def calc_flattop(i):
a0 = 0.21557895
a1 = 0.41663158
a2 = 0.277263158
a3 = 0.083578947
a4 = 0.006947368
return a0 - a1 * math.cos(2*math.pi*i) + a2 * math.cos(4*math.pi*i) - a3 * math.cos(6*math.pi*i) + a4 * math.cos(8*math.pi*i)
WindowList = []
WindowList.append(Window("Hann", calc_hann, 2.0))
WindowList.append(Window("Kaiser", calc_kaiser, 2.49))
WindowList.append(Window("Flattop", calc_flattop, 4.18))
for i in range(NUMBER_OF_COEFFICIENTS):
norm_i = (i+0.5) / NUMBER_OF_COEFFICIENTS

BIN
Software/PC_Application/Application
View File

Binary file not shown.

2
Software/PC_Application/Device/manualcontroldialog.cpp
View File

@ -174,6 +174,7 @@ ManualControlDialog::ManualControlDialog(Device &dev, QWidget *parent) :
connect(ui->Attenuator, qOverload<double>(&QDoubleSpinBox::valueChanged), [=](double) { UpdateDevice(); });
connect(ui->Samples, qOverload<int>(&QSpinBox::valueChanged), [=](double) { UpdateDevice(); });
connect(ui->cbWindow, qOverload<int>(&QComboBox::activated), [=](int) { UpdateDevice(); });
UpdateDevice();
}
@ -247,6 +248,7 @@ void ManualControlDialog::UpdateDevice()
m.Port2EN = ui->Port2Enable->isChecked();
m.RefEN = ui->RefEnable->isChecked();
m.Samples = ui->Samples->value();
m.WindowType = ui->cbWindow->currentIndex();
qDebug() << "Updating manual control state";

31
Software/PC_Application/Device/manualcontroldialog.ui
View File

@ -533,6 +533,37 @@
</property>
</widget>
</item>
<item row="1" column="0">
<widget class="QLabel" name="label_15">
<property name="text">
<string>Window:</string>
</property>
</widget>
</item>
<item row="1" column="1">
<widget class="QComboBox" name="cbWindow">
<item>
<property name="text">
<string>None</string>
</property>
</item>
<item>
<property name="text">
<string>Kaiser</string>
</property>
</item>
<item>
<property name="text">
<string>Hann</string>
</property>
</item>
<item>
<property name="text">
<string>Flat Top</string>
</property>
</item>
</widget>
</item>
</layout>
</item>
</layout>

4
Software/PC_Application/appwindow.cpp
View File

@ -284,7 +284,9 @@ void AppWindow::StartManualControl()
{
auto control = new ManualControlDialog(*device, this);
connect(control, &QDialog::finished, [=](){
Mode::getActiveMode()->initializeDevice();
if(device) {
Mode::getActiveMode()->initializeDevice();
}
});
control->show();
}

2
Software/PC_Application/preferences.h
View File

@ -63,7 +63,7 @@ private:
{&Startup.DefaultSweep.points, "Startup.DefaultSweep.points", 501},
{&Startup.DefaultSweep.bandwidth, "Startup.DefaultSweep.bandwidth", 1000.0},
{&Startup.DefaultSweep.excitation, "Startup.DefaultSweep.excitation", -10.00},
{&Acquisition.alwaysExciteBothPorts, "Acquisition.alwaysExciteBothPorts", false},
{&Acquisition.alwaysExciteBothPorts, "Acquisition.alwaysExciteBothPorts", true},
}};
};

1228
Software/VNA_embedded/.cproject
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File diff suppressed because it is too large Load Diff

2
Software/VNA_embedded/.mxproject
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File diff suppressed because one or more lines are too long

2
Software/VNA_embedded/Application/Communication/Protocol.cpp
View File

@ -327,6 +327,7 @@ static Protocol::ManualControl DecodeManualControl(uint8_t *buf) {
d.Port2EN = e.getBits(1);
d.RefEN = e.getBits(1);
e.get<uint32_t>(d.Samples);
d.WindowType = e.getBits(2);
return d;
}
static int16_t EncodeManualControl(Protocol::ManualControl d, uint8_t *buf,
@ -353,6 +354,7 @@ static int16_t EncodeManualControl(Protocol::ManualControl d, uint8_t *buf,
e.addBits(d.Port2EN, 1);
e.addBits(d.RefEN, 1);
e.add<uint32_t>(d.Samples);
e.addBits(d.WindowType, 2);
return e.getSize();
}

1
Software/VNA_embedded/Application/Communication/Protocol.hpp
View File

@ -95,6 +95,7 @@ using ManualControl = struct _manualControl {
uint8_t Port2EN :1;
uint8_t RefEN :1;
uint32_t Samples;
uint8_t WindowType :2;
};

6
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
View File

@ -137,6 +137,12 @@ void FPGA::Disable(Periphery p) {
WriteRegister(Reg::SystemControl, SysCtrlReg);
}
void FPGA::SetWindow(Window w) {
SysCtrlReg &= ~0x0060;
SysCtrlReg |= (int) w << 5;
WriteRegister(Reg::SystemControl, SysCtrlReg);
}
void FPGA::EnableInterrupt(Interrupt i) {
ISRMaskReg |= (uint16_t) i;
WriteRegister(Reg::InterruptMask, ISRMaskReg);

8
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
View File

@ -85,6 +85,13 @@ enum class Samples {
S91392 = 0x07,
};
enum class Window {
None = 0x00,
Kaiser = 0x01,
Hann = 0x02,
Flattop = 0x03,
};
bool Configure(Flash *f, uint32_t start_address, uint32_t bitstream_size);
using HaltedCallback = void(*)(void);
@ -93,6 +100,7 @@ void SetNumberOfPoints(uint16_t npoints);
void SetSamplesPerPoint(uint32_t nsamples);
void Enable(Periphery p, bool enable = true);
void Disable(Periphery p);
void SetWindow(Window w);
void EnableInterrupt(Interrupt i);
void DisableInterrupt(Interrupt i);
void WriteMAX2871Default(uint32_t *DefaultRegs);

5
Software/VNA_embedded/Application/Drivers/max2871.cpp
View File

@ -187,6 +187,11 @@ bool MAX2871::SetFrequency(uint64_t f) {
auto approx = Algorithm::BestRationalApproximation(fraction, 4095);
if(approx.denom == 1) {
// M value must be at least 2
approx.denom = 2;
}
int32_t rem_approx = ((uint64_t) f_PFD * approx.num) / approx.denom;
if(rem_approx != rem_f) {
LOG_WARN("Best match is F=%u/M=%u, deviation of %luHz",

4
Software/VNA_embedded/Application/VNA.cpp
View File

@ -340,6 +340,7 @@ bool VNA::ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb) {
// Si5351.SetCLK(1, IF1 + IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
// Si5351.ResetPLL(Si5351C::PLL::B);
// Enable mixers/amplifier/PLLs
FPGA::SetWindow(FPGA::Window::None);
FPGA::Enable(FPGA::Periphery::Port1Mixer);
FPGA::Enable(FPGA::Periphery::Port2Mixer);
FPGA::Enable(FPGA::Periphery::RefMixer);
@ -407,6 +408,8 @@ bool VNA::ConfigureManual(Protocol::ManualControl m, StatusCallback cb) {
FPGA::Samples::SPPRegister, 0,
(FPGA::LowpassFilter) m.SourceHighLowpass);
FPGA::SetWindow((FPGA::Window) m.WindowType);
// Enable/Disable periphery
FPGA::Enable(FPGA::Periphery::SourceChip, m.SourceHighCE);
FPGA::Enable(FPGA::Periphery::SourceRF, m.SourceHighRFEN);
@ -530,6 +533,7 @@ bool VNA::ConfigureGenerator(Protocol::GeneratorSettings g) {
m.Port2EN = 0;
m.RefEN = 0;
m.Samples = 131072;
m.WindowType = (int) FPGA::Window::None;
// Select correct source
if(g.frequency < BandSwitchFrequency) {
m.SourceLowEN = 1;

10
Software/VNA_embedded/Src/main.c
View File

@ -519,7 +519,7 @@ static void MX_UCPD1_Init(void)
LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MDATAALIGN_BYTE);
/* UCPD1 interrupt Init */
NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),6, 0));
NVIC_EnableIRQ(UCPD1_IRQn);
/* USER CODE BEGIN UCPD1_Init 1 */
@ -623,16 +623,16 @@ static void MX_DMA_Init(void)
/* DMA interrupt init */
/* DMA1_Channel1_IRQn interrupt configuration */
NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),6, 0));
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
/* DMA1_Channel2_IRQn interrupt configuration */
NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),6, 0));
NVIC_EnableIRQ(DMA1_Channel2_IRQn);
/* DMA1_Channel3_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 5, 0);
HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 6, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
/* DMA1_Channel4_IRQn interrupt configuration */
HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 5, 0);
HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 6, 0);
HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
}

8
Software/VNA_embedded/Src/stm32g4xx_hal_msp.c
View File

@ -508,10 +508,10 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
/* Peripheral clock enable */
__HAL_RCC_USB_CLK_ENABLE();
/* USB interrupt Init */
HAL_NVIC_SetPriority(USB_HP_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USB_HP_IRQn);
HAL_NVIC_SetPriority(USB_LP_IRQn, 5, 0);
HAL_NVIC_EnableIRQ(USB_LP_IRQn);
HAL_NVIC_SetPriority(USB_HP_IRQn, 6, 0);
// HAL_NVIC_EnableIRQ(USB_HP_IRQn);
HAL_NVIC_SetPriority(USB_LP_IRQn, 6, 0);
// HAL_NVIC_EnableIRQ(USB_LP_IRQn);
/* USER CODE BEGIN USB_MspInit 1 */
/* USER CODE END USB_MspInit 1 */

14
Software/VNA_embedded/VNA_embedded.ioc
View File

@ -148,10 +148,10 @@ Mcu.UserName=STM32G431CBUx
MxCube.Version=5.2.1
MxDb.Version=DB.5.0.21
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.DMA1_Channel1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
NVIC.DMA1_Channel2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
NVIC.DMA1_Channel3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
NVIC.DMA1_Channel4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
NVIC.DMA1_Channel1_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
NVIC.DMA1_Channel2_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
NVIC.DMA1_Channel3_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
NVIC.DMA1_Channel4_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
@ -163,9 +163,9 @@ NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true
NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn
NVIC.TimeBaseIP=TIM17
NVIC.UCPD1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:false
NVIC.USB_HP_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
NVIC.USB_LP_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
NVIC.UCPD1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:false
NVIC.USB_HP_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
NVIC.USB_LP_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
PA1.GPIOParameters=GPIO_Label
PA1.GPIO_Label=FPGA_AUX1