Windowing option added to sampling
This commit is contained in:
Jan Käberich
parent
de8761545d
commit
d9d00b8c71
@ -45,6 +45,7 @@ entity Sampling is
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PRE_DONE : out STD_LOGIC;
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START : in STD_LOGIC;
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SAMPLES : in STD_LOGIC_VECTOR (9 downto 0);
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WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
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PORT1_I : out STD_LOGIC_VECTOR (47 downto 0);
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PORT1_Q : out STD_LOGIC_VECTOR (47 downto 0);
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PORT2_I : out STD_LOGIC_VECTOR (47 downto 0);
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@ -71,6 +72,14 @@ COMPONENT SinCosMult
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p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT window
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PORT(
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CLK : IN std_logic;
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INDEX : IN std_logic_vector(6 downto 0);
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WINDOW_TYPE : IN std_logic_vector(1 downto 0);
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VALUE : OUT std_logic_vector(15 downto 0)
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);
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END COMPONENT;
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signal p1_I : signed(47 downto 0);
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signal p1_Q : signed(47 downto 0);
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@ -87,6 +96,13 @@ END COMPONENT;
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signal sine : std_logic_vector(15 downto 0);
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signal cosine : std_logic_vector(15 downto 0);
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signal windowed_sine : std_logic_vector(31 downto 0);
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signal windowed_cosine : std_logic_vector(31 downto 0);
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signal window_index : std_logic_vector(6 downto 0);
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signal window_value : std_logic_vector(15 downto 0);
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signal window_sample_cnt : integer range 0 to 1023;
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signal mult1_I : std_logic_vector(31 downto 0);
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signal mult1_Q : std_logic_vector(31 downto 0);
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signal mult2_I : std_logic_vector(31 downto 0);
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@ -113,45 +129,66 @@ begin
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PORT MAP (
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clk => CLK,
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a => PORT1,
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b => cosine,
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b => windowed_cosine(31 downto 16),
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p => mult1_I
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);
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Port1_Q_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => PORT1,
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b => sine,
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b => windowed_sine(31 downto 16),
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p => mult1_Q
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);
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Port2_I_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => PORT2,
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b => cosine,
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b => windowed_cosine(31 downto 16),
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p => mult2_I
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);
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Port2_Q_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => PORT2,
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b => sine,
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b => windowed_sine(31 downto 16),
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p => mult2_Q
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);
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Ref_I_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => REF,
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b => cosine,
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b => windowed_cosine(31 downto 16),
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p => multR_I
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);
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Ref_Q_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => REF,
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b => sine,
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b => windowed_sine(31 downto 16),
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p => multR_Q
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);
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Sine_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => window_value,
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b => sine,
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p => windowed_sine
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);
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Cosine_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => window_value,
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b => cosine,
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p => windowed_cosine
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);
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WindowROM: window PORT MAP(
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CLK => CLK,
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INDEX => window_index,
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WINDOW_TYPE => WINDOW_TYPE,
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VALUE => window_value
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);
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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@ -163,6 +200,7 @@ begin
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ACTIVE <= '0';
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clk_cnt <= 0;
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sample_cnt <= 0;
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window_sample_cnt <= 0;
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phase <= (others => '0');
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else
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-- when not idle, generate pulses for ADCs
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@ -228,6 +266,13 @@ begin
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else
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state <= Ready;
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end if;
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-- keep track of window index
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if window_sample_cnt < unsigned(SAMPLES) - 1 then
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window_sample_cnt <= window_sample_cnt + 1;
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else
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window_sample_cnt <= 0;
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window_index <= std_logic_vector( unsigned(window_index) + 1 );
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end if;
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when Ready =>
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ACTIVE <= '1';
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DONE <= '1';
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106
FPGA/VNA/Test_Window.vhd
Normal file
106
FPGA/VNA/Test_Window.vhd
Normal file
@ -0,0 +1,106 @@
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13:39:25 09/16/2020
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-- Design Name:
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-- Module Name: /home/jan/Projekte/VNA2/FPGA/VNA/Test_Window.vhd
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-- Project Name: VNA
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: window
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY Test_Window IS
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END Test_Window;
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ARCHITECTURE behavior OF Test_Window IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT window
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PORT(
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CLK : IN std_logic;
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INDEX : IN std_logic_vector(6 downto 0);
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WINDOW : IN std_logic_vector(1 downto 0);
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VALUE : OUT std_logic_vector(15 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal CLK : std_logic := '0';
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signal INDEX : std_logic_vector(6 downto 0) := (others => '0');
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signal WINDOW2 : std_logic_vector(1 downto 0) := (others => '0');
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--Outputs
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signal VALUE : std_logic_vector(15 downto 0);
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-- Clock period definitions
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constant CLK_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: window PORT MAP (
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CLK => CLK,
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INDEX => INDEX,
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WINDOW => WINDOW2,
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VALUE => VALUE
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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wait for 100 ns;
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WINDOW2 <= "00";
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INDEX <= "0000000";
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wait for CLK_period*10;
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WINDOW2 <= "10";
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-- insert stimulus here
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wait for CLK_period*10;
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INDEX <= "0000001";
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wait for CLK_period*10;
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INDEX <= "0000010";
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wait for CLK_period*10;
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INDEX <= "0000011";
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wait for CLK_period*10;
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INDEX <= "0000100";
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wait;
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end process;
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END;
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@ -47,6 +47,9 @@
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Window_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Window_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Window_isim_beh.wdb"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_top_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
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@ -63,6 +66,7 @@
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<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
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@ -111,6 +115,7 @@
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
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<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="window.vhi"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
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@ -121,31 +126,44 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1590511156" xil_pn:in_ck="766507318003862528" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1590511156">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="InputRemoved"/>
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<status xil_pn:value="OutputChanged"/>
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<status xil_pn:value="OutputRemoved"/>
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</transform>
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<transform xil_pn:end_ts="1590511022" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-1206566934435318832" xil_pn:start_ts="1590511022">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1590511022" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-273551377395144626" xil_pn:start_ts="1590511022">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1589440643" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1589440643">
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<transform xil_pn:end_ts="1600256580" xil_pn:in_ck="6180625018917402544" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1600256580">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="MAX2871.vhd"/>
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<outfile xil_pn:name="MCP33131.vhd"/>
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<outfile xil_pn:name="ResetDelay.vhd"/>
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<outfile xil_pn:name="SPIConfig.vhd"/>
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<outfile xil_pn:name="Sampling.vhd"/>
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<outfile xil_pn:name="Sweep.vhd"/>
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<outfile xil_pn:name="Synchronizer.vhd"/>
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<outfile xil_pn:name="Test_MAX2871.vhd"/>
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<outfile xil_pn:name="Test_MCP33131.vhd"/>
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<outfile xil_pn:name="Test_PLL.vhd"/>
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<outfile xil_pn:name="Test_SPI.vhd"/>
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<outfile xil_pn:name="Test_SPICommands.vhd"/>
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<outfile xil_pn:name="Test_Sampling.vhd"/>
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<outfile xil_pn:name="Test_SinCos.vhd"/>
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<outfile xil_pn:name="Test_Sync.vhd"/>
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<outfile xil_pn:name="Test_Window.vhd"/>
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<outfile xil_pn:name="spi_slave.vhd"/>
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<outfile xil_pn:name="top.vhd"/>
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<outfile xil_pn:name="window.vhd"/>
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</transform>
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<transform xil_pn:end_ts="1600256454" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="7911631781232912461" xil_pn:start_ts="1600256454">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600256454" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-8348183349870037301" xil_pn:start_ts="1600256454">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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<transform xil_pn:end_ts="1600256363" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1600256363">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
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<outfile xil_pn:name="ipcore_dir/SinCos.ngc"/>
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<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
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@ -154,18 +172,39 @@
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<outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
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<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
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</transform>
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<transform xil_pn:end_ts="1590511156" xil_pn:in_ck="766507318003862528" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1590511156">
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<transform xil_pn:end_ts="1600256580" xil_pn:in_ck="3204048457877733613" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1600256580">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="OutOfDateForOutputs"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="InputRemoved"/>
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<status xil_pn:value="OutputChanged"/>
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<status xil_pn:value="OutputRemoved"/>
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<outfile xil_pn:name="MAX2871.vhd"/>
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<outfile xil_pn:name="MCP33131.vhd"/>
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<outfile xil_pn:name="ResetDelay.vhd"/>
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<outfile xil_pn:name="SPIConfig.vhd"/>
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<outfile xil_pn:name="Sampling.vhd"/>
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<outfile xil_pn:name="Sweep.vhd"/>
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<outfile xil_pn:name="Synchronizer.vhd"/>
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<outfile xil_pn:name="Test_MAX2871.vhd"/>
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<outfile xil_pn:name="Test_MCP33131.vhd"/>
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<outfile xil_pn:name="Test_PLL.vhd"/>
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<outfile xil_pn:name="Test_SPI.vhd"/>
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<outfile xil_pn:name="Test_SPICommands.vhd"/>
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<outfile xil_pn:name="Test_Sampling.vhd"/>
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<outfile xil_pn:name="Test_SinCos.vhd"/>
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<outfile xil_pn:name="Test_Sync.vhd"/>
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<outfile xil_pn:name="Test_Window.vhd"/>
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<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
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<outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
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<outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
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<outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
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<outfile xil_pn:name="spi_slave.vhd"/>
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<outfile xil_pn:name="top.vhd"/>
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<outfile xil_pn:name="window.vhd"/>
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</transform>
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<transform xil_pn:end_ts="1590511158" xil_pn:in_ck="4178816336447958013" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-3530939538078141760" xil_pn:start_ts="1590511156">
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<transform xil_pn:end_ts="1600256582" xil_pn:in_ck="3204048457877733613" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-7714428255597766630" xil_pn:start_ts="1600256580">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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@ -173,20 +212,24 @@
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<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputChanged"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="Test_Window_beh.prj"/>
|
||||
<outfile xil_pn:name="Test_Window_isim_beh.exe"/>
|
||||
<outfile xil_pn:name="fuse.log"/>
|
||||
<outfile xil_pn:name="isim"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
<outfile xil_pn:name="xilinxsim.ini"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1590511159" xil_pn:in_ck="6047462992229066111" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="6352116336892055917" xil_pn:start_ts="1590511158">
|
||||
<transform xil_pn:end_ts="1600256582" xil_pn:in_ck="-6256802959996678011" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-2271436731750578457" xil_pn:start_ts="1600256582">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForInputs"/>
|
||||
<status xil_pn:value="OutOfDateForProperties"/>
|
||||
<status xil_pn:value="OutOfDateForPredecessor"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="InputRemoved"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
<outfile xil_pn:name="Test_Window_isim_beh.wdb"/>
|
||||
<outfile xil_pn:name="isim.cmd"/>
|
||||
<outfile xil_pn:name="isim.log"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1588686459" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1588686459">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
@ -223,7 +266,7 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600202513" xil_pn:in_ck="-94812602667091528" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600202496">
|
||||
<transform xil_pn:end_ts="1600263408" xil_pn:in_ck="-1505308035655400832" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1600263388">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
@ -245,7 +288,7 @@
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600202519" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600202513">
|
||||
<transform xil_pn:end_ts="1600263414" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1600263408">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
@ -254,7 +297,7 @@
|
||||
<outfile xil_pn:name="top.ngd"/>
|
||||
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600202564" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600202519">
|
||||
<transform xil_pn:end_ts="1600263452" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1600263414">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
@ -268,7 +311,7 @@
|
||||
<outfile xil_pn:name="top_summary.xml"/>
|
||||
<outfile xil_pn:name="top_usage.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600202589" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600202564">
|
||||
<transform xil_pn:end_ts="1600263480" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1600263452">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
@ -282,7 +325,7 @@
|
||||
<outfile xil_pn:name="top_pad.txt"/>
|
||||
<outfile xil_pn:name="top_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600202602" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1600202589">
|
||||
<transform xil_pn:end_ts="1600263493" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1600263480">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
@ -328,7 +371,7 @@
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<status xil_pn:value="OutputRemoved"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1600202589" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600202583">
|
||||
<transform xil_pn:end_ts="1600263480" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1600263473">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
|
||||
@ -17,40 +17,40 @@
|
||||
<files>
|
||||
<file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
|
||||
</file>
|
||||
<file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SweepConfigMem.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SinCosMult.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Sampling.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
@ -60,19 +60,19 @@
|
||||
</file>
|
||||
<file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
|
||||
</file>
|
||||
<file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
@ -100,7 +100,7 @@
|
||||
</file>
|
||||
<file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
@ -114,7 +114,17 @@
|
||||
</file>
|
||||
<file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
|
||||
</file>
|
||||
<file xil_pn:name="window.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="139"/>
|
||||
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="139"/>
|
||||
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="139"/>
|
||||
</file>
|
||||
<file xil_pn:name="ipcore_dir/SweepConfigMem.xise" xil_pn:type="FILE_COREGENISE">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
@ -372,8 +382,8 @@
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_top" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_top" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_Window/uut" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.window" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
@ -391,7 +401,7 @@
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_top" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.window" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
@ -443,7 +453,7 @@
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_MCP33131|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_Window|behavior" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
|
||||
@ -158,6 +158,7 @@ architecture Behavioral of top is
|
||||
NEW_SAMPLE : IN std_logic;
|
||||
START : IN std_logic;
|
||||
SAMPLES : IN std_logic_vector(9 downto 0);
|
||||
WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
ADC_START : OUT std_logic;
|
||||
DONE : OUT std_logic;
|
||||
PRE_DONE : OUT std_logic;
|
||||
@ -305,6 +306,7 @@ architecture Behavioral of top is
|
||||
signal sampling_samples : std_logic_vector(9 downto 0);
|
||||
signal sampling_user_samples : std_logic_vector(9 downto 0);
|
||||
signal sampling_result : std_logic_vector(287 downto 0);
|
||||
signal sampling_window : std_logic_vector(1 downto 0);
|
||||
|
||||
-- Sweep signals
|
||||
signal sweep_points : std_logic_vector(12 downto 0);
|
||||
@ -542,6 +544,7 @@ begin
|
||||
PRE_DONE => open,
|
||||
START => sampling_start,
|
||||
SAMPLES => sampling_samples,
|
||||
WINDOW_TYPE => sampling_window,
|
||||
PORT1_I => sampling_result(287 downto 240),
|
||||
PORT1_Q => sampling_result(239 downto 192),
|
||||
PORT2_I => sampling_result(191 downto 144),
|
||||
@ -646,7 +649,7 @@ begin
|
||||
SOURCE_CE_EN => SOURCE_CE,
|
||||
LO_CE_EN => LO1_CE,
|
||||
LEDS => user_leds,
|
||||
WINDOW_SETTING => open,
|
||||
WINDOW_SETTING => sampling_window,
|
||||
INTERRUPT_ASSERTED => intr,
|
||||
RESET_MINMAX => adc_reset_minmax,
|
||||
SWEEP_HALTED => sweep_halted,
|
||||
|
||||
77
FPGA/VNA/window.vhd
Normal file
77
FPGA/VNA/window.vhd
Normal file
@ -0,0 +1,77 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 13:28:54 09/16/2020
|
||||
-- Design Name:
|
||||
-- Module Name: window - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use std.textio.all;
|
||||
use ieee.std_logic_textio.all;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
entity window is
|
||||
Port ( CLK : in STD_LOGIC;
|
||||
INDEX : in STD_LOGIC_VECTOR (6 downto 0);
|
||||
WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
VALUE : out STD_LOGIC_VECTOR (15 downto 0));
|
||||
end window;
|
||||
|
||||
architecture Behavioral of window is
|
||||
type window_data is array(127 downto 0) of std_logic_vector(15 downto 0);
|
||||
|
||||
impure function InitWindowDataFromFile (RomFileName : in string) return window_data is
|
||||
FILE romfile : text is in RomFileName;
|
||||
variable RomFileLine : line;
|
||||
variable rom : window_data;
|
||||
begin
|
||||
for i in window_data'range loop
|
||||
readline(romfile, RomFileLine);
|
||||
read(RomFileLine, rom(i));
|
||||
end loop;
|
||||
return rom;
|
||||
end function;
|
||||
|
||||
constant hann : window_data := InitWindowDataFromFile("Hann.dat");
|
||||
constant kaiser : window_data := InitWindowDataFromFile("Kaiser.dat");
|
||||
constant flattop : window_data := InitWindowDataFromFile("Flattop.dat");
|
||||
signal i : integer range 0 to 127;
|
||||
begin
|
||||
|
||||
i <= to_integer(unsigned(INDEX));
|
||||
|
||||
process(CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
case WINDOW_TYPE is
|
||||
when "00" => VALUE <= "0001000000000000";
|
||||
when "01" => VALUE <= kaiser(i);
|
||||
when "10" => VALUE <= hann(i);
|
||||
when "11" => VALUE <= flattop(i);
|
||||
when others => VALUE <= (others => '0');
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
import math
|
||||
import numpy as np
|
||||
|
||||
# Adapt these constants to your window requirements
|
||||
NUMBER_OF_COEFFICIENTS = 128
|
||||
@ -12,6 +13,10 @@ INCLUDE_AMPLITUDE_CORRECTION = True
|
||||
|
||||
# Don't change anything below this line
|
||||
|
||||
def bindigits(n, bits):
|
||||
s = bin(n & int("1"*bits, 2))[2:]
|
||||
return ("{0:0>%s}" % (bits)).format(s)
|
||||
|
||||
class Window:
|
||||
def __init__(self, name, function, correction):
|
||||
self.name = name
|
||||
@ -19,7 +24,7 @@ class Window:
|
||||
self.correction = correction
|
||||
|
||||
def StartFile(self):
|
||||
self.file = open(self.name+".txt", "w")
|
||||
self.file = open(self.name+".dat", "w")
|
||||
|
||||
def AddCoefficient(self, normalized_index):
|
||||
if not hasattr(self, 'file'):
|
||||
@ -31,14 +36,28 @@ class Window:
|
||||
# prevent overflow
|
||||
if value >= (2 ** (BITS_PER_COEFFICIENT-1)):
|
||||
value = value - 1
|
||||
output = "{0:b}".format(value)
|
||||
self.file.write(output.zfill(BITS_PER_COEFFICIENT)+"\n")
|
||||
output = bindigits(value, BITS_PER_COEFFICIENT)
|
||||
self.file.write(output+"\n")
|
||||
|
||||
def calc_hann(i):
|
||||
return math.sin(math.pi * i) ** 2
|
||||
|
||||
def calc_kaiser(i):
|
||||
return np.kaiser(NUMBER_OF_COEFFICIENTS, 9.4)[int(i * NUMBER_OF_COEFFICIENTS)]
|
||||
|
||||
def calc_flattop(i):
|
||||
a0 = 0.21557895
|
||||
a1 = 0.41663158
|
||||
a2 = 0.277263158
|
||||
a3 = 0.083578947
|
||||
a4 = 0.006947368
|
||||
return a0 - a1 * math.cos(2*math.pi*i) + a2 * math.cos(4*math.pi*i) - a3 * math.cos(6*math.pi*i) + a4 * math.cos(8*math.pi*i)
|
||||
|
||||
WindowList = []
|
||||
WindowList.append(Window("Hann", calc_hann, 2.0))
|
||||
WindowList.append(Window("Kaiser", calc_kaiser, 2.49))
|
||||
WindowList.append(Window("Flattop", calc_flattop, 4.18))
|
||||
|
||||
|
||||
for i in range(NUMBER_OF_COEFFICIENTS):
|
||||
norm_i = (i+0.5) / NUMBER_OF_COEFFICIENTS
|
||||
|
||||
Binary file not shown.
@ -174,6 +174,7 @@ ManualControlDialog::ManualControlDialog(Device &dev, QWidget *parent) :
|
||||
|
||||
connect(ui->Attenuator, qOverload<double>(&QDoubleSpinBox::valueChanged), [=](double) { UpdateDevice(); });
|
||||
connect(ui->Samples, qOverload<int>(&QSpinBox::valueChanged), [=](double) { UpdateDevice(); });
|
||||
connect(ui->cbWindow, qOverload<int>(&QComboBox::activated), [=](int) { UpdateDevice(); });
|
||||
|
||||
UpdateDevice();
|
||||
}
|
||||
@ -247,6 +248,7 @@ void ManualControlDialog::UpdateDevice()
|
||||
m.Port2EN = ui->Port2Enable->isChecked();
|
||||
m.RefEN = ui->RefEnable->isChecked();
|
||||
m.Samples = ui->Samples->value();
|
||||
m.WindowType = ui->cbWindow->currentIndex();
|
||||
|
||||
qDebug() << "Updating manual control state";
|
||||
|
||||
|
||||
@ -533,6 +533,37 @@
|
||||
</property>
|
||||
</widget>
|
||||
</item>
|
||||
<item row="1" column="0">
|
||||
<widget class="QLabel" name="label_15">
|
||||
<property name="text">
|
||||
<string>Window:</string>
|
||||
</property>
|
||||
</widget>
|
||||
</item>
|
||||
<item row="1" column="1">
|
||||
<widget class="QComboBox" name="cbWindow">
|
||||
<item>
|
||||
<property name="text">
|
||||
<string>None</string>
|
||||
</property>
|
||||
</item>
|
||||
<item>
|
||||
<property name="text">
|
||||
<string>Kaiser</string>
|
||||
</property>
|
||||
</item>
|
||||
<item>
|
||||
<property name="text">
|
||||
<string>Hann</string>
|
||||
</property>
|
||||
</item>
|
||||
<item>
|
||||
<property name="text">
|
||||
<string>Flat Top</string>
|
||||
</property>
|
||||
</item>
|
||||
</widget>
|
||||
</item>
|
||||
</layout>
|
||||
</item>
|
||||
</layout>
|
||||
|
||||
@ -284,7 +284,9 @@ void AppWindow::StartManualControl()
|
||||
{
|
||||
auto control = new ManualControlDialog(*device, this);
|
||||
connect(control, &QDialog::finished, [=](){
|
||||
if(device) {
|
||||
Mode::getActiveMode()->initializeDevice();
|
||||
}
|
||||
});
|
||||
control->show();
|
||||
}
|
||||
|
||||
@ -63,7 +63,7 @@ private:
|
||||
{&Startup.DefaultSweep.points, "Startup.DefaultSweep.points", 501},
|
||||
{&Startup.DefaultSweep.bandwidth, "Startup.DefaultSweep.bandwidth", 1000.0},
|
||||
{&Startup.DefaultSweep.excitation, "Startup.DefaultSweep.excitation", -10.00},
|
||||
{&Acquisition.alwaysExciteBothPorts, "Acquisition.alwaysExciteBothPorts", false},
|
||||
{&Acquisition.alwaysExciteBothPorts, "Acquisition.alwaysExciteBothPorts", true},
|
||||
}};
|
||||
};
|
||||
|
||||
|
||||
@ -1,412 +1,822 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.settings">
|
||||
|
||||
<cconfiguration id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410">
|
||||
|
||||
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410" moduleId="org.eclipse.cdt.core.settings" name="Debug">
|
||||
|
||||
<externalSettings/>
|
||||
|
||||
<extensions>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
|
||||
|
||||
</extensions>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410" name="Debug" parent="fr.ac6.managedbuild.config.gnu.cross.exe.debug" postannouncebuildStep="Generating hex and Printing size information:" postbuildStep="arm-none-eabi-objcopy -O binary "${BuildArtifactFileBaseName}.elf" "${BuildArtifactFileBaseName}.bin" && arm-none-eabi-objcopy -O ihex "${BuildArtifactFileBaseName}.elf" "${BuildArtifactFileBaseName}.hex" && arm-none-eabi-size "${BuildArtifactFileName}"">
|
||||
|
||||
<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410" name="Debug" optionalBuildProperties="org.eclipse.cdt.docker.launcher.containerbuild.property.volumes=,org.eclipse.cdt.docker.launcher.containerbuild.property.selectedvolumes=" parent="fr.ac6.managedbuild.config.gnu.cross.exe.debug" postannouncebuildStep="Generating hex and Printing size information:" postbuildStep="arm-none-eabi-objcopy -O binary "${BuildArtifactFileBaseName}.elf" "${BuildArtifactFileBaseName}.bin" && arm-none-eabi-objcopy -O ihex "${BuildArtifactFileBaseName}.elf" "${BuildArtifactFileBaseName}.hex" && arm-none-eabi-size "${BuildArtifactFileName}"">
|
||||
|
||||
<folderInfo id="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410." name="/" resourcePath="">
|
||||
|
||||
<toolChain id="fr.ac6.managedbuild.toolchain.gnu.cross.exe.debug.382532646" name="Ac6 STM32 MCU GCC" superClass="fr.ac6.managedbuild.toolchain.gnu.cross.exe.debug">
|
||||
|
||||
<option id="fr.ac6.managedbuild.option.gnu.cross.prefix.88691778" name="Prefix" superClass="fr.ac6.managedbuild.option.gnu.cross.prefix" useByScannerDiscovery="false" value="arm-none-eabi-" valueType="string"/>
|
||||
|
||||
<option id="fr.ac6.managedbuild.option.gnu.cross.mcu.112180732" name="Mcu" superClass="fr.ac6.managedbuild.option.gnu.cross.mcu" useByScannerDiscovery="false" value="STM32G431CBUx" valueType="string"/>
|
||||
|
||||
<option id="fr.ac6.managedbuild.option.gnu.cross.board.1874862682" name="Board" superClass="fr.ac6.managedbuild.option.gnu.cross.board" useByScannerDiscovery="false" value="VNA_embedded" valueType="string"/>
|
||||
<option id="fr.ac6.managedbuild.option.gnu.cross.core.1083960614" name="Core" superClass="fr.ac6.managedbuild.option.gnu.cross.core" useByScannerDiscovery="false" valueType="stringList">
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="fr.ac6.managedbuild.option.gnu.cross.core.1083960614" name="Core" superClass="fr.ac6.managedbuild.option.gnu.cross.core" useByScannerDiscovery="false" valueType="stringList">
|
||||
|
||||
<listOptionValue builtIn="false" value="ARM Cortex-M4"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="CM4"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="fr.ac6.managedbuild.option.gnu.cross.instructionSet.1455996549" name="Instruction Set" superClass="fr.ac6.managedbuild.option.gnu.cross.instructionSet" useByScannerDiscovery="false" value="fr.ac6.managedbuild.option.gnu.cross.instructionSet.thumbII" valueType="enumerated"/>
|
||||
|
||||
<option id="fr.ac6.managedbuild.option.gnu.cross.fpu.363601131" name="Floating point hardware" superClass="fr.ac6.managedbuild.option.gnu.cross.fpu" useByScannerDiscovery="false" value="fr.ac6.managedbuild.option.gnu.cross.fpu.fpv4-sp-d16" valueType="enumerated"/>
|
||||
|
||||
<option id="fr.ac6.managedbuild.option.gnu.cross.floatabi.1331315324" name="Floating-point ABI" superClass="fr.ac6.managedbuild.option.gnu.cross.floatabi" useByScannerDiscovery="false" value="fr.ac6.managedbuild.option.gnu.cross.floatabi.hard" valueType="enumerated"/>
|
||||
|
||||
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="fr.ac6.managedbuild.targetPlatform.gnu.cross.424800885" isAbstract="false" osList="all" superClass="fr.ac6.managedbuild.targetPlatform.gnu.cross"/>
|
||||
|
||||
<builder arguments="-j5" buildPath="${workspace_loc:/VNA_embedded}/Debug" command="make" id="fr.ac6.managedbuild.builder.gnu.cross.1807206174" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="fr.ac6.managedbuild.builder.gnu.cross">
|
||||
|
||||
<outputEntries>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="outputPath" name="Debug"/>
|
||||
|
||||
</outputEntries>
|
||||
|
||||
</builder>
|
||||
|
||||
<tool id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.1927263688" name="MCU GCC Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler">
|
||||
|
||||
<option defaultValue="gnu.c.optimization.level.none" id="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level.1492730557" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.c.optimization.level.debug" valueType="enumerated"/>
|
||||
|
||||
<option id="gnu.c.compiler.option.debugging.level.24507088" name="Debug Level" superClass="gnu.c.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.c.debugging.level.max" valueType="enumerated"/>
|
||||
<option id="gnu.c.compiler.option.include.paths.1399135431" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.include.paths.1399135431" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
|
||||
|
||||
<listOptionValue builtIn="false" value="../Inc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Application}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Application/Drivers}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Application/Drivers/USB}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value=""${workspace_loc:/${ProjName}/Application/Drivers/USB/Core/Inc}""/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/STM32G4xx_HAL_Driver/Inc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/include"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/CMSIS_RTOS"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Middlewares/Third_Party/FreeRTOS/Source/portable/GCC/ARM_CM4F"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USBPD_Library/Core/inc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USBPD_Library/Devices/STM32G4XX/inc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Middlewares/ST/STM32_USBPD_Library/../../../Drivers/STM32G4xx_HAL_Driver/Inc"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Device/ST/STM32G4xx/Include"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="../Drivers/CMSIS/Include"/>
|
||||
|
||||
</option>
|
||||
<option id="gnu.c.compiler.option.preprocessor.def.symbols.396181760" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
|
||||
<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.preprocessor.def.symbols.396181760" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
|
||||
|
||||
<listOptionValue builtIn="false" value="USE_FULL_LL_DRIVER"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="__weak="__attribute__((weak))""/>
|
||||
|
||||
<listOptionValue builtIn="false" value="USBPD_PORT_COUNT=1"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="USBPDCORE_LIB_PD3_FULL"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="_RTOS"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="_SNK"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="STM32G431xx"/>
|
||||
|
||||
<listOptionValue builtIn="false" value="__packed=__attribute__((__packed__))"/>
|
||||
|
||||
</option>
|
||||
|
||||
<option id="fr.ac6.managedbuild.gnu.c.compiler.option.misc.other.10179012" superClass="fr.ac6.managedbuild.gnu.c.compiler.option.misc.other" useByScannerDiscovery="false" value="-fmessage-length=0" valueType="string"/>
|
||||
|
||||
<option id="gnu.c.compiler.option.dialect.std.295832639" name="Language standard" superClass="gnu.c.compiler.option.dialect.std" useByScannerDiscovery="true" value="gnu.c.compiler.dialect.default" valueType="enumerated"/>
|
||||
|
||||
<option id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.fdata.915472139" name="Place the data in their own section (-fdata-sections)" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.fdata" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
||||
|
||||
<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.1184125608" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c"/>
|
||||
|
||||
<inputType id="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s.1283603594" superClass="fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.s"/>
|
||||
|
||||
</tool>
|
||||
|
||||
<tool id="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.1186634618" name="MCU G++ Compiler" superClass="fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler">
|
||||
|
||||
<option defaultValue="gnu.cpp.optimization.level.none" id="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level.1296454962" name="Optimization Level" superClass="fr.ac6.managedbuild.gnu.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="fr.ac6.managedbuild.gnu.cpp.optimization.level.debug" valueType="enumerated"/>
|
||||
|
||||
<option id="gnu.cpp.compiler.option.debugging.level.1713488101" name="Debug Level" superClass="gnu.cpp.compiler.option.debugging.level" useByScannerDiscovery="false" value="gnu.cpp.compiler.debugging.level.max" valueType="enumerated"/>
|
||||
<option id="gnu.cpp.compiler.option.include.paths.1375604176" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
|
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|
||||
<inputType id="fr.ac6.managedbuild.tool.gnu.cross.assembler.input.890950827" superClass="fr.ac6.managedbuild.tool.gnu.cross.assembler.input"/>
|
||||
|
||||
</tool>
|
||||
|
||||
</toolChain>
|
||||
|
||||
</folderInfo>
|
||||
|
||||
<sourceEntries>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="startup"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Middlewares"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Drivers"/>
|
||||
|
||||
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name="Src"/>
|
||||
|
||||
</sourceEntries>
|
||||
|
||||
</configuration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
|
||||
</cconfiguration>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
|
||||
<project id="VNA_embedded.fr.ac6.managedbuild.target.gnu.cross.exe.1886728023" name="Executable" projectType="fr.ac6.managedbuild.target.gnu.cross.exe"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||
|
||||
<storageModule moduleId="refreshScope" versionNumber="2">
|
||||
|
||||
<configuration configurationName="Debug">
|
||||
<resource resourceType="PROJECT" workspacePath="/VNA_embedded"/>
|
||||
|
||||
<resource resourceType="PROJECT" workspacePath="VNA_embedded"/>
|
||||
|
||||
</configuration>
|
||||
|
||||
<configuration configurationName="Release"/>
|
||||
|
||||
</storageModule>
|
||||
|
||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410;fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410.;fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.1186634618;fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp.1826809538">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410;fr.ac6.managedbuild.config.gnu.cross.exe.debug.1502405410.;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.1927263688;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.1184125608">
|
||||
|
||||
<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.release.1788779437;fr.ac6.managedbuild.config.gnu.cross.exe.release.1788779437.;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.1927263688;fr.ac6.managedbuild.tool.gnu.cross.c.compiler.input.c.1184125608">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
<scannerConfigBuildInfo instanceId="fr.ac6.managedbuild.config.gnu.cross.exe.release.1788779437;fr.ac6.managedbuild.config.gnu.cross.exe.release.1788779437.;fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.1186634618;fr.ac6.managedbuild.tool.gnu.cross.cpp.compiler.input.cpp.1826809538">
|
||||
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
|
||||
</scannerConfigBuildInfo>
|
||||
|
||||
</storageModule>
|
||||
|
||||
</cproject>
|
||||
|
||||
File diff suppressed because one or more lines are too long
@ -327,6 +327,7 @@ static Protocol::ManualControl DecodeManualControl(uint8_t *buf) {
|
||||
d.Port2EN = e.getBits(1);
|
||||
d.RefEN = e.getBits(1);
|
||||
e.get<uint32_t>(d.Samples);
|
||||
d.WindowType = e.getBits(2);
|
||||
return d;
|
||||
}
|
||||
static int16_t EncodeManualControl(Protocol::ManualControl d, uint8_t *buf,
|
||||
@ -353,6 +354,7 @@ static int16_t EncodeManualControl(Protocol::ManualControl d, uint8_t *buf,
|
||||
e.addBits(d.Port2EN, 1);
|
||||
e.addBits(d.RefEN, 1);
|
||||
e.add<uint32_t>(d.Samples);
|
||||
e.addBits(d.WindowType, 2);
|
||||
return e.getSize();
|
||||
}
|
||||
|
||||
|
||||
@ -95,6 +95,7 @@ using ManualControl = struct _manualControl {
|
||||
uint8_t Port2EN :1;
|
||||
uint8_t RefEN :1;
|
||||
uint32_t Samples;
|
||||
uint8_t WindowType :2;
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -137,6 +137,12 @@ void FPGA::Disable(Periphery p) {
|
||||
WriteRegister(Reg::SystemControl, SysCtrlReg);
|
||||
}
|
||||
|
||||
void FPGA::SetWindow(Window w) {
|
||||
SysCtrlReg &= ~0x0060;
|
||||
SysCtrlReg |= (int) w << 5;
|
||||
WriteRegister(Reg::SystemControl, SysCtrlReg);
|
||||
}
|
||||
|
||||
void FPGA::EnableInterrupt(Interrupt i) {
|
||||
ISRMaskReg |= (uint16_t) i;
|
||||
WriteRegister(Reg::InterruptMask, ISRMaskReg);
|
||||
|
||||
@ -85,6 +85,13 @@ enum class Samples {
|
||||
S91392 = 0x07,
|
||||
};
|
||||
|
||||
enum class Window {
|
||||
None = 0x00,
|
||||
Kaiser = 0x01,
|
||||
Hann = 0x02,
|
||||
Flattop = 0x03,
|
||||
};
|
||||
|
||||
bool Configure(Flash *f, uint32_t start_address, uint32_t bitstream_size);
|
||||
|
||||
using HaltedCallback = void(*)(void);
|
||||
@ -93,6 +100,7 @@ void SetNumberOfPoints(uint16_t npoints);
|
||||
void SetSamplesPerPoint(uint32_t nsamples);
|
||||
void Enable(Periphery p, bool enable = true);
|
||||
void Disable(Periphery p);
|
||||
void SetWindow(Window w);
|
||||
void EnableInterrupt(Interrupt i);
|
||||
void DisableInterrupt(Interrupt i);
|
||||
void WriteMAX2871Default(uint32_t *DefaultRegs);
|
||||
|
||||
@ -187,6 +187,11 @@ bool MAX2871::SetFrequency(uint64_t f) {
|
||||
|
||||
auto approx = Algorithm::BestRationalApproximation(fraction, 4095);
|
||||
|
||||
if(approx.denom == 1) {
|
||||
// M value must be at least 2
|
||||
approx.denom = 2;
|
||||
}
|
||||
|
||||
int32_t rem_approx = ((uint64_t) f_PFD * approx.num) / approx.denom;
|
||||
if(rem_approx != rem_f) {
|
||||
LOG_WARN("Best match is F=%u/M=%u, deviation of %luHz",
|
||||
|
||||
@ -340,6 +340,7 @@ bool VNA::ConfigureSweep(Protocol::SweepSettings s, SweepCallback cb) {
|
||||
// Si5351.SetCLK(1, IF1 + IF2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
|
||||
// Si5351.ResetPLL(Si5351C::PLL::B);
|
||||
// Enable mixers/amplifier/PLLs
|
||||
FPGA::SetWindow(FPGA::Window::None);
|
||||
FPGA::Enable(FPGA::Periphery::Port1Mixer);
|
||||
FPGA::Enable(FPGA::Periphery::Port2Mixer);
|
||||
FPGA::Enable(FPGA::Periphery::RefMixer);
|
||||
@ -407,6 +408,8 @@ bool VNA::ConfigureManual(Protocol::ManualControl m, StatusCallback cb) {
|
||||
FPGA::Samples::SPPRegister, 0,
|
||||
(FPGA::LowpassFilter) m.SourceHighLowpass);
|
||||
|
||||
FPGA::SetWindow((FPGA::Window) m.WindowType);
|
||||
|
||||
// Enable/Disable periphery
|
||||
FPGA::Enable(FPGA::Periphery::SourceChip, m.SourceHighCE);
|
||||
FPGA::Enable(FPGA::Periphery::SourceRF, m.SourceHighRFEN);
|
||||
@ -530,6 +533,7 @@ bool VNA::ConfigureGenerator(Protocol::GeneratorSettings g) {
|
||||
m.Port2EN = 0;
|
||||
m.RefEN = 0;
|
||||
m.Samples = 131072;
|
||||
m.WindowType = (int) FPGA::Window::None;
|
||||
// Select correct source
|
||||
if(g.frequency < BandSwitchFrequency) {
|
||||
m.SourceLowEN = 1;
|
||||
|
||||
@ -519,7 +519,7 @@ static void MX_UCPD1_Init(void)
|
||||
LL_DMA_SetMemorySize(DMA1, LL_DMA_CHANNEL_2, LL_DMA_MDATAALIGN_BYTE);
|
||||
|
||||
/* UCPD1 interrupt Init */
|
||||
NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
|
||||
NVIC_SetPriority(UCPD1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),6, 0));
|
||||
NVIC_EnableIRQ(UCPD1_IRQn);
|
||||
|
||||
/* USER CODE BEGIN UCPD1_Init 1 */
|
||||
@ -623,16 +623,16 @@ static void MX_DMA_Init(void)
|
||||
|
||||
/* DMA interrupt init */
|
||||
/* DMA1_Channel1_IRQn interrupt configuration */
|
||||
NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
|
||||
NVIC_SetPriority(DMA1_Channel1_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),6, 0));
|
||||
NVIC_EnableIRQ(DMA1_Channel1_IRQn);
|
||||
/* DMA1_Channel2_IRQn interrupt configuration */
|
||||
NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),5, 0));
|
||||
NVIC_SetPriority(DMA1_Channel2_IRQn, NVIC_EncodePriority(NVIC_GetPriorityGrouping(),6, 0));
|
||||
NVIC_EnableIRQ(DMA1_Channel2_IRQn);
|
||||
/* DMA1_Channel3_IRQn interrupt configuration */
|
||||
HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 5, 0);
|
||||
HAL_NVIC_SetPriority(DMA1_Channel3_IRQn, 6, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA1_Channel3_IRQn);
|
||||
/* DMA1_Channel4_IRQn interrupt configuration */
|
||||
HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 5, 0);
|
||||
HAL_NVIC_SetPriority(DMA1_Channel4_IRQn, 6, 0);
|
||||
HAL_NVIC_EnableIRQ(DMA1_Channel4_IRQn);
|
||||
|
||||
}
|
||||
|
||||
@ -508,10 +508,10 @@ void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd)
|
||||
/* Peripheral clock enable */
|
||||
__HAL_RCC_USB_CLK_ENABLE();
|
||||
/* USB interrupt Init */
|
||||
HAL_NVIC_SetPriority(USB_HP_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(USB_HP_IRQn);
|
||||
HAL_NVIC_SetPriority(USB_LP_IRQn, 5, 0);
|
||||
HAL_NVIC_EnableIRQ(USB_LP_IRQn);
|
||||
HAL_NVIC_SetPriority(USB_HP_IRQn, 6, 0);
|
||||
// HAL_NVIC_EnableIRQ(USB_HP_IRQn);
|
||||
HAL_NVIC_SetPriority(USB_LP_IRQn, 6, 0);
|
||||
// HAL_NVIC_EnableIRQ(USB_LP_IRQn);
|
||||
/* USER CODE BEGIN USB_MspInit 1 */
|
||||
|
||||
/* USER CODE END USB_MspInit 1 */
|
||||
|
||||
@ -148,10 +148,10 @@ Mcu.UserName=STM32G431CBUx
|
||||
MxCube.Version=5.2.1
|
||||
MxDb.Version=DB.5.0.21
|
||||
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.DMA1_Channel1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
|
||||
NVIC.DMA1_Channel2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
|
||||
NVIC.DMA1_Channel3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
|
||||
NVIC.DMA1_Channel4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true
|
||||
NVIC.DMA1_Channel1_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
|
||||
NVIC.DMA1_Channel2_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
|
||||
NVIC.DMA1_Channel3_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
|
||||
NVIC.DMA1_Channel4_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true
|
||||
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
@ -163,9 +163,9 @@ NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:true
|
||||
NVIC.TIM1_TRG_COM_TIM17_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true
|
||||
NVIC.TimeBase=TIM1_TRG_COM_TIM17_IRQn
|
||||
NVIC.TimeBaseIP=TIM17
|
||||
NVIC.UCPD1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:false
|
||||
NVIC.USB_HP_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
|
||||
NVIC.USB_LP_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true
|
||||
NVIC.UCPD1_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:false
|
||||
NVIC.USB_HP_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
|
||||
NVIC.USB_LP_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true
|
||||
NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
|
||||
PA1.GPIOParameters=GPIO_Label
|
||||
PA1.GPIO_Label=FPGA_AUX1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user