From df8fa25935ea86474bda93e6fcf23de1a8ef675f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jan=20K=C3=A4berich?= Date: Sat, 19 Nov 2022 16:26:38 +0100 Subject: [PATCH] Increase settling time for PLLs --- Software/VNA_embedded/Application/Manual.cpp | 2 +- Software/VNA_embedded/Application/SpectrumAnalyzer.cpp | 2 +- Software/VNA_embedded/Application/VNA.cpp | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Software/VNA_embedded/Application/Manual.cpp b/Software/VNA_embedded/Application/Manual.cpp index 54bf7f8..e1bc3a8 100644 --- a/Software/VNA_embedded/Application/Manual.cpp +++ b/Software/VNA_embedded/Application/Manual.cpp @@ -54,7 +54,7 @@ void Manual::Setup(Protocol::ManualControlV1 m) { // Configure single sweep point FPGA::WriteSweepConfig(0, !m.SourceHighband, Source.GetRegisters(), - LO1.GetRegisters(), m.attenuator, 0, FPGA::SettlingTime::us20, + LO1.GetRegisters(), m.attenuator, 0, FPGA::SettlingTime::us60, FPGA::Samples::SPPRegister, 0, (FPGA::LowpassFilter) m.SourceHighLowpass); diff --git a/Software/VNA_embedded/Application/SpectrumAnalyzer.cpp b/Software/VNA_embedded/Application/SpectrumAnalyzer.cpp index 1bb2033..152ac1a 100644 --- a/Software/VNA_embedded/Application/SpectrumAnalyzer.cpp +++ b/Software/VNA_embedded/Application/SpectrumAnalyzer.cpp @@ -172,7 +172,7 @@ static void StartNextSample() { // Configure the sampling in the FPGA FPGA::WriteSweepConfig(0, trackingLowband, Source.GetRegisters(), LO1.GetRegisters(), attenuator, - trackingFreq, FPGA::SettlingTime::us20, FPGA::Samples::SPPRegister, 0, + trackingFreq, FPGA::SettlingTime::us60, FPGA::Samples::SPPRegister, 0, FPGA::LowpassFilter::Auto); FPGA::StartSweep(); diff --git a/Software/VNA_embedded/Application/VNA.cpp b/Software/VNA_embedded/Application/VNA.cpp index cb6fe80..0787a9d 100644 --- a/Software/VNA_embedded/Application/VNA.cpp +++ b/Software/VNA_embedded/Application/VNA.cpp @@ -263,7 +263,7 @@ bool VNA::Setup(Protocol::SweepSettings s) { } FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(), - LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us20, + LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us60, FPGA::Samples::SPPRegister, needs_halt); last_lowband = lowband; }