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Increase settling time for PLLs

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This commit is contained in:
Jan Käberich 2022-11-19 16:26:38 +01:00
parent 32e2a4d96d
commit df8fa25935
3 changed files with 3 additions and 3 deletions
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2
Software/VNA_embedded/Application/Manual.cpp
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@ -54,7 +54,7 @@ void Manual::Setup(Protocol::ManualControlV1 m) {
// Configure single sweep point // Configure single sweep point
FPGA::WriteSweepConfig(0, !m.SourceHighband, Source.GetRegisters(), FPGA::WriteSweepConfig(0, !m.SourceHighband, Source.GetRegisters(),
LO1.GetRegisters(), m.attenuator, 0, FPGA::SettlingTime::us20, LO1.GetRegisters(), m.attenuator, 0, FPGA::SettlingTime::us60,
FPGA::Samples::SPPRegister, 0, FPGA::Samples::SPPRegister, 0,
(FPGA::LowpassFilter) m.SourceHighLowpass); (FPGA::LowpassFilter) m.SourceHighLowpass);

2
Software/VNA_embedded/Application/SpectrumAnalyzer.cpp
View File

@ -172,7 +172,7 @@ static void StartNextSample() {
// Configure the sampling in the FPGA // Configure the sampling in the FPGA
FPGA::WriteSweepConfig(0, trackingLowband, Source.GetRegisters(), LO1.GetRegisters(), attenuator, FPGA::WriteSweepConfig(0, trackingLowband, Source.GetRegisters(), LO1.GetRegisters(), attenuator,
trackingFreq, FPGA::SettlingTime::us20, FPGA::Samples::SPPRegister, 0, trackingFreq, FPGA::SettlingTime::us60, FPGA::Samples::SPPRegister, 0,
FPGA::LowpassFilter::Auto); FPGA::LowpassFilter::Auto);
FPGA::StartSweep(); FPGA::StartSweep();

2
Software/VNA_embedded/Application/VNA.cpp
View File

@ -263,7 +263,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
} }
FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(), FPGA::WriteSweepConfig(i, lowband, Source.GetRegisters(),
LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us20, LO1.GetRegisters(), attenuator, freq, FPGA::SettlingTime::us60,
FPGA::Samples::SPPRegister, needs_halt); FPGA::Samples::SPPRegister, needs_halt);
last_lowband = lowband; last_lowband = lowband;
} }