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evaluate AUX3 in standby state

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This commit is contained in:
Andre Dunford 2022-12-20 01:16:22 -08:00
parent fc8eee58e7
commit ec5e0e208c
5 changed files with 11 additions and 1 deletions
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4
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp
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@ -284,6 +284,10 @@ bool FPGA::InitiateSampleRead(ReadCallback cb) {
return true;
}
bool FPGA::IsSweepActive() {
return isHigh(AUX3);
}
static int64_t assembleSampleResultValue(uint8_t *raw) {
// LOG_DEBUG("Raw: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x", raw[4], raw[5], raw[2], raw[3], raw[1], raw[0]);
return sign_extend_64(

1
Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp
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@ -135,6 +135,7 @@ ADCLimits GetADCLimits();
void ResetADCLimits();
bool ResumeHaltedSweep();
uint16_t GetStatus();
bool IsSweepActive();
void OverwriteHardware(uint8_t attenuation, LowpassFilter filter, bool lowband, bool port1_enabled, bool port2_enabled);
void DisableHardwareOverwrite();

2
Software/VNA_embedded/Application/Hardware.cpp
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@ -303,7 +303,7 @@ bool HW::TimedOut() {
auto bufISR = lastISR;
uint64_t now = Delay::get_us();
uint64_t timeSinceLast = now - bufISR;
if(activeMode != Mode::Idle && activeMode != Mode::Generator && !VNA::GetStandbyMode() && timeSinceLast > timeout) {
if(activeMode != Mode::Idle && activeMode != Mode::Generator && !VNA::IsWaitingInStandby() && timeSinceLast > timeout) {
LOG_WARN("Timed out, last ISR was at %lu%06lu, now %lu%06lu"
, (uint32_t) (bufISR / 1000000), (uint32_t)(bufISR%1000000)
, (uint32_t) (now / 1000000), (uint32_t)(now%1000000));

4
Software/VNA_embedded/Application/VNA.cpp
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@ -278,6 +278,10 @@ bool VNA::GetStandbyMode() {
return settings.standby;
}
bool VNA::IsWaitingInStandby() {
return settings.standby && !FPGA::IsSweepActive();
}
static void PassOnData() {
Protocol::PacketInfo info;
info.type = Protocol::PacketType::VNADatapoint;

1
Software/VNA_embedded/Application/VNA.hpp
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@ -9,6 +9,7 @@ namespace VNA {
bool Setup(Protocol::SweepSettings s);
void InitiateSweep();
bool GetStandbyMode();
bool IsWaitingInStandby();
bool MeasurementDone(const FPGA::SamplingResult &result);
void Work();
void SweepHalted();