Remove IFTable limitation, calculate 2.LO shift on the fly
This commit is contained in:
Jan Käberich
parent
df8fa25935
commit
ec6fae5822
@ -23,6 +23,7 @@
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static Protocol::SweepSettings settings;
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static uint16_t pointCnt;
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static uint8_t stageCnt;
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static uint32_t last_LO2;
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static double logMultiplier, logFrequency;
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static Protocol::VNADatapoint<32> data;
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static bool active = false;
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@ -37,15 +38,6 @@ static bool zerospan;
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static constexpr uint8_t sourceHarmonic = 5;
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static constexpr uint8_t LOHarmonic = 3;
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using IFTableEntry = struct {
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uint16_t pointCnt;
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uint8_t clkconfig[8];
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};
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static constexpr uint16_t IFTableNumEntries = 500;
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static IFTableEntry IFTable[IFTableNumEntries];
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static uint16_t IFTableIndexCnt = 0;
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static constexpr float alternativeSamplerate = 914285.7143f;
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static constexpr uint8_t alternativePrescaler = 102400000UL / alternativeSamplerate;
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static_assert(alternativePrescaler * alternativeSamplerate == 102400000UL, "alternative ADCSamplerate can not be reached exactly");
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@ -77,6 +69,42 @@ static uint64_t getPointFrequency(uint16_t pointNum) {
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}
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}
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static void setPLLFrequencies(uint64_t f) {
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if(f > HW::Info.limits_maxFreq) {
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Source.SetFrequency(f / sourceHarmonic);
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LO1.SetFrequency((f + HW::getIF1()) / LOHarmonic);
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} else {
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if(f >= HW::BandSwitchFrequency) {
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Source.SetFrequency(f);
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}
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LO1.SetFrequency(f + HW::getIF1());
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}
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}
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static bool needs2LOshift(uint64_t f, uint32_t current2LO, uint32_t IFBW, uint32_t *new2LO) {
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// Check if 2.LO needs to be shifted
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uint64_t actualSource, actual1LO;
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actualSource = Source.GetActualFrequency();
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actual1LO = LO1.GetActualFrequency();
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if(f > HW::Info.limits_maxFreq) {
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actualSource *= sourceHarmonic;
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actual1LO *= LOHarmonic;
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} else if(f < HW::BandSwitchFrequency) {
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// can use the lowband PLL with high frequency resolution, assume perfect frequency match
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actualSource = f;
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}
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uint32_t actualFirstIF = actual1LO - actualSource;
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uint32_t actualFinalIF = actualFirstIF - current2LO;
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uint32_t IFdeviation = abs(actualFinalIF - HW::getIF2());
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if(IFdeviation > IFBW / 2) {
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*new2LO = actualFirstIF - HW::getIF2();
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return true;
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} else {
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// no shift required
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return false;
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}
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}
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bool VNA::Setup(Protocol::SweepSettings s) {
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VNA::Stop();
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vTaskDelay(5);
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@ -130,108 +158,48 @@ bool VNA::Setup(Protocol::SweepSettings s) {
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FPGA::WriteMAX2871Default(Source.GetRegisters());
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uint32_t last_LO2 = HW::getIF1() - HW::getIF2();
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last_LO2 = HW::getIF1() - HW::getIF2();
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Si5351.SetCLK(SiChannel::Port1LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::Port2LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::RefLO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.ResetPLL(Si5351C::PLL::B);
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Si5351.WaitForLock(Si5351C::PLL::B, 10);
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IFTableIndexCnt = 0;
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zerospan = (s.f_start == s.f_stop) && (s.cdbm_excitation_start == s.cdbm_excitation_stop);
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bool last_lowband = false;
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// invalidate first entry of IFTable, preventing switing of 2.LO in halted callback
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IFTable[0].pointCnt = 0xFFFF;
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uint16_t pointsWithoutHalt = 0;
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// Transfer PLL configuration to FPGA
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for (uint16_t i = 0; i < settings.points; i++) {
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bool harmonic_mixing = false;
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uint64_t freq = getPointFrequency(i);
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int16_t power = s.cdbm_excitation_start + (s.cdbm_excitation_stop - s.cdbm_excitation_start) * i / (settings.points - 1);
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freq = Cal::FrequencyCorrectionToDevice(freq);
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if(freq > 6000000000ULL) {
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harmonic_mixing = true;
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}
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// SetFrequency only manipulates the register content in RAM, no SPI communication is done.
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// No mode-switch of FPGA necessary here.
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bool needs_halt = false;
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uint64_t actualSourceFreq;
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bool lowband = false;
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if (freq < HW::BandSwitchFrequency) {
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needs_halt = true;
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lowband = true;
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actualSourceFreq = freq;
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} else {
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uint64_t srcFreq = freq;
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if(harmonic_mixing) {
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srcFreq /= sourceHarmonic;
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}
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Source.SetFrequency(srcFreq);
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actualSourceFreq = Source.GetActualFrequency();
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if(harmonic_mixing) {
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actualSourceFreq *= sourceHarmonic;
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}
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if(i == 0) {
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// halt before first point (makes sure that the 2.LO gets configured correctly if it was shifted for the last point in
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// the previous sweep
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needs_halt = true;
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}
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// SetFrequency only manipulates the register content in RAM, no SPI communication is done.
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// No mode-switch of FPGA necessary here.
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setPLLFrequencies(freq);
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if(s.suppressPeaks) {
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if(needs2LOshift(freq, last_LO2, actualBandwidth, &last_LO2)) {
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needs_halt = true;
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}
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}
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if (last_lowband && !lowband) {
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// additional halt before first highband point to enable highband source
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needs_halt = true;
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}
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uint64_t LOFreq = freq + HW::getIF1();
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if(harmonic_mixing) {
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LOFreq /= LOHarmonic;
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}
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LO1.SetFrequency(LOFreq);
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uint64_t actualLO1 = LO1.GetActualFrequency();
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if(harmonic_mixing) {
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actualLO1 *= LOHarmonic;
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}
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uint32_t actualFirstIF = actualLO1 - actualSourceFreq;
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uint32_t actualFinalIF = actualFirstIF - last_LO2;
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uint32_t IFdeviation = abs(actualFinalIF - HW::getIF2());
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bool needs_LO2_shift = false;
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if(IFdeviation > actualBandwidth / 2) {
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needs_LO2_shift = true;
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}
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if (s.suppressPeaks && needs_LO2_shift) {
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if (IFTableIndexCnt < IFTableNumEntries) {
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// still room in table
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needs_halt = true;
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IFTable[IFTableIndexCnt].pointCnt = i;
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if(IFTableIndexCnt < IFTableNumEntries - 1) {
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// Configure LO2 for the changed IF1. This is not necessary right now but it will generate
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// the correct clock settings
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last_LO2 = actualFirstIF - HW::getIF2();
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LOG_INFO("Changing 2.LO to %lu at point %lu (%lu%06luHz) to reach correct 2.IF frequency (1.LO: %lu%06luHz, 1.IF: %lu%06luHz)",
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last_LO2, i, (uint32_t ) (freq / 1000000),
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(uint32_t ) (freq % 1000000), (uint32_t ) (actualLO1 / 1000000),
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(uint32_t ) (actualLO1 % 1000000), (uint32_t ) (actualFirstIF / 1000000),
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(uint32_t ) (actualFirstIF % 1000000));
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} else {
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// last entry in IF table, revert LO2 to default
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last_LO2 = HW::getIF1() - HW::getIF2();
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}
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Si5351.SetCLK(SiChannel::RefLO2, last_LO2,
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Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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// store calculated clock configuration for later change
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Si5351.ReadRawCLKConfig(SiChannel::RefLO2, IFTable[IFTableIndexCnt].clkconfig);
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IFTableIndexCnt++;
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needs_LO2_shift = false;
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}
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}
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if(needs_LO2_shift) {
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// if shift is still needed either peak suppression is disabled or no more room in IFTable was available
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LOG_WARN(
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"PLL deviation of %luHz for measurement at %lu%06luHz, will cause a peak",
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IFdeviation, (uint32_t ) (freq / 1000000), (uint32_t ) (freq % 1000000));
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}
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// halt on regular intervals to prevent USB buffer overflow
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if(!needs_halt) {
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@ -239,8 +207,7 @@ bool VNA::Setup(Protocol::SweepSettings s) {
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if(pointsWithoutHalt > maxPointsBetweenHalts) {
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needs_halt = true;
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}
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}
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if(needs_halt) {
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} else {
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pointsWithoutHalt = 0;
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}
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@ -286,7 +253,6 @@ bool VNA::Setup(Protocol::SweepSettings s) {
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FPGA::Enable(FPGA::Periphery::PortSwitch);
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pointCnt = 0;
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stageCnt = 0;
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IFTableIndexCnt = 0;
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adcShifted = false;
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active = true;
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// Enable new data and sweep halt interrupt
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@ -344,7 +310,6 @@ bool VNA::MeasurementDone(const FPGA::SamplingResult &result) {
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if (pointCnt >= settings.points) {
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// reached end of sweep, start again
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pointCnt = 0;
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IFTableIndexCnt = 0;
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// request to trigger work function
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return true;
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}
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@ -376,22 +341,11 @@ void VNA::SweepHalted() {
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// are handled through the STM::DispatchToInterrupt functionality, ensuring that they do not interrupt each other
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STM::DispatchToInterrupt([](){
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LOG_DEBUG("Halted before point %d", pointCnt);
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// Check if IF table has entry at this point
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if (IFTableIndexCnt < IFTableNumEntries && IFTable[IFTableIndexCnt].pointCnt == pointCnt) {
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Si5351.WriteRawCLKConfig(SiChannel::Port1LO2, IFTable[IFTableIndexCnt].clkconfig);
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Si5351.WriteRawCLKConfig(SiChannel::Port2LO2, IFTable[IFTableIndexCnt].clkconfig);
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Si5351.WriteRawCLKConfig(SiChannel::RefLO2, IFTable[IFTableIndexCnt].clkconfig);
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Si5351.ResetPLL(Si5351C::PLL::B);
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IFTableIndexCnt++;
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Si5351.WaitForLock(Si5351C::PLL::B, 10);
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// PLL reset causes the 2.LO to turn off briefly and then ramp on back, needs delay before next point
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Delay::us(1500);
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}
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bool adcShiftRequired = false;
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uint64_t frequency = getPointFrequency(pointCnt);
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int16_t power = settings.cdbm_excitation_start
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+ (settings.cdbm_excitation_stop - settings.cdbm_excitation_start)
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* pointCnt / (settings.points - 1);
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bool adcShiftRequired = false;
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if (frequency < HW::BandSwitchFrequency) {
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auto driveStrength = fixedPowerLowband;
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if(!settings.fixedPowerSetting) {
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@ -432,6 +386,20 @@ void VNA::SweepHalted() {
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Si5351.Disable(SiChannel::LowbandSource);
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FPGA::Enable(FPGA::Periphery::SourceRF);
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}
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if(settings.suppressPeaks) {
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// does not actually change PLL settings, just calculates the register values and
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// is required to determine the need for a 2.LO shift
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setPLLFrequencies(frequency);
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if(needs2LOshift(frequency, last_LO2, actualBandwidth, &last_LO2)) {
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Si5351.SetCLK(SiChannel::Port1LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::Port2LO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.SetCLK(SiChannel::RefLO2, last_LO2, Si5351C::PLL::B, Si5351C::DriveStrength::mA2);
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Si5351.ResetPLL(Si5351C::PLL::B);
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Si5351.WaitForLock(Si5351C::PLL::B, 10);
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// PLL reset causes the 2.LO to turn off briefly and then ramp on back, needs delay before next point
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Delay::us(1500);
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}
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}
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if (pointCnt == 0) {
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HAL_Delay(2);
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