Test of DFT implementation in FPGA

Documentation/DeveloperInfo/FPGA_protocol.tex

@@ -88,7 +88,8 @@ The word received while transmitting the command word is the interrupt status re
 \begin{center}
 \begin{tikzpicture}
 \bitrect{16}{16-\bit}
-\robits{0}{11}{reserved}
+\robits{0}{10}{reserved}
+\rwbits{10}{1}{DFT}
 \rwbits{11}{1}{SH}
 \rwbits{12}{1}{OR}
 \rwbits{13}{1}{ND}
@@ -97,6 +98,7 @@ The word received while transmitting the command word is the interrupt status re
 \end{tikzpicture}
 \end{center}
 \begin{itemize}
+\item \textbf{DFT:} New DFT result available (see section~\ref{dft}).
 \item \textbf{SH:} Sweep halted due to halt bit set. Sweep will be resumed once the resume command is issued.
 \item \textbf{OR:} Data overrun occured (only cleared by resetting the FPGA)
 \item \textbf{ND:} New data available
@@ -111,8 +113,8 @@ Writing a register requires the transfer of two words: First the control word se
 \rwbits{0}{1}{1}
 \rwbits{1}{1}{0}
 \rwbits{2}{1}{0}
-\robits{3}{9}{reserved}
+\robits{3}{8}{reserved}
-\rwbits{12}{4}{Register Address}
+\rwbits{11}{5}{Register Address}
 \end{tikzpicture}
 \begin{tikzpicture}
 \bitrect{16}{16-\bit}
@@ -145,7 +147,7 @@ Initiate the reading of sampling data by sending the command word:
 \robits{3}{13}{reserved}
 \end{tikzpicture}
 \end{center}
-Afterwards, read 18 words before setting NSS high. These 18 words will contain the sampling result (see section~\ref{result}), transmitted with the least significant word first.
+Afterwards, read up to 19 words before setting NSS high. These 19 words will contain the sampling result (see section~\ref{result}), transmitted with the least significant word first.
 
 \subsection{Resuming a halted sweep}
 When the halt bit is set in the SweepConfig, the FPGA will configure the Source and LO as requested but will not start the settling timer (and subsequently the sampling process) until this resume command is issued. The halted sweep is indicated by the sweep halted bit in the status register.
@@ -213,12 +215,77 @@ Issuing this command result in all minimum values set to 32767 and all maximum v
 \end{tikzpicture}
 \end{center}
 
+\subsection{Reading the DFT result}
+Initiate the reading of the DFT result (see section~\ref{dft}) by sending the command word:
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{1}{1}
+\rwbits{1}{1}{0}
+\rwbits{2}{1}{1}
+\robits{3}{13}{reserved}
+\end{tikzpicture}
+\end{center}
+Afterwards, read 12 words before setting NSS high. These 12 words will contain the first bin of the DFT, the least significant word is transmitted first:
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{192-\bit}
+\rwbits{0}{16}{Port 1 I[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{176-\bit}
+\rwbits{0}{16}{Port 1 I[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{168-\bit}
+\rwbits{0}{16}{Port 1 I[15:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{144-\bit}
+\rwbits{0}{16}{Port 1 Q[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{128-\bit}
+\rwbits{0}{16}{Port 1 Q[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{112-\bit}
+\rwbits{0}{16}{Port 1 Q[15:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{96-\bit}
+\rwbits{0}{16}{Port 2 I[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{80-\bit}
+\rwbits{0}{16}{Port 2 I[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{64-\bit}
+\rwbits{0}{16}{Port 2 I[15:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{48-\bit}
+\rwbits{0}{16}{Port 2 Q[47:32]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{32-\bit}
+\rwbits{0}{16}{Port 2 Q[31:16]}
+\end{tikzpicture}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{Port 2 Q[15:0]}
+\end{tikzpicture}
+\end{center}
+Repeating this procedure will return the next DFT bin. For each bin, the CS pin has to be toggled and the command word needs to be sent again (each DFT bin requires a new SPI transaction). The DFT interrupt is reset once all bins have been read. Alternatively, toggling the DFT off and on (by disabling and enabling its interrupt) will also reset the interrupt flag.
+
 \section{Registers}
 \subsection{Interrupt Mask Register: 0x00}
 \begin{center}
 \begin{tikzpicture}
 \bitrect{16}{16-\bit}
-\robits{0}{11}{reserved}
+\robits{0}{10}{reserved}
+\rwbits{10}{1}{DFTIE}
 \rwbits{11}{1}{SHIE}
 \rwbits{12}{1}{ORIE}
 \rwbits{13}{1}{NDIE}
@@ -227,6 +294,7 @@ Issuing this command result in all minimum values set to 32767 and all maximum v
 \end{tikzpicture}
 \end{center}
 \begin{itemize}
+\item \textbf{DFTIE:} DFT interrupt enable. This bit also enables the DFT (see section~\ref{dft}).
 \item \textbf{SHIE:} Sweep halted interrupt enable
 \item \textbf{ORIE:} Data overrun interrupt enable 
 \item \textbf{NDIE:} New data interrupt enable
@@ -244,10 +312,11 @@ Issuing this command result in all minimum values set to 32767 and all maximum v
 The register contains the number of points per sweep negative one, e.g. set to 11b if the sweep contains four points.
 
 \subsection{Samples Per Point Register: 0x02}
+\label{reg:spp}
 \begin{center}
 \begin{tikzpicture}
 \bitrect{16}{16-\bit}
-\robits{0}{6}{reserved}
+\robits{0}{3}{reserved}
 \rwbits{3}{13}{SPP[12:0]}
 \end{tikzpicture}
 \end{center}
@@ -306,6 +375,7 @@ Setting & Window type\\
 \end{itemize}
 
 \subsection{ADC Prescaler register: 0x04}
+\label{reg:ADC}
 \begin{center}
 \begin{tikzpicture}
 \bitrect{16}{16-\bit}
@@ -320,6 +390,7 @@ The minimum value for this register is 111, which results in a samplerate of rou
 \end{itemize}
 
 \subsection{Phase Increment: 0x05}
+\label{reg:phaseinc}
 \begin{center}
 \begin{tikzpicture}
 \bitrect{16}{16-\bit}
@@ -371,6 +442,60 @@ See datasheet of MAX2871 for bit descriptions. Bits for the fields N, FRAC, M, V
 \end{tikzpicture}
 \end{center}
 
+\subsection{DFT registers}
+\label{dft}
+In addition to the single bin DFT configured through the ADC prescaler and phase increment registers (see \ref{reg:ADC} and \ref{reg:phaseinc}), the FPGA also includes a multiple point DFT. This DFT only operates on the port 1 and port 2 receivers and is intended to speed up spectrum analyzer measurements. If enabled, the DFT runs in parallel to all other calculations.
+
+The DFT has a fixed number of bins (64), but the frequencies these bins correspond to can be changed.
+
+\subsubsection{Number of samples: 0x10}
+\label{reg:dft-nsamples}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{DFT\_SAMPLES[15:0]}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{DFT\_SAMPLES[15:0]:} Amount of samples the DFT should take. This should always match the number of samples configured with the Samples Per Point register (see~\ref{reg:spp}).
+\end{itemize}
+
+\subsubsection{Window increment: 0x11}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{DFT\_WINDOW\_INC[15:0]}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{DFT\_WINDOW\_INC[15:0]:} Window increment value after each sample. This should always be set in such a way, that the window is iterated over exactly once after all samples configured with DFT\_SAMPLES (see \ref{reg:dft-nsamples}) have been taken.
+$$ TODO: formula $$
+\end{itemize}
+
+\subsubsection{DFT\_FIRST\_BIN: 0x12}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{DFT\_FIRST\_BIN[15:0]}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{DFT\_FIRST\_BIN[15:0]:} This value determines the frequency corresponding to the first DFT bin.
+$$ f_{firstBin} =  \frac{SR_{ADC} * DFT\_FIRST\_BIN}{2^{16}}$$
+\end{itemize}
+
+\subsubsection{DFT\_FREQ\_SPACING: 0x13}
+\begin{center}
+\begin{tikzpicture}
+\bitrect{16}{16-\bit}
+\rwbits{0}{16}{DFT\_FREQ\_SPACING[15:0]}
+\end{tikzpicture}
+\end{center}
+\begin{itemize}
+\item \textbf{DFT\_FREQ\_SPACING[15:0]:} This value determines the frequency difference between bins.
+$$ \Delta f =  \frac{SR_{ADC} * DFT\_FREQ\_SPACING}{2^{24}}$$
+\end{itemize}
+
 \section{SweepConfig}
 \label{sweepconfig}
 The SweepConfig contains data for the source and LO1 PLL as well as the attenuator and source filter. Each point in the sweep, needs a valid SweepConfig before the sweep is started.
@@ -458,9 +583,15 @@ Setting & Selected Band\\
 
 \section{Sampling Result}
 \label{result}
-Each point in the sweep generates two sampling results. The first one contains the measurement when the source was routed to Port 1, the second sampling result was taken when the source was routed to Port 2. The sampling result does not indicate which point in the sweep it belongs to, that information is implicitly given by the order of transmitted sampling results.
+Each point in the sweep generates two sampling results. The first one contains the measurement when the source was routed to Port 1, the second sampling result was taken when the source was routed to Port 2. 
 \begin{center}
 \begin{tikzpicture}
+\bitrect{16}{304-\bit}
+\rwbits{0}{1}{SRC}
+\robits{1}{2}{reserved}
+\rwbits{3}{13}{POINT\_NUMBER[12:0]}
+\end{tikzpicture}
+\begin{tikzpicture}
 \bitrect{16}{288-\bit}
 \rwbits{0}{16}{Port 1 I[47:32]}
 \end{tikzpicture}

FPGA/VNA/DFT.vhd

@@ -47,6 +47,28 @@ entity DFT is
 end DFT;
 
 architecture Behavioral of DFT is
+COMPONENT dft_result
+GENERIC(depth : integer);
+PORT(
+	CLK : IN std_logic;
+	READ_ADDRESS : in integer range 0 to depth-1;
+	WRITE_ADDRESS : in integer range 0 to depth-1;
+	DATA_IN : IN std_logic_vector(191 downto 0);
+	WE : IN std_logic;          
+	DATA_OUT : OUT std_logic_vector(191 downto 0)
+	);
+END COMPONENT;
+COMPONENT result_bram
+  PORT (
+    clka : IN STD_LOGIC;
+    wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+    addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+    dina : IN STD_LOGIC_VECTOR(191 DOWNTO 0);
+    clkb : IN STD_LOGIC;
+    addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+    doutb : OUT STD_LOGIC_VECTOR(191 DOWNTO 0)
+  );
+END COMPONENT;
 COMPONENT SinCos
   PORT (
     clk : IN STD_LOGIC;
@@ -72,20 +94,34 @@ PORT(
 	);
 END COMPONENT;
 
-	type result is array(BINS-1 downto 0) of std_logic_vector(47 downto 0);
+	--type result is array(BINS-1 downto 0) of std_logic_vector(47 downto 0);
-	signal port1_real : result;
+	--signal port1_real : result;
-	signal port1_imag : result;
+	--signal port1_imag : result;
-	signal port2_real : result;
+	--signal port2_real : result;
-	signal port2_imag : result;
+	--signal port2_imag : result;
+	
+	--signal port1_real_read : std_logic_vector(47 downto 0);
+	--signal port1_imag_read : std_logic_vector(47 downto 0);
+	--signal port2_real_read : std_logic_vector(47 downto 0);
+	--signal port2_imag_read : std_logic_vector(47 downto 0);
+	
 	signal sample_cnt : integer range 0 to 65535;
 	signal bin_cnt : integer range 0 to BINS+2;
-	signal output_cnt : integer range 0 to BINS-1;
+	
-	type States is (WaitingForSample, WindowingStart, WaitMult, WaitMult2, PhaseReady, WindowingReady, WaitSinCos, Busy, Ready);
+	signal read_address : integer range 0 to BINS-1;
+	signal write_address : integer range 0 to BINS-1;
+	signal read_address_vector : std_logic_vector(5 downto 0);
+	signal write_address_vector : std_logic_vector(5 downto 0);
+	signal we : std_logic_vector(0 downto 0);
+	signal ram_in : std_logic_vector(191 downto 0);
+	signal ram_out : std_logic_vector(191 downto 0);
+	
+	type States is (WaitingForSample, WaitMult, WaitMult2, PhaseReady, WindowingReady, WaitSinCos, Busy, Ready);
 	signal state : States;
 	signal port1_latch : std_logic_vector(15 downto 0);
 	signal port2_latch : std_logic_vector(15 downto 0);
 	
-	signal window_index : std_logic_vector(6 downto 0);
+	signal window_index : std_logic_vector(15 downto 0);
 
 	signal window_value : std_logic_vector(15 downto 0);
 	
@@ -153,28 +189,50 @@ begin
 		VALUE => window_value
 	);
 	
+--	result_ram: dft_result
+--	GENERIC MAP(depth => BINS)
+--	PORT MAP(
+--		CLK => CLK,
+--		READ_ADDRESS => read_address,
+--		WRITE_ADDRESS => write_address,
+--		DATA_IN => ram_in,
+--		DATA_OUT => ram_out,
+--		WE => we
+--	);
+
+your_instance_name : result_bram
+  PORT MAP (
+    clka => CLK,
+    wea => we,
+    addra => write_address_vector,
+    dina => ram_in,
+    clkb => CLK,
+    addrb => read_address_vector,
+    doutb => ram_out
+  );
+	
+	read_address_vector <= std_logic_vector(to_unsigned(read_address, 6));
+	write_address_vector <= std_logic_vector(to_unsigned(write_address, 6));
+	OUTPUT <= ram_out;
+	
 	process(CLK, RESET)
 	begin
 		if rising_edge(CLK) then
 			if RESET = '1' then
 				window_index <= (others => '0');
 				sample_cnt <= 0;
-				RESULT_READY <= '1';
+				RESULT_READY <= '0';
+				read_address <= 0;
+				write_address <= 0;
+				we <= "0";
 				state <= WaitingForSample;
 			else
 				case state is
 					when WaitingForSample =>
-						RESULT_READY <= '1';
+						we <= "0";
-						OUTPUT <= port1_real(output_cnt) & port1_imag(output_cnt) & port2_real(output_cnt) & port2_imag(output_cnt);
-						if NEXT_OUTPUT = '1' then
-							if output_cnt < BINS - 1 then
-								output_cnt <= output_cnt + 1;
-							else
-								output_cnt <= 0;
-							end if;
-						end if;
 						if NEW_SAMPLE = '1' then
 							-- calculate phase for initial bin
+							-- TODO this should use unsigned multiplication
 							mult1_a <= std_logic_vector(to_unsigned(sample_cnt, 16));
 							mult1_b <= BIN1_PHASEINC;
 							mult2_a <= std_logic_vector(to_unsigned(sample_cnt, 16));
@@ -185,21 +243,26 @@ begin
 							mult4_a <= PORT2;
 							mult4_b <= window_value;
 							state <= WaitMult;
+							read_address <= 0;
 						end if;
 					when WaitMult =>
 						RESULT_READY <= '0';
+						we <= "0";
 						state <= WaitMult2;
 					when WaitMult2 =>
 						RESULT_READY <= '0';
+						we <= "0";
 						state <= PhaseReady;							
 					when PhaseReady =>
 						RESULT_READY <= '0';
+						we <= "0";
 						-- initial phase is ready
-						phase <= mult1_p;
+						phase <= mult1_p(15 downto 0) & "0000000000000000";
-						phase_inc <= mult2_p;
+						phase_inc <= mult2_p(23 downto 0) & "00000000";
 						state <= WindowingReady;
 					when WindowingReady =>
 						RESULT_READY <= '0';
+						we <= "0";
 						phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
 						port1_latch <= mult3_p(31 downto 16);
 						port2_latch <= mult4_p(31 downto 16);
@@ -208,6 +271,7 @@ begin
 					when WaitSinCos =>
 						phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
 						RESULT_READY <= '0';
+						we <= "0";
 						if bin_cnt < 4 then
 							bin_cnt <= bin_cnt + 1;
 						else
@@ -215,6 +279,7 @@ begin
 							state <= BUSY;
 						end if;
 					when BUSY =>
+						RESULT_READY <= '0';
 						phase <= std_logic_vector(unsigned(phase)+unsigned(phase_inc));
 						mult1_a <= port1_latch;
 						mult1_b <= sine;
@@ -226,30 +291,49 @@ begin
 						mult4_b <= cosine;
 						if bin_cnt >= 3 then
 							-- multiplier result is available, accumulate
-							if sample_cnt = 0 then
+							we <= "1";
-								port1_real(bin_cnt-3) <= mult1_p;
+							write_address <= bin_cnt - 3;
-								port1_imag(bin_cnt-3) <= mult2_p;
+							ram_in <= std_logic_vector(signed(ram_out(191 downto 144))+signed(mult1_p))
-								port2_real(bin_cnt-3) <= mult3_p;
+										& std_logic_vector(signed(ram_out(143 downto 96))+signed(mult2_p))
-								port2_imag(bin_cnt-3) <= mult4_p;
+										& std_logic_vector(signed(ram_out(95 downto 48))+signed(mult3_p))
-							else
+										& std_logic_vector(signed(ram_out(47 downto 0))+signed(mult4_p));
-								port1_real(bin_cnt-3) <= std_logic_vector(unsigned(port1_real(bin_cnt-3))+unsigned(mult1_p));
+						else
-								port1_imag(bin_cnt-3) <= std_logic_vector(unsigned(port1_imag(bin_cnt-3))+unsigned(mult2_p));
+							we <= "0";
-								port2_real(bin_cnt-3) <= std_logic_vector(unsigned(port2_real(bin_cnt-3))+unsigned(mult3_p));
-								--port2_imag(bin_cnt-3) <= std_logic_vector(unsigned(port2_imag(bin_cnt-3))+unsigned(mult4_p));
-							end if;
 						end if;
 						if bin_cnt >= BINS+2 then
-							state <= WaitingForSample;
+							read_address <= 0;
-							RESULT_READY <= '1';
+							if sample_cnt < unsigned(NSAMPLES) then
-							sample_cnt <= sample_cnt + 1;
+								sample_cnt <= sample_cnt + 1;
-							window_index <= std_logic_vector(unsigned(window_index)+unsigned(WINDOW_INC));
+								state <= WaitingForSample;
-							output_cnt <= 0;
+								window_index <= std_logic_vector(unsigned(window_index)+unsigned(WINDOW_INC));
+							else
+								state <= Ready;
+							end if;
 						else
-							RESULT_READY <= '0';
 							bin_cnt <= bin_cnt + 1;
+							if bin_cnt >= 1 then
+								read_address <= bin_cnt - 1;
+							end if;
+						end if;
+					when Ready =>
+						we <= "0";
+						RESULT_READY <= '1';
+						if NEXT_OUTPUT = '1' then
+							-- reset last entry to prepare for next DFT
+							write_address <= read_address;
+							ram_in <= (others => '0');
+							we <= "1";
+							-- fetch next entry from RAM
+							if read_address < BINS - 1 then
+								read_address <= read_address + 1;
+							else
+								RESULT_READY <= '0';
+								sample_cnt <= 0;
+								state <= WaitingForSample;
+								read_address <= 0;
+							end if;
 						end if;
 					when others =>
-						RESULT_READY <= '0';
 						state <= WaitingForSample;
 				end case;
 			end if;

FPGA/VNA/SPIConfig.vhd

@@ -37,7 +37,7 @@ entity SPICommands is
            MISO : out  STD_LOGIC;
            NSS : in  STD_LOGIC;
            NEW_SAMPLING_DATA : in  STD_LOGIC;
-           SAMPLING_RESULT : in  STD_LOGIC_VECTOR (287 downto 0);
+           SAMPLING_RESULT : in  STD_LOGIC_VECTOR (303 downto 0);
 			  ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
            SOURCE_UNLOCKED : in  STD_LOGIC;
            LO_UNLOCKED : in  STD_LOGIC;
@@ -69,6 +69,17 @@ entity SPICommands is
 			  RESET_MINMAX : out STD_LOGIC;
 			  SWEEP_HALTED : in STD_LOGIC;
 			  SWEEP_RESUME : out STD_LOGIC;
+			  
+			  -- DFT signals
+			  DFT_NSAMPLES : out STD_LOGIC_VECTOR (15 downto 0);
+			  DFT_BIN1_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
+           DFT_DIFFBIN_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
+			  DFT_WINDOW_INC : out STD_LOGIC_VECTOR (15 downto 0);
+			  DFT_RESULT_READY : in  STD_LOGIC;
+           DFT_OUTPUT : in  STD_LOGIC_VECTOR (191 downto 0);
+           DFT_NEXT_OUTPUT : out  STD_LOGIC;
+			  DFT_ENABLE : out STD_LOGIC;
+			  			  
 			  DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0));
 end SPICommands;
 
@@ -94,7 +105,11 @@ architecture Behavioral of SPICommands is
 	signal word_cnt : integer range 0 to 19;
 	type SPI_states is (Invalid, WriteSweepConfig, ReadResult, WriteRegister, ReadTest);
 	signal state : SPI_states;
-	signal selected_register : integer range 0 to 15;
+	signal selected_register : integer range 0 to 31;
+	
+	signal dft_next : std_logic;
+	
+	signal last_NSS : std_logic;
 	
 	signal sweep_config_write : std_logic;
 	signal unread_sampling_data : std_logic;
@@ -103,7 +118,7 @@ architecture Behavioral of SPICommands is
 	signal interrupt_mask : std_logic_vector(15 downto 0);
 	signal interrupt_status : std_logic_vector(15 downto 0);
 	
-	signal latched_result : std_logic_vector(271 downto 0);
+	signal latched_result : std_logic_vector(287 downto 0);
 	signal sweepconfig_buffer : std_logic_vector(79 downto 0);
 begin
 	SPI: spi_slave
@@ -119,11 +134,9 @@ begin
 		COMPLETE =>spi_complete 
 	);
 	
-	interrupt_status <= DEBUG_STATUS & SWEEP_HALTED & data_overrun & unread_sampling_data & SOURCE_UNLOCKED & LO_UNLOCKED;
-	INTERRUPT_ASSERTED <= '1' when (interrupt_status and interrupt_mask) /= "0000000000000000" else
-									'0';
-
 	SWEEP_WRITE(0) <= sweep_config_write;
+	DFT_NEXT_OUTPUT <= dft_next;
+	DFT_ENABLE <= interrupt_mask(5); 
 
 	process(CLK, RESET)
 	begin
@@ -143,6 +156,8 @@ begin
 				SOURCE_CE_EN <= '0';
 				LO_CE_EN <= '0';
 				PORTSWITCH_EN <= '0';
+				EXCITE_PORT1 <= '0';
+				EXCITE_PORT2 <= '0';
 				LEDS <= (others => '1');
 				WINDOW_SETTING <= "00";
 				unread_sampling_data <= '0';
@@ -150,21 +165,39 @@ begin
 				ADC_PRESCALER <= std_logic_vector(to_unsigned(112, 8));
 				ADC_PHASEINC <= std_logic_vector(to_unsigned(1120, 12));
 				RESET_MINMAX <= '0';
+				INTERRUPT_ASSERTED <= '0';
+				
+				DFT_NSAMPLES <= (others => '0');
+				DFT_BIN1_PHASEINC <= (others => '0');
+				DFT_DIFFBIN_PHASEINC <= (others => '0');
+				DFT_WINDOW_INC <= (others => '0');
+				dft_next <= '0';
+				last_NSS <= '1';
 			else
+				interrupt_status <= DEBUG_STATUS(10 downto 1) & DFT_RESULT_READY & SWEEP_HALTED & data_overrun & unread_sampling_data & SOURCE_UNLOCKED & LO_UNLOCKED;
+				if (interrupt_status and interrupt_mask) = "0000000000000000" then
+					INTERRUPT_ASSERTED <= '0';
+				else
+					INTERRUPT_ASSERTED <= '1';
+				end if;
 				if sweep_config_write = '1' then
 					sweep_config_write <= '0';
 				end if;
+				if dft_next = '1' then
+					dft_next <= '0';
+				end if;
+				RESET_MINMAX <= '0';
+				SWEEP_RESUME <= '0';
 				if NEW_SAMPLING_DATA = '1' then
 					unread_sampling_data <= '1';
 					if unread_sampling_data = '1' then
 						data_overrun <= '1';
 					end if;
 				end if;
-				if NSS = '1' then
+				last_NSS <= NSS;
+				if NSS = '0' and last_NSS = '1' then
 					word_cnt <= 0;
 					spi_buf_in <= interrupt_status;
-					RESET_MINMAX <= '0';
-					SWEEP_RESUME <= '0';
 				elsif spi_complete = '1' then
 					word_cnt <= word_cnt + 1;
 					if word_cnt = 0 then
@@ -180,9 +213,13 @@ begin
 							when "011" => state <= Invalid;
 											RESET_MINMAX <= '1';
 							when "100" => state <= WriteRegister;
-											selected_register <= to_integer(unsigned(spi_buf_out(3 downto 0)));
+											selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0)));
+							when "101" => state <= ReadResult;-- can use same state as read result, but the latched data will contain the DFT values
+											latched_result(175 downto 0) <= DFT_OUTPUT(191 downto 16);
+											spi_buf_in <= DFT_OUTPUT(15 downto 0);
+											dft_next <= '1';
 							when "110" => state <= ReadResult;
-											latched_result <= SAMPLING_RESULT(287 downto 16);
+											latched_result <= SAMPLING_RESULT(303 downto 16);
 											spi_buf_in <= SAMPLING_RESULT(15 downto 0);
 											unread_sampling_data <= '0';
 							when "111" => state <= ReadResult; -- can use same state as read result, but the latched data will contain the min/max ADC values
@@ -220,6 +257,10 @@ begin
 								when 13 => MAX2871_DEF_3(31 downto 16) <= spi_buf_out;
 								when 14 => MAX2871_DEF_4(15 downto 0) <= spi_buf_out;
 								when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
+								when 16 => DFT_NSAMPLES <= spi_buf_out;
+								when 17 => DFT_WINDOW_INC <= spi_buf_out;
+								when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
+								when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
 								when others => 
 							end case;
 							selected_register <= selected_register + 1;
@@ -235,7 +276,7 @@ begin
 						elsif state = ReadResult then
 							-- pass on next word of latched result
 							spi_buf_in <= latched_result(15 downto 0);
-							latched_result <= "0000000000000000" & latched_result(271 downto 16);
+							latched_result <= "0000000000000000" & latched_result(287 downto 16);
 						end if;
 					end if;
 				end if;

FPGA/VNA/Sampling.vhd

@@ -111,6 +111,8 @@ END COMPONENT;
 	signal multR_I : std_logic_vector(31 downto 0);
 	signal multR_Q : std_logic_vector(31 downto 0);
 	
+	signal last_sample : std_logic;
+	
 	type States is (Idle, Sampling, WaitForMult, Accumulating, Ready);
 	signal state : States;
 begin
@@ -207,8 +209,13 @@ begin
 			else
 				-- when not idle, generate pulses for ADCs
 				if state /= Idle then
-					if clk_cnt = unsigned(ADC_PRESCALER) - 1 then
+					if clk_cnt = unsigned(ADC_PRESCALER) - 1 and last_sample = '0' then
 						ADC_START <= '1';
+						if sample_cnt < samples_to_take then
+							sample_cnt <= sample_cnt + 1;
+						else
+							last_sample <= '1';
+						end if;
 						clk_cnt <= 0;
 					else
 						clk_cnt <= clk_cnt + 1;
@@ -220,6 +227,7 @@ begin
 				-- handle state transitions
 				case state is
 					when Idle =>
+						last_sample <= '0';
 						sample_cnt <= 0;
 						DONE <= '0';
 						PRE_DONE <= '0';
@@ -281,8 +289,7 @@ begin
 						DONE <= '0';
 						PRE_DONE <= '0';
 						phase <= std_logic_vector(unsigned(phase) + unsigned(PHASEINC));
-						if sample_cnt < samples_to_take then
+						if last_sample = '0' then
-							sample_cnt <= sample_cnt + 1;
 							state <= Sampling;
 						else
 							state <= Ready;

FPGA/VNA/Sweep.vhd

@@ -71,7 +71,8 @@ entity Sweep is
 			  EXCITE_PORT2 : in STD_LOGIC;
 			  
 			  -- Debug signals
-			  DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0)
+			  DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0);
+			  RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0)
 			  );
 end Sweep;
 
@@ -144,6 +145,7 @@ begin
 				START_SAMPLING <= '0';
 				RELOAD_PLL_REGS <= '0';
 				SWEEP_HALTED <= '0';
+				RESULT_INDEX <= (others => '1');
 			else
 				case state is
 					when TriggerSetup =>
@@ -184,6 +186,7 @@ begin
 						-- wait for sampling to finish
 						START_SAMPLING <= '0';
 						if SAMPLING_BUSY = '0' then
+							RESULT_INDEX <= "000" & std_logic_vector(point_cnt);
 							if EXCITE_PORT2 = '1' then
 								state <= SettlingPort2;
 							else
@@ -205,6 +208,7 @@ begin
 					when ExcitingPort2 =>
 						-- wait for sampling to finish
 						START_SAMPLING <= '0';
+						RESULT_INDEX <= "100" & std_logic_vector(point_cnt);
 						if SAMPLING_BUSY = '0' then
 							state <= NextPoint;
 						end if;

FPGA/VNA/Test_DFT.vhd

@@ -47,6 +47,7 @@ ARCHITECTURE behavior OF Test_DFT IS
          PORT1 : IN  std_logic_vector(15 downto 0);
          PORT2 : IN  std_logic_vector(15 downto 0);
          NEW_SAMPLE : IN  std_logic;
+			NSAMPLES : in STD_LOGIC_VECTOR (15 downto 0);
          BIN1_PHASEINC : IN  std_logic_vector(15 downto 0);
          DIFFBIN_PHASEINC : IN  std_logic_vector(15 downto 0);
          WINDOW_INC : IN  std_logic_vector(15 downto 0);
@@ -69,6 +70,7 @@ ARCHITECTURE behavior OF Test_DFT IS
    signal WINDOW_INC : std_logic_vector(15 downto 0) := (others => '0');
    signal WINDOW_TYPE : std_logic_vector(1 downto 0) := (others => '0');
    signal NEXT_OUTPUT : std_logic := '0';
+	signal NSAMPLES : STD_LOGIC_VECTOR (15 downto 0);
 
  	--Outputs
    signal RESULT_READY : std_logic;
@@ -81,13 +83,14 @@ BEGIN
  
 	-- Instantiate the Unit Under Test (UUT)
    uut: DFT
-	GENERIC MAP(BINS => 100)
+	GENERIC MAP(BINS => 64)
 	PORT MAP (
           CLK => CLK,
           RESET => RESET,
           PORT1 => PORT1,
           PORT2 => PORT2,
           NEW_SAMPLE => NEW_SAMPLE,
+			 NSAMPLES => NSAMPLES,
           BIN1_PHASEINC => BIN1_PHASEINC,
           DIFFBIN_PHASEINC => DIFFBIN_PHASEINC,
           WINDOW_INC => WINDOW_INC,
@@ -117,18 +120,19 @@ BEGIN
 		BIN1_PHASEINC <= "0100000000000000";
 		DIFFBIN_PHASEINC <= "0010000000000000";
 		WINDOW_INC <= "0000100000000000";
+		NSAMPLES <= "0000000000000011";
       wait for 100 ns;	
 		RESET <= '0';
       wait for CLK_period*10;
 		NEW_SAMPLE <= '1';
 		wait for CLK_period;
 		NEW_SAMPLE <= '0';
-		--wait until RESULT_READY = '1';
+		while True loop
-		wait for CLK_period*112;
+			wait for CLK_period * 111;
-		NEW_SAMPLE <= '1';
+			NEW_SAMPLE <= '1';
-		wait for CLK_period;
+			wait for CLK_period;
-		NEW_SAMPLE <= '0';
+			NEW_SAMPLE <= '0';
-      -- insert stimulus here 
+		end loop;
 
       wait;
    end process;

FPGA/VNA/Test_SPI.vhd

@@ -219,6 +219,9 @@ BEGIN
       wait for CLK_period*10;
 		CS <= '0';
 		SPI("0101010101010101");
+		BUF_IN <= "1010101010101010";
+		wait for SPI_CLK_period/2;
+		SPI("1100110011001100");
 		CS <= '1';
 		
       wait;

FPGA/VNA/Test_Sampling.vhd

@@ -40,29 +40,30 @@ ARCHITECTURE behavior OF Test_Sampling IS
     -- Component Declaration for the Unit Under Test (UUT)
  
     COMPONENT Sampling
-	 Generic(CLK_DIV : integer;
+	 Generic(CLK_CYCLES_PRE_DONE : integer);
-			CLK_FREQ : integer;
+	PORT(
-			IF_FREQ : integer;
+		CLK : IN std_logic;
-			CLK_CYCLES_PRE_DONE : integer);
+		RESET : IN std_logic;
-    PORT(
+		ADC_PRESCALER : IN std_logic_vector(7 downto 0);
-         CLK : IN  std_logic;
+		PHASEINC : IN std_logic_vector(11 downto 0);
-         RESET : IN  std_logic;
+		PORT1 : IN std_logic_vector(15 downto 0);
-         PORT1 : IN  std_logic_vector(15 downto 0);
+		PORT2 : IN std_logic_vector(15 downto 0);
-         PORT2 : IN  std_logic_vector(15 downto 0);
+		REF : IN std_logic_vector(15 downto 0);
-         REF : IN  std_logic_vector(15 downto 0);
+		NEW_SAMPLE : IN std_logic;
-         ADC_START : OUT  std_logic;
+		START : IN std_logic;
-         NEW_SAMPLE : IN  std_logic;
+		SAMPLES : IN std_logic_vector(12 downto 0);
-         DONE : OUT  std_logic;
+		WINDOW_TYPE : IN std_logic_vector(1 downto 0);          
-         PRE_DONE : OUT  std_logic;
+		ADC_START : OUT std_logic;
-         START : IN  std_logic;
+		DONE : OUT std_logic;
-         SAMPLES : IN  std_logic_vector(16 downto 0);
+		PRE_DONE : OUT std_logic;
-         PORT1_I : OUT  std_logic_vector(47 downto 0);
+		PORT1_I : OUT std_logic_vector(47 downto 0);
-         PORT1_Q : OUT  std_logic_vector(47 downto 0);
+		PORT1_Q : OUT std_logic_vector(47 downto 0);
-         PORT2_I : OUT  std_logic_vector(47 downto 0);
+		PORT2_I : OUT std_logic_vector(47 downto 0);
-         PORT2_Q : OUT  std_logic_vector(47 downto 0);
+		PORT2_Q : OUT std_logic_vector(47 downto 0);
-         REF_I : OUT  std_logic_vector(47 downto 0);
+		REF_I : OUT std_logic_vector(47 downto 0);
-         REF_Q : OUT  std_logic_vector(47 downto 0)
+		REF_Q : OUT std_logic_vector(47 downto 0);
-        );
+		ACTIVE : OUT std_logic
+		);
     END COMPONENT;
     
 
@@ -74,8 +75,9 @@ ARCHITECTURE behavior OF Test_Sampling IS
    signal REF : std_logic_vector(15 downto 0) := (others => '0');
    signal NEW_SAMPLE : std_logic := '0';
    signal START : std_logic := '0';
-   signal SAMPLES : std_logic_vector(16 downto 0) := (others => '0');
+   signal SAMPLES : std_logic_vector(12 downto 0) := (others => '0');
-
+	signal ADC_PRESCALER : std_logic_vector(7 downto 0);
+	signal PHASEINC : std_logic_vector(11 downto 0);
  	--Outputs
    signal ADC_START : std_logic;
    signal DONE : std_logic;
@@ -94,28 +96,29 @@ BEGIN
  
 	-- Instantiate the Unit Under Test (UUT)
    uut: Sampling
-	Generic MAP(CLK_DIV => 165,
+	Generic MAP(CLK_CYCLES_PRE_DONE => 0)
-				CLK_FREQ => 160000000,
-				IF_FREQ => 250000,
-				CLK_CYCLES_PRE_DONE => 0)
 	PORT MAP (
-          CLK => CLK,
+			CLK => CLK,
-          RESET => RESET,
+			RESET => RESET,
-          PORT1 => PORT1,
+			ADC_PRESCALER => ADC_PRESCALER,
-          PORT2 => PORT2,
+			PHASEINC => PHASEINC,
-          REF => REF,
+			PORT1 => PORT1,
-          ADC_START => ADC_START,
+			PORT2 => PORT2,
-          NEW_SAMPLE => NEW_SAMPLE,
+			REF => REF,
-          DONE => DONE,
+			NEW_SAMPLE => NEW_SAMPLE,
-          PRE_DONE => PRE_DONE,
+			START => START,
-          START => START,
+			SAMPLES => SAMPLES,
-          SAMPLES => SAMPLES,
+			WINDOW_TYPE => "00",        
-          PORT1_I => PORT1_I,
+			ADC_START => ADC_START,
-          PORT1_Q => PORT1_Q,
+			DONE => DONE,
-          PORT2_I => PORT2_I,
+			PRE_DONE => PRE_DONE,
-          PORT2_Q => PORT2_Q,
+			PORT1_I => PORT1_I,
-          REF_I => REF_I,
+			PORT1_Q => PORT1_Q,
-          REF_Q => REF_Q
+			PORT2_I => PORT2_I,
+			PORT2_Q => PORT2_Q,
+			REF_I => REF_I,
+			REF_Q => REF_I,
+			ACTIVE => open
         );
 
    -- Clock process definitions
@@ -138,15 +141,17 @@ BEGIN
       wait for CLK_period*10;
 
       -- insert stimulus here
+		ADC_PRESCALER <= "01110000";
+		PHASEINC <= "010001100000";
 		PORT1 <= "0111111111111111";
 		PORT2 <= "0111111111111111";
 		REF <= "0111111111111111";
-		SAMPLES <= "00000000000001000";
+		SAMPLES <= "0000000000001";
 		START <= '1';
 		while True loop
 			wait until ADC_START = '1';
 			START <= '0';
-			wait for CLK_period * 150;
+			wait for CLK_period * 110;
 			NEW_SAMPLE <= '1';
 			wait for CLK_period;
 			NEW_SAMPLE <= '0';

FPGA/VNA/VNA.gise

@@ -22,6 +22,7 @@
   <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="VNA.xise"/>
 
   <files xmlns="http://www.xilinx.com/XMLSchema">
+    <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="DFT.vhi"/>
     <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MAX2871.vhi"/>
     <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MCP33131.vhi"/>
     <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="ResetDelay.vhi"/>
@@ -45,9 +46,7 @@
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_SPI_beh.prj"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
-    <file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_SPI_isim_beh.wdb"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
@@ -63,6 +62,7 @@
     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+    <file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="dft_result.vhi"/>
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
     <file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
     <file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
@@ -99,6 +99,7 @@
     <file xil_pn:fileType="FILE_XPI" xil_pn:name="top.xpi"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="top.xst"/>
     <file xil_pn:fileType="FILE_HTML" xil_pn:name="top_envsettings.html"/>
+    <file xil_pn:fileType="FILE_LOG" xil_pn:name="top_fpga_editor.log"/>
     <file xil_pn:fileType="FILE_NCD" xil_pn:name="top_guide.ncd" xil_pn:origination="imported"/>
     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="top_isim_beh.exe"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.map" xil_pn:subbranch="Map"/>
@@ -128,7 +129,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1601146490" xil_pn:in_ck="-760725241865927573" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1601146490">
+    <transform xil_pn:end_ts="1604520805" xil_pn:in_ck="2193033869104949559" xil_pn:name="TRAN_copyAbstractToPostAbstractSimulation" xil_pn:start_ts="1604520805">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -153,19 +154,20 @@
       <outfile xil_pn:name="Test_SinCos.vhd"/>
       <outfile xil_pn:name="Test_Sync.vhd"/>
       <outfile xil_pn:name="Test_Window.vhd"/>
+      <outfile xil_pn:name="dft_result.vhd"/>
       <outfile xil_pn:name="spi_slave.vhd"/>
       <outfile xil_pn:name="top.vhd"/>
       <outfile xil_pn:name="window.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1601125757" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-2603858341434889151" xil_pn:start_ts="1601125757">
+    <transform xil_pn:end_ts="1604520805" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="-5354180755060525133" xil_pn:start_ts="1604520805">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1601125757" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4552913978128179903" xil_pn:start_ts="1601125757">
+    <transform xil_pn:end_ts="1604520805" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="4601062479098204721" xil_pn:start_ts="1604520805">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1601125758" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1601125757">
+    <transform xil_pn:end_ts="1604498987" xil_pn:in_ck="-1881940375859338364" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604498987">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
@@ -175,8 +177,10 @@
       <outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
       <outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
+      <outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
+      <outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1601146490" xil_pn:in_ck="-7092619378539932792" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1601146490">
+    <transform xil_pn:end_ts="1604520805" xil_pn:in_ck="3333396920699583347" xil_pn:name="TRAN_copyPostAbstractToPreSimulation" xil_pn:start_ts="1604520805">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -202,15 +206,17 @@
       <outfile xil_pn:name="Test_SinCos.vhd"/>
       <outfile xil_pn:name="Test_Sync.vhd"/>
       <outfile xil_pn:name="Test_Window.vhd"/>
+      <outfile xil_pn:name="dft_result.vhd"/>
       <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SinCos.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
+      <outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
       <outfile xil_pn:name="spi_slave.vhd"/>
       <outfile xil_pn:name="top.vhd"/>
       <outfile xil_pn:name="window.vhd"/>
     </transform>
-    <transform xil_pn:end_ts="1601146493" xil_pn:in_ck="-7092619378539932792" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-75338102225213726" xil_pn:start_ts="1601146490">
+    <transform xil_pn:end_ts="1604520811" xil_pn:in_ck="3333396920699583347" xil_pn:name="TRAN_ISimulateBehavioralModelRunFuse" xil_pn:prop_ck="-5642200015192194106" xil_pn:start_ts="1604520805">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
@@ -218,20 +224,20 @@
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_SPI_beh.prj"/>
+      <outfile xil_pn:name="Test_DFT_beh.prj"/>
-      <outfile xil_pn:name="Test_SPI_isim_beh.exe"/>
+      <outfile xil_pn:name="Test_DFT_isim_beh.exe"/>
       <outfile xil_pn:name="fuse.log"/>
       <outfile xil_pn:name="isim"/>
       <outfile xil_pn:name="isim.log"/>
       <outfile xil_pn:name="xilinxsim.ini"/>
     </transform>
-    <transform xil_pn:end_ts="1601146493" xil_pn:in_ck="-3358899429776077154" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-1346610876870411377" xil_pn:start_ts="1601146493">
+    <transform xil_pn:end_ts="1604520811" xil_pn:in_ck="-3358899429776077154" xil_pn:name="TRAN_ISimulateBehavioralModel" xil_pn:prop_ck="-8724408846642916045" xil_pn:start_ts="1604520811">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
-      <outfile xil_pn:name="Test_SPI_isim_beh.wdb"/>
+      <outfile xil_pn:name="Test_DFT_isim_beh.wdb"/>
       <outfile xil_pn:name="isim.cmd"/>
       <outfile xil_pn:name="isim.log"/>
     </transform>
@@ -243,7 +249,7 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1601116205" xil_pn:in_ck="-6165752171532536899" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1601116205">
+    <transform xil_pn:end_ts="1604440718" xil_pn:in_ck="-1881940375859338364" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604440718">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
@@ -253,6 +259,8 @@
       <outfile xil_pn:name="ipcore_dir/SinCosMult.vhd"/>
       <outfile xil_pn:name="ipcore_dir/SweepConfigMem.ngc"/>
       <outfile xil_pn:name="ipcore_dir/SweepConfigMem.vhd"/>
+      <outfile xil_pn:name="ipcore_dir/result_bram.ngc"/>
+      <outfile xil_pn:name="ipcore_dir/result_bram.vhd"/>
     </transform>
     <transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600270761">
       <status xil_pn:value="SuccessfullyRun"/>
@@ -270,9 +278,8 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1601308559" xil_pn:in_ck="-4506597320363840754" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1601308538">
+    <transform xil_pn:end_ts="1604523374" xil_pn:in_ck="-7635529597152014087" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1604523352">
       <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
       <status xil_pn:value="OutputChanged"/>
@@ -288,11 +295,11 @@
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1601131743" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1601131743">
+    <transform xil_pn:end_ts="1604436130" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1604436130">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1601308565" xil_pn:in_ck="490340488621696080" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1601308559">
+    <transform xil_pn:end_ts="1604523381" xil_pn:in_ck="-3571942932097917307" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1604523374">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_ngo"/>
@@ -301,12 +308,10 @@
       <outfile xil_pn:name="top.ngd"/>
       <outfile xil_pn:name="top_ngdbuild.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1601308605" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1448924893915930207" xil_pn:start_ts="1601308565">
+    <transform xil_pn:end_ts="1604523453" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-7036854207931970956" xil_pn:start_ts="1604523381">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
       <outfile xil_pn:name="top.pcf"/>
       <outfile xil_pn:name="top_map.map"/>
@@ -317,7 +322,7 @@
       <outfile xil_pn:name="top_summary.xml"/>
       <outfile xil_pn:name="top_usage.xml"/>
     </transform>
-    <transform xil_pn:end_ts="1601308633" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1601308605">
+    <transform xil_pn:end_ts="1604523487" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1604523453">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
@@ -331,7 +336,7 @@
       <outfile xil_pn:name="top_pad.txt"/>
       <outfile xil_pn:name="top_par.xrpt"/>
     </transform>
-    <transform xil_pn:end_ts="1601308646" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1601308633">
+    <transform xil_pn:end_ts="1604523501" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1604523487">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
@@ -377,7 +382,15 @@
       <status xil_pn:value="OutputChanged"/>
       <status xil_pn:value="OutputRemoved"/>
     </transform>
-    <transform xil_pn:end_ts="1601308633" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1601308626">
+    <transform xil_pn:end_ts="1604431776" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1604431776">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputAdded"/>
+      <status xil_pn:value="InputChanged"/>
+      <status xil_pn:value="InputRemoved"/>
+    </transform>
+    <transform xil_pn:end_ts="1604523487" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1604523479">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

FPGA/VNA/VNA.xise

@@ -17,14 +17,14 @@
   <files>
     <file xil_pn:name="top.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="top.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="MCP33131.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="Test_MCP33131.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -34,22 +34,22 @@
     </file>
     <file xil_pn:name="MAX2871.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="ipcore_dir/SweepConfigMem.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="Sampling.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="ipcore_dir/SinCos.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="ipcore_dir/SinCosMult.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="Test_Sampling.vhd" xil_pn:type="FILE_VHDL">
@@ -59,20 +59,20 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
     </file>
     <file xil_pn:name="spi_slave.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="SPIConfig.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="Sweep.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="ipcore_dir/PLL.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="Test_MAX2871.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -100,24 +100,24 @@
     </file>
     <file xil_pn:name="ResetDelay.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="Test_SinCos.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="Test_SPI.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="133"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="133"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="133"/>
     </file>
     <file xil_pn:name="Synchronizer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="window.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="Test_Window.vhd" xil_pn:type="FILE_VHDL">
@@ -127,15 +127,23 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="139"/>
     </file>
     <file xil_pn:name="DFT.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="Test_DFT.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="144"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="144"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="144"/>
     </file>
+    <file xil_pn:name="dft_result.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="ipcore_dir/result_bram.xco" xil_pn:type="FILE_COREGEN">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+    </file>
     <file xil_pn:name="ipcore_dir/SweepConfigMem.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
@@ -148,6 +156,9 @@
     <file xil_pn:name="ipcore_dir/PLL.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="ipcore_dir/result_bram.xise" xil_pn:type="FILE_COREGENISE">
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
   </files>
 
   <properties>
@@ -213,7 +224,7 @@
     <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -246,7 +257,7 @@
     <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -392,8 +403,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_SPI" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_DFT" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_SPI" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -411,7 +422,7 @@
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_SPI" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.Test_DFT" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -463,7 +474,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_SPI|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|Test_DFT|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="VNA" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

FPGA/VNA/dft_result.vhd

@@ -0,0 +1,56 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    22:01:17 11/03/2020 
+-- Design Name: 
+-- Module Name:    dft_result - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity dft_result is
+	 Generic (depth : integer);
+    Port ( CLK : in  STD_LOGIC;
+           READ_ADDRESS : in integer range 0 to depth-1;
+           WRITE_ADDRESS : in integer range 0 to depth-1;
+           DATA_IN : in  STD_LOGIC_VECTOR (191 downto 0);
+           DATA_OUT : out  STD_LOGIC_VECTOR (191 downto 0);
+           WE : in  STD_LOGIC);
+end dft_result;
+
+architecture rtl of dft_result is
+	type memory is array(depth-1 downto 0) of std_logic_vector(191 downto 0);
+	signal ram : memory;
+begin
+	process(CLK)
+	begin
+		if rising_edge(CLK) then
+			DATA_OUT <= ram(READ_ADDRESS);
+			if(WE = '1') then
+				ram(WRITE_ADDRESS) <= DATA_IN;
+			end if;
+		end if;
+	end process;
+end rtl;
+

FPGA/VNA/ipcore_dir/result_bram.xco

@@ -0,0 +1,108 @@
+##############################################################
+#
+# Xilinx Core Generator version 14.6
+# Date: Tue Nov  3 21:55:11 2020
+#
+##############################################################
+#
+#  This file contains the customisation parameters for a
+#  Xilinx CORE Generator IP GUI. It is strongly recommended
+#  that you do not manually alter this file as it may cause
+#  unexpected and unsupported behavior.
+#
+##############################################################
+#
+#  Generated from component: xilinx.com:ip:blk_mem_gen:7.3
+#
+##############################################################
+#
+# BEGIN Project Options
+SET addpads = false
+SET asysymbol = true
+SET busformat = BusFormatAngleBracketNotRipped
+SET createndf = false
+SET designentry = VHDL
+SET device = xc6slx9
+SET devicefamily = spartan6
+SET flowvendor = Other
+SET formalverification = false
+SET foundationsym = false
+SET implementationfiletype = Ngc
+SET package = tqg144
+SET removerpms = false
+SET simulationfiles = Behavioral
+SET speedgrade = -2
+SET verilogsim = false
+SET vhdlsim = true
+# END Project Options
+# BEGIN Select
+SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:7.3
+# END Select
+# BEGIN Parameters
+CSET additional_inputs_for_power_estimation=false
+CSET algorithm=Minimum_Area
+CSET assume_synchronous_clk=false
+CSET axi_id_width=4
+CSET axi_slave_type=Memory_Slave
+CSET axi_type=AXI4_Full
+CSET byte_size=9
+CSET coe_file=no_coe_file_loaded
+CSET collision_warnings=ALL
+CSET component_name=result_bram
+CSET disable_collision_warnings=false
+CSET disable_out_of_range_warnings=false
+CSET ecc=false
+CSET ecctype=No_ECC
+CSET enable_32bit_address=false
+CSET enable_a=Always_Enabled
+CSET enable_b=Always_Enabled
+CSET error_injection_type=Single_Bit_Error_Injection
+CSET fill_remaining_memory_locations=false
+CSET interface_type=Native
+CSET load_init_file=false
+CSET mem_file=no_Mem_file_loaded
+CSET memory_type=Simple_Dual_Port_RAM
+CSET operating_mode_a=WRITE_FIRST
+CSET operating_mode_b=WRITE_FIRST
+CSET output_reset_value_a=0
+CSET output_reset_value_b=0
+CSET pipeline_stages=0
+CSET port_a_clock=100
+CSET port_a_enable_rate=100
+CSET port_a_write_rate=50
+CSET port_b_clock=100
+CSET port_b_enable_rate=100
+CSET port_b_write_rate=0
+CSET primitive=8kx2
+CSET read_width_a=192
+CSET read_width_b=192
+CSET register_porta_input_of_softecc=false
+CSET register_porta_output_of_memory_core=false
+CSET register_porta_output_of_memory_primitives=false
+CSET register_portb_output_of_memory_core=false
+CSET register_portb_output_of_memory_primitives=false
+CSET register_portb_output_of_softecc=false
+CSET remaining_memory_locations=0
+CSET reset_memory_latch_a=false
+CSET reset_memory_latch_b=false
+CSET reset_priority_a=CE
+CSET reset_priority_b=CE
+CSET reset_type=SYNC
+CSET softecc=false
+CSET use_axi_id=false
+CSET use_bram_block=Stand_Alone
+CSET use_byte_write_enable=false
+CSET use_error_injection_pins=false
+CSET use_regcea_pin=false
+CSET use_regceb_pin=false
+CSET use_rsta_pin=false
+CSET use_rstb_pin=false
+CSET write_depth_a=64
+CSET write_width_a=192
+CSET write_width_b=192
+# END Parameters
+# BEGIN Extra information
+MISC pkg_timestamp=2012-11-19T16:22:25Z
+# END Extra information
+GENERATE
+# CRC: 64af2239

FPGA/VNA/ipcore_dir/result_bram.xise

@@ -0,0 +1,73 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="14.6" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="result_bram.ngc" xil_pn:type="FILE_NGC">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="result_bram.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx9" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|result_bram|result_bram_a" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="result_bram.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/result_bram" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="result_bram" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2020-11-03T22:56:00" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="954C7EB37A9CAA0D6F0F8CE18AB6F28F" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries/>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>

FPGA/VNA/spi_slave.vhd

@@ -46,7 +46,7 @@ entity spi_slave is
 end spi_slave;
 
 architecture Behavioral of spi_slave is
-	--signal miso_buffer : STD_LOGIC_VECTOR (W-1 downto 0);
+	signal miso_buffer : STD_LOGIC_VECTOR (W-1 downto 0);
 	signal mosi_buffer : STD_LOGIC_VECTOR (W-2 downto 0);
 
 	signal data_valid : STD_LOGIC_VECTOR(2 downto 0);
@@ -60,22 +60,21 @@ begin
 	begin
 		if rising_edge(CLK) then
 			data_valid(2 downto 1) <= data_valid(1 downto 0);
-			if data_valid(2) = '1' then
+			COMPLETE <= '0';
+			if data_valid(1) = '1' then
 				if data_synced(0) = '0' then
 					BUF_OUT <= data;
 					COMPLETE <= '1';
 					data_synced(0) <= '1';
-				else
-					COMPLETE <= '0';
 				end if;
 			else
-				COMPLETE <= '0';
 				data_synced(0) <= '0';
 			end if;
 		end if;
 	end process;
 
-	MISO <= BUF_IN(W - 1 - bit_cnt);-- when bit_cnt = 0 else miso_buffer(W-2);
+	--MISO <= BUF_IN(W - 1 - bit_cnt);-- when bit_cnt = 0 else miso_buffer(W-2);
+	MISO <= BUF_IN(15) when bit_cnt = 0 else miso_buffer(W-2);
 
 	slave_in: process(SPI_CLK)
 	begin
@@ -99,14 +98,13 @@ begin
 	begin
 		if CS = '1' then
 			bit_cnt <= 0;
-			--miso_buffer <= BUF_IN;
 		elsif falling_edge(SPI_CLK) then
 			if bit_cnt < W-1 then
 				bit_cnt <= bit_cnt + 1;
 				if bit_cnt = 0 then
-					--miso_buffer <= BUF_IN;
+					miso_buffer <= BUF_IN;
 				else
-					--miso_buffer <= miso_buffer(W-2 downto 0) & '0';
+					miso_buffer <= miso_buffer(W-2 downto 0) & '0';
 				end if;
 			else
 				bit_cnt <= 0;

FPGA/VNA/top.ucf

@@ -1,6 +1,6 @@
 CONFIG VCCAUX  = 3.3;
-NET "CLK" PERIOD = 62.5 ns;
+NET "CLK" PERIOD = 62.5 ns HIGH 50%;
-NET "MCU_SCK" PERIOD = 31.25ns;
+NET "MCU_SCK" PERIOD = 25ns HIGH 50%;
 
 NET "ATTENUATION[6]" IOSTANDARD = LVCMOS33;
 NET "ATTENUATION[5]" IOSTANDARD = LVCMOS33;

FPGA/VNA/top.vhd

@@ -141,6 +141,7 @@ architecture Behavioral of top is
 		SOURCE_FILTER : OUT std_logic_vector(1 downto 0);
 		EXCITE_PORT1 : in STD_LOGIC;
 		EXCITE_PORT2 : in STD_LOGIC;
+		RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0);
 		DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0)
 		);
 	END COMPONENT;
@@ -211,7 +212,7 @@ architecture Behavioral of top is
 		MOSI : IN std_logic;
 		NSS : IN std_logic;
 		NEW_SAMPLING_DATA : IN std_logic;
-		SAMPLING_RESULT : IN std_logic_vector(287 downto 0);
+		SAMPLING_RESULT : IN std_logic_vector(303 downto 0);
 		ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
 		SOURCE_UNLOCKED : IN std_logic;
 		LO_UNLOCKED : IN std_logic;          
@@ -244,10 +245,37 @@ architecture Behavioral of top is
 		RESET_MINMAX : out STD_LOGIC;
 		SWEEP_HALTED : in STD_LOGIC;
 		SWEEP_RESUME : out STD_LOGIC;
+		DFT_NSAMPLES : out STD_LOGIC_VECTOR (15 downto 0);
+		DFT_BIN1_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
+		DFT_DIFFBIN_PHASEINC : out  STD_LOGIC_VECTOR (15 downto 0);
+		DFT_WINDOW_INC : out STD_LOGIC_VECTOR (15 downto 0);
+		DFT_RESULT_READY : in  STD_LOGIC;
+		DFT_OUTPUT : in  STD_LOGIC_VECTOR (191 downto 0);
+		DFT_NEXT_OUTPUT : out  STD_LOGIC;
+		DFT_ENABLE : out STD_LOGIC;
 		DEBUG_STATUS : in STD_LOGIC_VECTOR (10 downto 0)
 		);
 	END COMPONENT;
 	
+	COMPONENT DFT
+	Generic (BINS : integer);
+	PORT(
+		CLK : IN std_logic;
+		RESET : IN std_logic;
+		PORT1 : IN std_logic_vector(15 downto 0);
+		PORT2 : IN std_logic_vector(15 downto 0);
+		NEW_SAMPLE : IN std_logic;
+		NSAMPLES : IN std_logic_vector(15 downto 0);
+		BIN1_PHASEINC : IN std_logic_vector(15 downto 0);
+		DIFFBIN_PHASEINC : IN std_logic_vector(15 downto 0);
+		WINDOW_INC : IN std_logic_vector(15 downto 0);
+		WINDOW_TYPE : IN std_logic_vector(1 downto 0);
+		NEXT_OUTPUT : IN std_logic;          
+		RESULT_READY : OUT std_logic;
+		OUTPUT : OUT std_logic_vector(191 downto 0)
+		);
+	END COMPONENT;
+	
 	COMPONENT SweepConfigMem
 	PORT (
 		clka : IN STD_LOGIC;
@@ -307,7 +335,7 @@ architecture Behavioral of top is
 	signal sampling_start : std_logic;
 	signal sampling_samples : std_logic_vector(12 downto 0);
 	signal sampling_user_samples : std_logic_vector(12 downto 0);
-	signal sampling_result : std_logic_vector(287 downto 0);
+	signal sampling_result : std_logic_vector(303 downto 0);
 	signal sampling_window : std_logic_vector(1 downto 0);
 	signal sampling_prescaler : std_logic_vector(7 downto 0);
 	signal sampling_phaseinc : std_logic_vector(11 downto 0);
@@ -360,9 +388,21 @@ architecture Behavioral of top is
 	signal aux3_sync : std_logic;
 	signal lo_ld_sync : std_logic;
 	signal source_ld_sync : std_logic;
+	signal nss_sync : std_logic;
 	
 	signal debug : std_logic_vector(10 downto 0);
 	signal intr : std_logic;
+	
+	-- DFT signals
+	signal dft_nsamples : std_logic_vector (15 downto 0);
+	signal dft_bin1_phaseinc : std_logic_vector (15 downto 0);
+	signal dft_diffbin_phaseinc : std_logic_vector (15 downto 0);
+	signal dft_window_inc : std_logic_vector (15 downto 0);
+	signal dft_ready : std_logic;
+	signal dft_output : std_logic_vector (191 downto 0);
+	signal dft_next_output : std_logic;
+	signal dft_enable : std_logic;
+	signal dft_reset : std_logic;
 begin
 
 	-- Reference CLK LED
@@ -448,6 +488,13 @@ begin
 		SYNC_IN => SOURCE_LD,
 		SYNC_OUT => source_ld_sync
 	);	
+	Sync_NSS : Synchronizer
+	GENERIC MAP(stages => 2)
+	PORT MAP(
+		CLK => clk160,
+		SYNC_IN => MCU_NSS,
+		SYNC_OUT => nss_sync
+	);	
 	
 
 	Source: MAX2871
@@ -594,7 +641,8 @@ begin
 		SOURCE_FILTER => source_filter,
 		EXCITE_PORT1 => sweep_excite_port1,
 		EXCITE_PORT2 => sweep_excite_port2,
-		DEBUG_STATUS => debug
+		DEBUG_STATUS => debug,
+		RESULT_INDEX => sampling_result(303 downto 288)
 	);
 	
 	-- Source filter mapping
@@ -605,7 +653,7 @@ begin
 	
 	-- PLL/SPI mux
 	-- only select FPGA SPI slave when both AUX1 and AUX2 are low
-	fpga_select <= MCU_NSS when aux1_sync = '0' and aux2_sync = '0' else '1';
+	fpga_select <= nss_sync when aux1_sync = '0' and aux2_sync = '0' else '1';
 	-- direct connection between MCU and SOURCE when AUX1 is high
 	SOURCE_CLK <= MCU_SCK when aux1_sync = '1' else fpga_source_SCK;
 	SOURCE_MOSI <= MCU_MOSI when aux1_sync = '1' else fpga_source_MOSI;
@@ -663,9 +711,36 @@ begin
 		SWEEP_RESUME => sweep_resume,
 		EXCITE_PORT1 => sweep_excite_port1,
 		EXCITE_PORT2 => sweep_excite_port2,
+		DFT_NSAMPLES => dft_nsamples,
+		DFT_BIN1_PHASEINC => dft_bin1_phaseinc,
+		DFT_DIFFBIN_PHASEINC => dft_diffbin_phaseinc,
+		DFT_WINDOW_INC => dft_window_inc,
+		DFT_RESULT_READY => dft_ready,
+		DFT_OUTPUT => dft_output,
+		DFT_NEXT_OUTPUT => dft_next_output,
+		DFT_ENABLE => dft_enable,
 		DEBUG_STATUS => debug
 	);
 	
+	dft_reset <= not dft_enable;
+	
+	SA_DFT: DFT GENERIC MAP(BINS => 64)
+	PORT MAP(
+		CLK => clk160,
+		RESET => dft_reset,
+		PORT1 => adc_port1_data,
+		PORT2 => adc_port2_data,
+		NEW_SAMPLE => adc_port1_ready,
+		NSAMPLES => dft_nsamples,
+		BIN1_PHASEINC => dft_bin1_phaseinc,
+		DIFFBIN_PHASEINC => dft_diffbin_phaseinc,
+		WINDOW_INC => dft_window_inc,
+		WINDOW_TYPE => sampling_window,
+		RESULT_READY => dft_ready,
+		OUTPUT => dft_output,
+		NEXT_OUTPUT => dft_next_output
+	);
+	
 	ConfigMem : SweepConfigMem
 	PORT MAP (
 		clka => clk160,

Software/VNA_embedded/Application/App.cpp

@@ -22,8 +22,8 @@
 #define LOG_MODULE	"App"
 #include "Log.h"
 
-static Protocol::Datapoint result;
 static Protocol::SweepSettings settings;
+static uint16_t lastPoint;
 
 static Protocol::PacketInfo recv_packet, transmit_packet;
 static TaskHandle_t handle;
@@ -45,6 +45,7 @@ static void VNACallback(const Protocol::Datapoint &res) {
 	DEBUG2_HIGH();
 	transmit_packet.type = Protocol::PacketType::Datapoint;
 	transmit_packet.datapoint = res;
+	lastPoint = res.pointNum;
 	BaseType_t woken = false;
 	xTaskNotifyFromISR(handle, FLAG_DATAPOINT, eSetBits, &woken);
 	portYIELD_FROM_ISR(woken);
@@ -205,7 +206,7 @@ void App_Start() {
 		}
 
 		if(sweepActive && HAL_GetTick() - lastNewPoint > 1000) {
-			LOG_WARN("Timed out waiting for point, last received point was %d (Status 0x%04x)", result.pointNum, FPGA::GetStatus());
+			LOG_WARN("Timed out waiting for point, last received point was %d (Status 0x%04x)", lastPoint, FPGA::GetStatus());
 			FPGA::AbortSweep();
 			// restart the current sweep
 			HW::Init();

Software/VNA_embedded/Application/Drivers/FPGA/FPGA.cpp

@@ -3,6 +3,7 @@
 #include "stm.hpp"
 #include "main.h"
 #include "FPGA_HAL.hpp"
+#include <complex>
 
 #define LOG_LEVEL	LOG_LEVEL_DEBUG
 #define LOG_MODULE	"FPGA"
@@ -119,7 +120,7 @@ void FPGA::SetSamplesPerPoint(uint32_t nsamples) {
 	nsamples /= 16;
 	// constrain to maximum value
 	if(nsamples >= 8192) {
-		nsamples = 8192;
+		nsamples = 8191;
 	}
 	WriteRegister(Reg::SamplesPerPoint, nsamples);
 }
@@ -237,7 +238,7 @@ static inline int64_t sign_extend_64(int64_t x, uint16_t bits) {
 }
 
 static FPGA::ReadCallback callback;
-static uint8_t raw[38];
+static uint8_t raw[40];
 static FPGA::SamplingResult result;
 static bool busy_reading = false;
 
@@ -247,15 +248,16 @@ bool FPGA::InitiateSampleRead(ReadCallback cb) {
 		return false;
 	}
 	callback = cb;
-	uint8_t cmd[38] = {0xC0, 0x00};
+	uint8_t cmd[40] = {0xC0, 0x00};
 	// Start data read
 	Low(CS);
 	busy_reading = true;
-	HAL_SPI_TransmitReceive_DMA(&FPGA_SPI, cmd, raw, 38);
+	HAL_SPI_TransmitReceive_DMA(&FPGA_SPI, cmd, raw, 40);
 	return true;
 }
 
 static int64_t assembleSampleResultValue(uint8_t *raw) {
+//	LOG_DEBUG("Raw: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x", raw[4], raw[5], raw[2], raw[3], raw[1], raw[0]);
 	return sign_extend_64(
 			(uint16_t) raw[0] << 8 | raw[1] | (uint32_t) raw[2] << 24
 					| (uint32_t) raw[3] << 16 | (uint64_t) raw[4] << 40
@@ -272,6 +274,8 @@ void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) {
 	result.P2Q = assembleSampleResultValue(&raw[14]);
 	result.RefI = assembleSampleResultValue(&raw[8]);
 	result.RefQ = assembleSampleResultValue(&raw[2]);
+	result.pointNum = (uint16_t)(raw[38]&0x1F) << 8 | raw[39];
+	result.activePort = raw[38] & 0x80 ? 1 : 0;
 	High(CS);
 	busy_reading = false;
 	if ((status & 0x0004) && callback) {
@@ -367,4 +371,25 @@ void FPGA::ResumeHaltedSweep() {
 	High(CS);
 }
 
-
+FPGA::DFTResult FPGA::ReadDFTResult() {
+	uint8_t cmd[2] = {0xA0, 0x00};
+	uint8_t recv[24];
+	Low(CS);
+	HAL_SPI_Transmit(&FPGA_SPI, cmd, 2, 100);
+	HAL_SPI_Receive(&FPGA_SPI, recv, 24, 100);
+	High(CS);
+	// assemble words
+	int64_t p2imag = assembleSampleResultValue(&recv[0]);
+	int64_t p2real = assembleSampleResultValue(&recv[6]);
+	int64_t p1imag = assembleSampleResultValue(&recv[12]);
+	int64_t p1real = assembleSampleResultValue(&recv[18]);
+//	LOG_INFO("DFT raw: %ld, %ld, %ld, %ld", (int32_t) p1real, (int32_t) p1imag, (int32_t) p2real, (int32_t) p2imag);
+//	Log_Flush();
+	auto p1 = std::complex<float>(p1real, p1imag);
+	auto p2 = std::complex<float>(p2real, p2imag);
+	DFTResult res;
+//	LOG_INFO("DFT: %ld, %ld, %ld, %ld", (int32_t) p1.real(), (int32_t) p1.imag(), (int32_t) p2.real(), (int32_t) p2.imag());
+	res.P1 = std::abs(p1);
+	res.P2 = std::abs(p2);
+	return res;
+}

Software/VNA_embedded/Application/Drivers/FPGA/FPGA.hpp

@@ -6,6 +6,7 @@
 namespace FPGA {
 
 static constexpr uint16_t MaxPoints = 4501;
+static constexpr uint16_t DFTbins = 64;
 
 enum class Reg {
 	InterruptMask = 0x00,
@@ -22,12 +23,22 @@ enum class Reg {
 	MAX2871Def3MSB = 0x0D,
 	MAX2871Def4LSB = 0x0E,
 	MAX2871Def4MSB = 0x0F,
+	DFTSamples = 0x10,
+	DFTWindowInc = 0x11,
+	DFTFirstBin = 0x12,
+	DFTFreqSpacing = 0x13,
 };
 
 using SamplingResult = struct _samplingresult {
 	int64_t P1I, P1Q;
 	int64_t P2I, P2Q;
 	int64_t RefI, RefQ;
+	uint16_t pointNum :15;
+	uint16_t activePort :1;
+};
+
+using DFTResult = struct _dftresult {
+	float P1, P2;
 };
 
 using ADCLimits = struct _adclimits {
@@ -59,6 +70,7 @@ enum class Interrupt {
 	NewData = 0x0004,
 	DataOverrun = 0x0008,
 	SweepHalted = 0x0010,
+	DFTReady = 0x0020,
 };
 
 enum class LowpassFilter {
@@ -112,6 +124,7 @@ void WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceRegs, uin
 		uint8_t attenuation, uint64_t frequency, SettlingTime settling, Samples samples, bool halt = false, LowpassFilter filter = LowpassFilter::Auto);
 using ReadCallback = void(*)(const SamplingResult &result);
 bool InitiateSampleRead(ReadCallback cb);
+DFTResult ReadDFTResult();
 ADCLimits GetADCLimits();
 void ResetADCLimits();
 void ResumeHaltedSweep();

Software/VNA_embedded/Application/Drivers/FPGA/FPGA_HAL.hpp

@@ -21,6 +21,7 @@ static constexpr GPIO FPGA_RESET = {.gpio = FPGA_RESET_GPIO_Port, .pin = FPGA_RE
 static constexpr GPIO AUX1 = {.gpio = FPGA_AUX1_GPIO_Port, .pin = FPGA_AUX1_Pin};
 static constexpr GPIO AUX2 = {.gpio = FPGA_AUX2_GPIO_Port, .pin = FPGA_AUX2_Pin};
 static constexpr GPIO AUX3 = {.gpio = FPGA_AUX3_GPIO_Port, .pin = FPGA_AUX3_Pin};
+static constexpr GPIO IRQ = {.gpio = FPGA_INTR_GPIO_Port, .pin = FPGA_INTR_Pin};
 
 static inline void Low(GPIO g) {
 	if(g.gpio) {

Software/VNA_embedded/Application/SpectrumAnalyzer.cpp

@@ -111,6 +111,9 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
 	s = settings;
 	HW::SetMode(HW::Mode::SA);
 	FPGA::SetMode(FPGA::Mode::FPGA);
+	FPGA::DisableInterrupt(FPGA::Interrupt::NewData);
+	FPGA::DisableInterrupt(FPGA::Interrupt::SweepHalted);
+	FPGA::EnableInterrupt(FPGA::Interrupt::DFTReady);
 	// in almost all cases a full sweep requires more points than the FPGA can handle at a time
 	// individually start each point and do the sweep in the uC
 	FPGA::SetNumberOfPoints(1);
@@ -144,6 +147,14 @@ void SA::Setup(Protocol::SpectrumAnalyzerSettings settings) {
 	FPGA::Enable(FPGA::Periphery::ExcitePort1);
 	FPGA::Enable(FPGA::Periphery::Port1Mixer);
 	FPGA::Enable(FPGA::Periphery::Port2Mixer);
+
+	// Configure DFT
+	LOG_INFO("DFT samples: %lu", sampleNum);
+	FPGA::WriteRegister(FPGA::Reg::DFTSamples, sampleNum - 1);
+	FPGA::WriteRegister(FPGA::Reg::DFTWindowInc, 65536 / sampleNum);
+	FPGA::WriteRegister(FPGA::Reg::DFTFirstBin, 17920);
+	FPGA::WriteRegister(FPGA::Reg::DFTFreqSpacing, 1147);
+
 	lastLO2 = 0;
 	active = true;
 	StartNextSample();
@@ -154,6 +165,19 @@ bool SA::MeasurementDone(const FPGA::SamplingResult &result) {
 		return false;
 	}
 	FPGA::AbortSweep();
+
+	uint16_t i=0;
+	while(FPGA::GetStatus() & (uint16_t) FPGA::Interrupt::DFTReady) {
+		auto dft = FPGA::ReadDFTResult();
+		dft.P1 /= sampleNum;
+		dft.P2 /= sampleNum;
+		LOG_INFO("DFT %d: %lu, %lu", i, (uint32_t) dft.P1, (uint32_t) dft.P2);
+		Log_Flush();
+		i++;
+	}
+	FPGA::DisableInterrupt(FPGA::Interrupt::DFTReady);
+	FPGA::EnableInterrupt(FPGA::Interrupt::DFTReady);
+
 	float port1 = abs(std::complex<float>(result.P1I, result.P1Q))/sampleNum;
 	float port2 = abs(std::complex<float>(result.P2I, result.P2Q))/sampleNum;
 	if(port1 < port1Measurement) {

Software/VNA_embedded/Application/VNA.cpp

@@ -202,6 +202,11 @@ bool VNA::MeasurementDone(const FPGA::SamplingResult &result) {
 	if(!active) {
 		return false;
 	}
+	if(result.pointNum != pointCnt || !result.activePort != excitingPort1) {
+		LOG_WARN("Indicated point does not match (%u != %u, %d != %d)", result.pointNum, pointCnt, result.activePort, !excitingPort1);
+		FPGA::AbortSweep();
+		return false;
+	}
 	// normal sweep mode
 	auto port1_raw = std::complex<float>(result.P1I, result.P1Q);
 	auto port2_raw = std::complex<float>(result.P2I, result.P2Q);