caiyu/LibreVNA
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3 Commits

Author SHA1 Message Date
Jan Käberich
8b9b8265b9 Use full multiplier bitwidth for windowing + increased number of DFT bins 2020-11-08 14:38:31 +01:00
Jan Käberich
f889ec854b Test of DFT implementation in FPGA 2020-11-08 14:38:31 +01:00
Jan Käberich
16f050a11e FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00