Jan Käberich
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73e26a25c4
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WIP: synchronization
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2022-08-08 18:08:40 +02:00 |
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Jan Käberich
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7b3aa6e158
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WIP: synchronization
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2022-08-07 13:28:31 +02:00 |
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Jan Käberich
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58918f81c1
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WIP: device synchronization
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2022-08-07 03:01:22 +02:00 |
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Jan Käberich
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37d8474260
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Added stages to FPGA protocol
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2022-04-01 23:01:22 +02:00 |
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Jan Käberich
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7bc18881a5
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Allow different source PLL power per sweep point, add power range to sweep
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2021-07-09 22:25:54 +02:00 |
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Jan Käberich
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ce475fa042
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Basic DFT spectrum analysis working
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2020-11-08 14:38:31 +01:00 |
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Jan Käberich
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f889ec854b
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Test of DFT implementation in FPGA
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2020-11-08 14:38:31 +01:00 |
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Jan Käberich
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2157b3f3c4
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Improved USB throughput, stimulus power up to 0dbm, fine tuning of dynamic range
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2020-09-29 23:03:20 +02:00 |
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Jan Käberich
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926392e5b9
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Bugfixes and speed improvements
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2020-09-26 23:34:31 +02:00 |
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Jan Käberich
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de8761545d
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Experimental feature: only excite one port when other traces are paused
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2020-09-15 23:22:08 +02:00 |
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Jan Käberich
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7d9d5e27eb
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different settling time/samples per point in sweep
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2020-09-14 11:03:37 +02:00 |
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Jan Käberich
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16f050a11e
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FPGA project adapted to new pinout
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2020-08-30 16:19:18 +02:00 |
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