caiyu/LibreVNA
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4 Commits

Author SHA1 Message Date
Jan Käberich
926392e5b9 Bugfixes and speed improvements 2020-09-26 23:34:31 +02:00
Jan Käberich
57b4ebfb26 mitigation for peaks caused by limited fractional divider in PLLs 2020-09-20 10:13:06 +02:00
Jan Käberich
fc3ce7a828 Improved spectrum analyzer mode 
- Faster sweeps by changing 2.LO only when necessary and using 400kHz I2C frequency
- Added FPGA settings for selectable ADC samplerate
- Additional measurement with different ADC samplerate when signal ID is on to remove ADC images
 2020-09-17 19:54:03 +02:00
Jan Käberich
38e73365df proof-of-concept spectrum analyzer mode 2020-09-17 15:51:20 +02:00