6 Commits

Author	SHA1	Message	Date
Jan Käberich	57b4ebfb26	mitigation for peaks caused by limited fractional divider in PLLs	2020-09-20 10:13:06 +02:00
Jan Käberich	fc3ce7a828	Improved spectrum analyzer mode ... - Faster sweeps by changing 2.LO only when necessary and using 400kHz I2C frequency - Added FPGA settings for selectable ADC samplerate - Additional measurement with different ADC samplerate when signal ID is on to remove ADC images	2020-09-17 19:54:03 +02:00
Jan Käberich	38e73365df	proof-of-concept spectrum analyzer mode	2020-09-17 15:51:20 +02:00
Jan Käberich	de8761545d	Experimental feature: only excite one port when other traces are paused	2020-09-15 23:22:08 +02:00
Jan Käberich	aae01a602e	Working generator mode	2020-09-13 18:01:32 +02:00
Jan Käberich	b7033a029e	Refactoring: splitting mode logic into different classes	2020-09-13 14:44:45 +02:00