Jan Käberich
9b4865dceb
Renaming packet types, implementing different packet contents per hardware version
2023-02-20 13:08:31 +01:00
Andre Dunford
9b38a1fc3d
implement optional device status updates
2022-12-05 22:29:33 -08:00
Jan Käberich
df8fa25935
Increase settling time for PLLs
2022-11-19 16:26:38 +01:00
Jan Käberich
c6ef075f4f
split device info and status protocol messages
2022-04-03 20:26:30 +02:00
Jan Käberich
37d8474260
Added stages to FPGA protocol
2022-04-01 23:01:22 +02:00
Jan Käberich
00f0de43f2
Timeout handling in FPGA communication (better recovery from missing reference)
2020-12-15 18:03:29 +01:00
Jan Käberich
ce475fa042
Basic DFT spectrum analysis working
2020-11-08 14:38:31 +01:00
Jan Käberich
6bc6b1d202
Speed improvements
2020-10-03 21:56:09 +02:00
Jan Käberich
fc3ce7a828
Improved spectrum analyzer mode
...
- Faster sweeps by changing 2.LO only when necessary and using 400kHz I2C frequency
- Added FPGA settings for selectable ADC samplerate
- Additional measurement with different ADC samplerate when signal ID is on to remove ADC images
2020-09-17 19:54:03 +02:00
Jan Käberich
38e73365df
proof-of-concept spectrum analyzer mode
2020-09-17 15:51:20 +02:00
Jan Käberich
00244022c9
Refactoring, better code encapsulation for different operating modes
2020-09-17 09:53:52 +02:00
