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#
# Xilinx Core Generator version 14.6
# Date: Fri Nov  6 13:57:46 2020
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:xbip_dsp48_macro:2.1
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT DSP48_Macro xilinx.com:ip:xbip_dsp48_macro:2.1
# END Select
# BEGIN Parameters
CSET a_binarywidth=0
CSET a_width=18
CSET areg_1=false
CSET areg_2=false
CSET areg_3=true
CSET areg_4=true
CSET b_binarywidth=0
CSET b_width=18
CSET breg_1=false
CSET breg_2=false
CSET breg_3=true
CSET breg_4=true
CSET c_binarywidth=0
CSET c_width=48
CSET cinreg_1=false
CSET cinreg_2=false
CSET cinreg_3=false
CSET cinreg_4=false
CSET cinreg_5=false
CSET component_name=DSP_SLICE
CSET concat_binarywidth=0
CSET concat_width=48
CSET concatreg_3=false
CSET concatreg_4=false
CSET concatreg_5=false
CSET creg_1=false
CSET creg_2=false
CSET creg_3=true
CSET creg_4=true
CSET creg_5=true
CSET d_binarywidth=0
CSET d_width=18
CSET dreg_1=false
CSET dreg_2=false
CSET dreg_3=false
CSET gui_behaviour=Coregen
CSET has_a_ce=false
CSET has_a_sclr=false
CSET has_acout=false
CSET has_b_ce=false
CSET has_b_sclr=false
CSET has_bcout=false
CSET has_c_ce=false
CSET has_c_sclr=false
CSET has_carrycascout=false
CSET has_carryout=false
CSET has_ce=true
CSET has_concat_ce=false
CSET has_concat_sclr=false
CSET has_d_ce=false
CSET has_d_sclr=false
CSET has_m_ce=false
CSET has_m_sclr=false
CSET has_p_ce=false
CSET has_p_sclr=false
CSET has_pcout=false
CSET has_sclr=false
CSET has_sel_ce=false
CSET has_sel_sclr=false
CSET instruction1=A*B
CSET instruction2=A*B+C
CSET instruction3=#
CSET instruction4=#
CSET instruction5=#
CSET instruction6=#
CSET instruction7=#
CSET instruction8=#
CSET instruction_list=#
CSET mreg_5=true
CSET opreg_1=false
CSET opreg_2=false
CSET opreg_3=true
CSET opreg_4=true
CSET opreg_5=true
CSET output_properties=Full_Precision
CSET p_binarywidth=0
CSET p_full_width=48
CSET p_width=48
CSET pcin_binarywidth=0
CSET pipeline_options=Automatic
CSET preg_6=true
CSET show_filtered=false
CSET tier_1=false
CSET tier_2=false
CSET tier_3=false
CSET tier_4=false
CSET tier_5=false
CSET tier_6=false
CSET use_dsp48=true
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2012-11-05T14:23:53Z
# END Extra information
GENERATE
# CRC: 57648294