140 lines
5.1 KiB
VHDL
140 lines
5.1 KiB
VHDL
--------------------------------------------------------------------------------
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-- This file is owned and controlled by Xilinx and must be used solely --
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-- for design, simulation, implementation and creation of design files --
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-- limited to Xilinx devices or technologies. Use with non-Xilinx --
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-- devices or technologies is expressly prohibited and immediately --
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-- terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
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-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
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-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
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-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
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-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
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-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
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-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
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-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
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-- PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support appliances, --
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-- devices, or systems. Use in such applications are expressly --
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-- prohibited. --
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-- --
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-- (c) Copyright 1995-2020 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file DSP48.vhd when simulating
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-- the core, DSP48. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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LIBRARY XilinxCoreLib;
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-- synthesis translate_on
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ENTITY DSP48 IS
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PORT (
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clk : IN STD_LOGIC;
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ce : IN STD_LOGIC;
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sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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);
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END DSP48;
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ARCHITECTURE DSP48_a OF DSP48 IS
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-- synthesis translate_off
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COMPONENT wrapped_DSP48
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PORT (
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clk : IN STD_LOGIC;
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ce : IN STD_LOGIC;
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sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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);
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END COMPONENT;
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-- Configuration specification
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FOR ALL : wrapped_DSP48 USE ENTITY XilinxCoreLib.xbip_dsp48_macro_v2_1(behavioral)
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GENERIC MAP (
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c_a_width => 18,
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c_b_width => 18,
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c_c_width => 48,
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c_concat_width => 48,
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c_constant_1 => 1,
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c_d_width => 18,
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c_has_a => 1,
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c_has_acin => 0,
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c_has_acout => 0,
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c_has_b => 1,
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c_has_bcin => 0,
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c_has_bcout => 0,
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c_has_c => 1,
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c_has_carrycascin => 0,
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c_has_carrycascout => 0,
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c_has_carryin => 0,
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c_has_carryout => 0,
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c_has_ce => 1,
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c_has_cea => 0,
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c_has_ceb => 0,
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c_has_cec => 0,
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c_has_ceconcat => 0,
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c_has_ced => 0,
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c_has_cem => 0,
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c_has_cep => 0,
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c_has_cesel => 0,
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c_has_concat => 0,
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c_has_d => 0,
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c_has_indep_ce => 0,
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c_has_indep_sclr => 0,
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c_has_pcin => 0,
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c_has_pcout => 0,
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c_has_sclr => 0,
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c_has_sclra => 0,
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c_has_sclrb => 0,
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c_has_sclrc => 0,
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c_has_sclrconcat => 0,
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c_has_sclrd => 0,
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c_has_sclrm => 0,
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c_has_sclrp => 0,
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c_has_sclrsel => 0,
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c_latency => -1,
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c_model_type => 0,
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c_opmodes => "0000000000010000000,0000001100010000000",
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c_p_lsb => 0,
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c_p_msb => 47,
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c_reg_config => "00000000000011100111100111100100",
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c_sel_width => 1,
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c_test_core => 0,
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c_verbosity => 0,
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c_xdevicefamily => "spartan6"
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);
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_DSP48
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PORT MAP (
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clk => clk,
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ce => ce,
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sel => sel,
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a => a,
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b => b,
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c => c,
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p => p
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);
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-- synthesis translate_on
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END DSP48_a;
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