107 lines
4.4 KiB
VHDL
107 lines
4.4 KiB
VHDL
--------------------------------------------------------------------------------
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-- This file is owned and controlled by Xilinx and must be used solely --
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-- for design, simulation, implementation and creation of design files --
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-- limited to Xilinx devices or technologies. Use with non-Xilinx --
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-- devices or technologies is expressly prohibited and immediately --
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-- terminates your license. --
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-- --
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-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY --
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-- FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY --
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-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE --
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-- IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS --
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-- MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY --
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-- CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY --
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-- RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY --
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-- DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
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-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
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-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
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-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A --
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-- PARTICULAR PURPOSE. --
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-- --
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-- Xilinx products are not intended for use in life support appliances, --
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-- devices, or systems. Use in such applications are expressly --
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-- prohibited. --
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-- --
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-- (c) Copyright 1995-2020 Xilinx, Inc. --
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-- All rights reserved. --
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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-- You must compile the wrapper file SinCos.vhd when simulating
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-- the core, SinCos. When compiling the wrapper file, be sure to
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-- reference the XilinxCoreLib VHDL simulation library. For detailed
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-- instructions, please refer to the "CORE Generator Help".
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-- The synthesis directives "translate_off/translate_on" specified
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-- below are supported by Xilinx, Mentor Graphics and Synplicity
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-- synthesis tools. Ensure they are correct for your synthesis tool(s).
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- synthesis translate_off
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LIBRARY XilinxCoreLib;
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-- synthesis translate_on
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ENTITY SinCos IS
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PORT (
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clk : IN STD_LOGIC;
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phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
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cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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);
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END SinCos;
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ARCHITECTURE SinCos_a OF SinCos IS
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-- synthesis translate_off
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COMPONENT wrapped_SinCos
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PORT (
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clk : IN STD_LOGIC;
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phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
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cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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);
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END COMPONENT;
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-- Configuration specification
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FOR ALL : wrapped_SinCos USE ENTITY XilinxCoreLib.dds_compiler_v4_0(behavioral)
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GENERIC MAP (
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c_accumulator_width => 12,
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c_amplitude => 0,
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c_channels => 1,
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c_has_ce => 0,
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c_has_channel_index => 0,
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c_has_phase_out => 0,
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c_has_phasegen => 0,
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c_has_rdy => 0,
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c_has_rfd => 0,
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c_has_sclr => 0,
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c_has_sincos => 1,
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c_latency => -1,
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c_mem_type => 1,
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c_negative_cosine => 0,
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c_negative_sine => 0,
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c_noise_shaping => 0,
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c_optimise_goal => 0,
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c_output_width => 16,
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c_outputs_required => 2,
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c_phase_angle_width => 12,
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c_phase_increment => 2,
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c_phase_increment_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
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c_phase_offset => 0,
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c_phase_offset_value => "0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0",
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c_por_mode => 0,
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c_use_dsp48 => 0,
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c_xdevicefamily => "spartan6"
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);
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-- synthesis translate_on
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BEGIN
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-- synthesis translate_off
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U0 : wrapped_SinCos
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PORT MAP (
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clk => clk,
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phase_in => phase_in,
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cosine => cosine,
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sine => sine
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);
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-- synthesis translate_on
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END SinCos_a;
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