118 lines
2.9 KiB
VHDL
118 lines
2.9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 16:59:45 05/05/2020
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-- Design Name:
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-- Module Name: MAX2871 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity MAX2871 is
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Generic (CLK_DIV : integer);
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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REG4 : in STD_LOGIC_VECTOR (31 downto 0);
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REG3 : in STD_LOGIC_VECTOR (31 downto 0);
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REG1 : in STD_LOGIC_VECTOR (31 downto 0);
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REG0 : in STD_LOGIC_VECTOR (31 downto 0);
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RELOAD : in STD_LOGIC;
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CLK_OUT : out STD_LOGIC;
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MOSI : out STD_LOGIC;
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LE : out STD_LOGIC;
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DONE : out STD_LOGIC);
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end MAX2871;
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architecture Behavioral of MAX2871 is
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signal clk_cnt : integer range 0 to (CLK_DIV/2)-1;
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signal reg_cnt : integer range 0 to 3;
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signal bit_cnt : integer range 0 to 32;
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signal latched_regs : std_logic_vector(127 downto 0);
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signal sclk : std_logic;
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signal latch : std_logic;
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signal done_int : std_logic;
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begin
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CLK_OUT <= sclk;
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MOSI <= latched_regs(127);
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LE <= latch;
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DONE <= done_int;
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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sclk <= '0';
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latch <= '0';
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done_int <= '1';
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else
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if done_int = '1' then
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-- can start a new reload process
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if RELOAD = '1' then
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done_int <= '0';
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latched_regs <= REG4 & REG3 & REG1 & REG0;
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reg_cnt <= 0;
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bit_cnt <= 0;
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clk_cnt <= 0;
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end if;
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else
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if clk_cnt < (CLK_DIV/2) - 1 then
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clk_cnt <= clk_cnt + 1;
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else
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clk_cnt <= 0;
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-- advance SPI state machine
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if bit_cnt < 32 then
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if sclk = '0' then
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sclk <= '1';
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else
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-- falling edge of clk, shift out new bit
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sclk <= '0';
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latched_regs <= latched_regs(126 downto 0) & "0";
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bit_cnt <= bit_cnt + 1;
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end if;
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else
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-- shifted out one register, strobe latch
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if latch = '0' then
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latch <= '1';
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else
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latch <= '0';
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-- move on to next register
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if reg_cnt < 3 then
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reg_cnt <= reg_cnt + 1;
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bit_cnt <= 0;
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else
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-- all done
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done_int <= '1';
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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