62 lines
1.3 KiB
VHDL
62 lines
1.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:06:31 05/12/2020
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-- Design Name:
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-- Module Name: ResetDelay - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ResetDelay is
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Generic(CLK_DELAY : integer);
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Port ( CLK : in STD_LOGIC;
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IN_RESET : in STD_LOGIC;
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OUT_RESET : out STD_LOGIC);
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end ResetDelay;
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architecture Behavioral of ResetDelay is
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signal clk_cnt : integer range 0 to CLK_DELAY-1;
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begin
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process(CLK, IN_RESET)
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begin
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if rising_edge(CLK) then
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if IN_RESET = '1' then
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clk_cnt <= 0;
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OUT_RESET <= '1';
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else
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if clk_cnt < CLK_DELAY-1 then
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clk_cnt <= clk_cnt + 1;
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else
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OUT_RESET <= '0';
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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