54 lines
1.2 KiB
VHDL
54 lines
1.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 23:31:10 05/15/2020
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-- Design Name:
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-- Module Name: Synchronizer - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Synchronizer is
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Generic(stages : integer);
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Port ( CLK : in STD_LOGIC;
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SYNC_IN : in STD_LOGIC;
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SYNC_OUT : out STD_LOGIC);
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end Synchronizer;
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architecture Behavioral of Synchronizer is
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signal sync_line : std_logic_vector(stages downto 0);
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begin
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SYNC_OUT <= sync_line(stages);
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process(CLK)
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begin
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if rising_edge(CLK) then
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sync_line <= sync_line(stages-1 downto 0) & SYNC_IN;
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end if;
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end process;
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end Behavioral;
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