128 lines
3.3 KiB
VHDL
128 lines
3.3 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:46:34 05/07/2020
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-- Design Name:
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-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_MAX2871.vhd
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-- Project Name: VNA
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: MAX2871
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY Test_MAX2871 IS
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END Test_MAX2871;
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ARCHITECTURE behavior OF Test_MAX2871 IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT MAX2871
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Generic (CLK_DIV : integer);
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PORT(
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CLK : IN std_logic;
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RESET : IN std_logic;
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REG4 : IN std_logic_vector(31 downto 0);
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REG3 : IN std_logic_vector(31 downto 0);
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REG1 : IN std_logic_vector(31 downto 0);
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REG0 : IN std_logic_vector(31 downto 0);
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RELOAD : IN std_logic;
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CLK_OUT : OUT std_logic;
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MOSI : OUT std_logic;
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LE : OUT std_logic;
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DONE : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal CLK : std_logic := '0';
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signal RESET : std_logic := '0';
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signal REG4 : std_logic_vector(31 downto 0) := (others => '0');
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signal REG3 : std_logic_vector(31 downto 0) := (others => '0');
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signal REG1 : std_logic_vector(31 downto 0) := (others => '0');
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signal REG0 : std_logic_vector(31 downto 0) := (others => '0');
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signal RELOAD : std_logic := '0';
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--Outputs
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signal CLK_OUT : std_logic;
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signal MOSI : std_logic;
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signal LE : std_logic;
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signal DONE : std_logic;
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-- Clock period definitions
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constant CLK_period : time := 6.25 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: MAX2871
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GENERIC MAP(CLK_DIV => 10)
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PORT MAP (
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CLK => CLK,
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RESET => RESET,
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REG4 => REG4,
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REG3 => REG3,
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REG1 => REG1,
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REG0 => REG0,
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RELOAD => RELOAD,
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CLK_OUT => CLK_OUT,
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MOSI => MOSI,
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LE => LE,
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DONE => DONE
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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RESET <= '1';
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wait for 100 ns;
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RESET <= '0';
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wait for CLK_period*10;
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-- insert stimulus here
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REG4 <= "11111111000000001111111100000000";
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REG3 <= "11110000111100001111000011110000";
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REG1 <= "11001100110011001100110011001100";
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REG0 <= "10101010101010101010101010101010";
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RELOAD <= '1';
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wait for CLK_period;
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RELOAD <= '0';
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wait;
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end process;
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END;
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