310 lines
8.9 KiB
VHDL
310 lines
8.9 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 18:42:26 05/07/2020
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-- Design Name:
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-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_SPICommands.vhd
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-- Project Name: VNA
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: SPICommands
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY Test_SPICommands IS
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END Test_SPICommands;
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ARCHITECTURE behavior OF Test_SPICommands IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT SPICommands
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PORT(
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CLK : IN std_logic;
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RESET : IN std_logic;
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SCLK : IN std_logic;
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MOSI : IN std_logic;
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MISO : OUT std_logic;
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NSS : IN std_logic;
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NEW_SAMPLING_DATA : IN std_logic;
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SAMPLING_RESULT : IN std_logic_vector(303 downto 0);
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SOURCE_UNLOCKED : IN std_logic;
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LO_UNLOCKED : IN std_logic;
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MAX2871_DEF_4 : OUT std_logic_vector(31 downto 0);
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MAX2871_DEF_3 : OUT std_logic_vector(31 downto 0);
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MAX2871_DEF_1 : OUT std_logic_vector(31 downto 0);
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MAX2871_DEF_0 : OUT std_logic_vector(31 downto 0);
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SWEEP_DATA : OUT std_logic_vector(95 downto 0);
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SWEEP_ADDRESS : OUT std_logic_vector(12 downto 0);
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SWEEP_WRITE : OUT std_logic_vector(0 downto 0);
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SWEEP_POINTS : OUT std_logic_vector(12 downto 0);
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NSAMPLES : OUT std_logic_vector(12 downto 0);
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PORT1_EN : OUT std_logic;
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PORT2_EN : OUT std_logic;
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REF_EN : OUT std_logic;
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AMP_SHDN : OUT std_logic;
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SOURCE_RF_EN : OUT std_logic;
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LO_RF_EN : OUT std_logic;
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LEDS : OUT std_logic_vector(2 downto 0);
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INTERRUPT_ASSERTED : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal CLK : std_logic := '0';
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signal RESET : std_logic := '0';
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signal SCLK : std_logic := '0';
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signal MOSI : std_logic := '0';
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signal NSS : std_logic := '0';
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signal NEW_SAMPLING_DATA : std_logic := '0';
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signal SAMPLING_RESULT : std_logic_vector(303 downto 0) := (others => '0');
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signal SOURCE_UNLOCKED : std_logic := '1';
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signal LO_UNLOCKED : std_logic := '1';
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--Outputs
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signal MISO : std_logic;
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signal MAX2871_DEF_4 : std_logic_vector(31 downto 0);
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signal MAX2871_DEF_3 : std_logic_vector(31 downto 0);
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signal MAX2871_DEF_1 : std_logic_vector(31 downto 0);
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signal MAX2871_DEF_0 : std_logic_vector(31 downto 0);
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signal SWEEP_DATA : std_logic_vector(95 downto 0);
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signal SWEEP_ADDRESS : std_logic_vector(12 downto 0);
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signal SWEEP_WRITE : std_logic_vector(0 downto 0);
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signal SWEEP_POINTS : std_logic_vector(12 downto 0);
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signal NSAMPLES : std_logic_vector(12 downto 0);
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signal PORT1_EN : std_logic;
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signal PORT2_EN : std_logic;
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signal REF_EN : std_logic;
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signal AMP_SHDN : std_logic;
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signal SOURCE_RF_EN : std_logic;
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signal LO_RF_EN : std_logic;
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signal LEDS : std_logic_vector(2 downto 0);
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signal INTERRUPT_ASSERTED : std_logic;
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-- Clock period definitions
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constant CLK_period : time := 6.25 ns;
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constant SPI_CLK_period : time := 100 ns;
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signal data_signal : std_logic_vector(15 downto 0);
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: SPICommands PORT MAP (
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CLK => CLK,
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RESET => RESET,
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SCLK => SCLK,
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MOSI => MOSI,
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MISO => MISO,
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NSS => NSS,
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NEW_SAMPLING_DATA => NEW_SAMPLING_DATA,
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SAMPLING_RESULT => SAMPLING_RESULT,
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SOURCE_UNLOCKED => SOURCE_UNLOCKED,
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LO_UNLOCKED => LO_UNLOCKED,
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MAX2871_DEF_4 => MAX2871_DEF_4,
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MAX2871_DEF_3 => MAX2871_DEF_3,
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MAX2871_DEF_1 => MAX2871_DEF_1,
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MAX2871_DEF_0 => MAX2871_DEF_0,
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SWEEP_DATA => SWEEP_DATA,
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SWEEP_ADDRESS => SWEEP_ADDRESS,
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SWEEP_WRITE => SWEEP_WRITE,
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SWEEP_POINTS => SWEEP_POINTS,
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NSAMPLES => NSAMPLES,
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PORT1_EN => PORT1_EN,
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PORT2_EN => PORT2_EN,
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REF_EN => REF_EN,
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AMP_SHDN => AMP_SHDN,
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SOURCE_RF_EN => SOURCE_RF_EN,
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LO_RF_EN => LO_RF_EN,
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LEDS => LEDS,
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INTERRUPT_ASSERTED => INTERRUPT_ASSERTED
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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procedure SPI(data : std_logic_vector(15 downto 0)) is
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begin
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MOSI <= data(15);
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data_signal <= data(14 downto 0) & "0";
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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MOSI <= data_signal(15);
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data_signal <= data_signal(14 downto 0) & '0';
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wait for SPI_CLK_period/2;
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SCLK <= '1';
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wait for SPI_CLK_period/2;
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SCLK <= '0';
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end procedure SPI;
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begin
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-- hold reset state for 100 ns.
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RESET <= '1';
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NSS <= '1';
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wait for 100 ns;
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RESET <= '0';
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wait for CLK_period*10;
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NSS <= '0';
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SPI("1100000000000000");
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SPI("0000000000000000");
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NSS <= '1';
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wait for CLK_period*50;
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-- insert stimulus here
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-- write number of points
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NSS <= '0';
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SPI("1000000000000001");
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SPI("1111000011110000");
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NSS <= '1';
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wait for CLK_period*100;
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-- Write sweep config
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NSS <= '0';
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SPI("0000000000001011");
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SPI("1111111100000000");
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SPI("1111000011110000");
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SPI("1100110011001100");
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SPI("1010101010101010");
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SPI("1101101101101101");
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SPI("1110111011101110");
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SPI("1111101111101111");
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NSS <= '1';
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wait for CLK_period*50;
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NEW_SAMPLING_DATA <= '1';
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wait for CLK_period;
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NEW_SAMPLING_DATA <= '0';
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wait for CLK_period*20;
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NSS <= '0';
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SPI("1100000000000000");
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NSS <= '1';
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wait for CLK_period*50;
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NEW_SAMPLING_DATA <= '1';
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wait for CLK_period;
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NEW_SAMPLING_DATA <= '0';
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wait for CLK_period*20;
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NSS <= '0';
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SPI("1100000000000000");
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NSS <= '1';
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wait;
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end process;
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END;
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