162 lines
4.4 KiB
VHDL
162 lines
4.4 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 18:40:38 05/05/2020
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-- Design Name:
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-- Module Name: /home/jan/Projekte/VNA/FPGA/VNA/Test_Sampling.vhd
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-- Project Name: VNA
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: Sampling
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--USE ieee.numeric_std.ALL;
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ENTITY Test_Sampling IS
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END Test_Sampling;
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ARCHITECTURE behavior OF Test_Sampling IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Sampling
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Generic(CLK_CYCLES_PRE_DONE : integer);
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PORT(
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CLK : IN std_logic;
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RESET : IN std_logic;
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ADC_PRESCALER : IN std_logic_vector(7 downto 0);
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PHASEINC : IN std_logic_vector(11 downto 0);
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PORT1 : IN std_logic_vector(17 downto 0);
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PORT2 : IN std_logic_vector(17 downto 0);
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REF : IN std_logic_vector(17 downto 0);
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NEW_SAMPLE : IN std_logic;
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START : IN std_logic;
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SAMPLES : IN std_logic_vector(12 downto 0);
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ADC_START : OUT std_logic;
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DONE : OUT std_logic;
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PRE_DONE : OUT std_logic;
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PORT1_I : OUT std_logic_vector(47 downto 0);
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PORT1_Q : OUT std_logic_vector(47 downto 0);
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PORT2_I : OUT std_logic_vector(47 downto 0);
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PORT2_Q : OUT std_logic_vector(47 downto 0);
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REF_I : OUT std_logic_vector(47 downto 0);
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REF_Q : OUT std_logic_vector(47 downto 0);
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ACTIVE : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal CLK : std_logic := '0';
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signal RESET : std_logic := '0';
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signal PORT1 : std_logic_vector(17 downto 0) := (others => '0');
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signal PORT2 : std_logic_vector(17 downto 0) := (others => '0');
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signal REF : std_logic_vector(17 downto 0) := (others => '0');
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signal NEW_SAMPLE : std_logic := '0';
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signal START : std_logic := '0';
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signal SAMPLES : std_logic_vector(12 downto 0) := (others => '0');
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signal ADC_PRESCALER : std_logic_vector(7 downto 0);
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signal PHASEINC : std_logic_vector(11 downto 0);
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--Outputs
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signal ADC_START : std_logic;
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signal DONE : std_logic;
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signal PRE_DONE : std_logic;
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signal PORT1_I : std_logic_vector(47 downto 0);
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signal PORT1_Q : std_logic_vector(47 downto 0);
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signal PORT2_I : std_logic_vector(47 downto 0);
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signal PORT2_Q : std_logic_vector(47 downto 0);
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signal REF_I : std_logic_vector(47 downto 0);
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signal REF_Q : std_logic_vector(47 downto 0);
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-- Clock period definitions
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constant CLK_period : time := 6.25 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Sampling
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Generic MAP(CLK_CYCLES_PRE_DONE => 0)
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PORT MAP (
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CLK => CLK,
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RESET => RESET,
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ADC_PRESCALER => ADC_PRESCALER,
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PHASEINC => PHASEINC,
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PORT1 => PORT1,
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PORT2 => PORT2,
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REF => REF,
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NEW_SAMPLE => NEW_SAMPLE,
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START => START,
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SAMPLES => SAMPLES,
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ADC_START => ADC_START,
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DONE => DONE,
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PRE_DONE => PRE_DONE,
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PORT1_I => PORT1_I,
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PORT1_Q => PORT1_Q,
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PORT2_I => PORT2_I,
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PORT2_Q => PORT2_Q,
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REF_I => REF_I,
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REF_Q => REF_Q,
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ACTIVE => open
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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-- hold reset state for 100 ns.
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RESET <= '1';
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wait for 100 ns;
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RESET <= '0';
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wait for CLK_period*10;
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-- insert stimulus here
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ADC_PRESCALER <= "011110000";
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PHASEINC <= "010001100000";
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PORT1 <= "000001111111111111";
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PORT2 <= "000011111111111111";
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REF <= "000111111111111111";
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SAMPLES <= "0000000000001";
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START <= '1';
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while True loop
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wait until ADC_START = '1';
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START <= '0';
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wait for CLK_period * 110;
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NEW_SAMPLE <= '1';
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wait for CLK_period;
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NEW_SAMPLE <= '0';
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end loop;
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wait;
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end process;
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END;
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