202 lines
5.9 KiB
VHDL
202 lines
5.9 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 18:18:17 11/06/2020
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-- Design Name:
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-- Module Name: Windowing - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Windowing is
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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WINDOW_TYPE : in STD_LOGIC_VECTOR (1 downto 0);
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PORT1_RAW : in STD_LOGIC_VECTOR (15 downto 0);
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PORT2_RAW : in STD_LOGIC_VECTOR (15 downto 0);
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REF_RAW : in STD_LOGIC_VECTOR (15 downto 0);
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ADC_READY : in STD_LOGIC;
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PORT1_WINDOWED : out STD_LOGIC_VECTOR (17 downto 0);
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PORT2_WINDOWED : out STD_LOGIC_VECTOR (17 downto 0);
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REF_WINDOWED : out STD_LOGIC_VECTOR (17 downto 0);
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WINDOWING_DONE : out STD_LOGIC;
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NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0));
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end Windowing;
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architecture Behavioral of Windowing is
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COMPONENT window
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PORT(
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CLK : IN std_logic;
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INDEX : IN std_logic_vector(6 downto 0);
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WINDOW_TYPE : IN std_logic_vector(1 downto 0);
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VALUE : OUT std_logic_vector(15 downto 0)
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);
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END COMPONENT;
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COMPONENT DSP_SLICE
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PORT (
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clk : IN STD_LOGIC;
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ce : IN STD_LOGIC;
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sel : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
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a : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
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c : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
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p : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
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);
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END COMPONENT;
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signal window_index : std_logic_vector(6 downto 0);
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signal window_value : std_logic_vector(15 downto 0);
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signal window_sample_cnt : integer range -8 to 8191;
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signal window_index_inc : integer range 0 to 8;
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signal window_sample_compare : integer range 0 to 8191;
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signal window_sample_cnt_inc : integer range 0 to 8;
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signal mult_a : std_logic_vector(17 downto 0);
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signal mult_b : std_logic_vector(17 downto 0);
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signal mult_p : std_logic_vector(47 downto 0);
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signal mult_enable : std_logic;
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type states is (CalcWindowInc, WaitingForADC, CalcPort1, CalcPort2, CalcRef, MultDelay1, MultDelay2, StorePort1, StorePort2, StoreRef);
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signal state : states;
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begin
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Mult : DSP_SLICE
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PORT MAP (
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clk => CLK,
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ce => mult_enable,
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sel => "0",
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a => mult_a,
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b => mult_b,
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c => (others => '0'),
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p => mult_p
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);
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WindowROM: window PORT MAP(
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CLK => CLK,
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INDEX => window_index,
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WINDOW_TYPE => WINDOW_TYPE,
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VALUE => window_value
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);
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-- sign extend multiplier inputs
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mult_a(17 downto 16) <= mult_a(15) & mult_a(15);
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mult_b(17 downto 16) <= mult_b(15) & mult_b(15);
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mult_a(15 downto 0) <= window_value;
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process(CLK)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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WINDOWING_DONE <= '0';
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state <= CalcWindowInc;
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mult_enable <= '0';
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mult_b(15 downto 0) <= (others => '0');
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window_index <= (others => '0');
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window_sample_cnt <= 0;
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window_sample_compare <= to_integer(unsigned(NSAMPLES));
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else
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case state is
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when CalcWindowInc =>
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case window_sample_compare is
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when 1 =>
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-- 16 samples, increment on every sample by 8
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window_sample_cnt_inc <= 1;
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window_index_inc <= 8;
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when 2 to 3 =>
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-- 32-48 samples, increment by 4
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window_sample_cnt_inc <= 2;
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window_index_inc <= 4;
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when 4 to 7 =>
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-- 64-112 samples, increment by 2
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window_sample_cnt_inc <= 4;
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window_index_inc <= 2;
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when others =>
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-- 128 or more samples, increment by 1
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window_sample_cnt_inc <= 8;
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window_index_inc <= 1;
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end case;
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state <= WaitingForADC;
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when WaitingForADC =>
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WINDOWING_DONE <= '0';
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mult_enable <= '0';
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mult_b(15 downto 0) <= (others => '0');
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if ADC_READY = '1' then
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state <= CalcPort1;
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end if;
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when CalcPort1 =>
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WINDOWING_DONE <= '0';
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mult_enable <= '1';
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mult_b(15 downto 0) <= PORT1_RAW;
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state <= CalcPort2;
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when CalcPort2 =>
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WINDOWING_DONE <= '0';
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mult_enable <= '1';
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mult_b(15 downto 0) <= PORT2_RAW;
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state <= CalcRef;
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when CalcRef =>
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WINDOWING_DONE <= '0';
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mult_enable <= '1';
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mult_b(15 downto 0) <= REF_RAW;
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state <= MultDelay1;
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when MultDelay1 =>
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WINDOWING_DONE <= '0';
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mult_enable <= '1';
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mult_b(15 downto 0) <= (others => '0');
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state <= MultDelay2;
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when MultDelay2 =>
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WINDOWING_DONE <= '0';
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mult_enable <= '1';
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mult_b(15 downto 0) <= (others => '0');
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state <= StorePort1;
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when StorePort1 =>
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WINDOWING_DONE <= '0';
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mult_enable <= '1';
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mult_b(15 downto 0) <= (others => '0');
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PORT1_WINDOWED <= mult_p(30 downto 13);
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state <= StorePort2;
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when StorePort2 =>
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WINDOWING_DONE <= '0';
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mult_enable <= '1';
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mult_b(15 downto 0) <= (others => '0');
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PORT2_WINDOWED <= mult_p(30 downto 13);
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state <= StoreRef;
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when StoreRef =>
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WINDOWING_DONE <= '1';
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mult_enable <= '0';
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mult_b(15 downto 0) <= (others => '0');
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REF_WINDOWED <= mult_p(30 downto 13);
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-- update window increment
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if window_sample_cnt + window_sample_cnt_inc < window_sample_compare then
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window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc;
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else
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window_sample_cnt <= window_sample_cnt + window_sample_cnt_inc - window_sample_compare;
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window_index <= std_logic_vector( unsigned(window_index) + window_index_inc );
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end if;
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state <= WaitingForADC;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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