279 lines
9.8 KiB
VHDL
279 lines
9.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 21:35:02 05/06/2020
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-- Design Name:
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-- Module Name: Sweep - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Sweep is
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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NPOINTS : in STD_LOGIC_VECTOR (12 downto 0);
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CONFIG_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
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CONFIG_DATA : in STD_LOGIC_VECTOR (95 downto 0);
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USER_NSAMPLES : in STD_LOGIC_VECTOR (12 downto 0);
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NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
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SAMPLING_BUSY : in STD_LOGIC;
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SAMPLING_DONE : in STD_LOGIC;
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START_SAMPLING : out STD_LOGIC;
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BAND_SELECT : out STD_LOGIC;
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-- fixed part of source/LO registers
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MAX2871_DEF_4 : in STD_LOGIC_VECTOR (31 downto 0);
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MAX2871_DEF_3 : in STD_LOGIC_VECTOR (31 downto 0);
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MAX2871_DEF_1 : in STD_LOGIC_VECTOR (31 downto 0);
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MAX2871_DEF_0 : in STD_LOGIC_VECTOR (31 downto 0);
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-- assembled source/LO registers
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SOURCE_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
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SOURCE_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
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SOURCE_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
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SOURCE_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
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LO_REG_4 : out STD_LOGIC_VECTOR (31 downto 0);
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LO_REG_3 : out STD_LOGIC_VECTOR (31 downto 0);
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LO_REG_1 : out STD_LOGIC_VECTOR (31 downto 0);
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LO_REG_0 : out STD_LOGIC_VECTOR (31 downto 0);
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RELOAD_PLL_REGS : out STD_LOGIC;
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PLL_RELOAD_DONE : in STD_LOGIC;
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PLL_LOCKED : in STD_LOGIC;
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SWEEP_HALTED : out STD_LOGIC;
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SWEEP_RESUME : in STD_LOGIC;
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SYNC_ENABLED : in STD_LOGIC;
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SYNC_MASTER : in STD_LOGIC;
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TRIGGER_IN : in STD_LOGIC;
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TRIGGER_OUT : out STD_LOGIC;
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NEW_DATA : out STD_LOGIC;
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ATTENUATOR : out STD_LOGIC_VECTOR(6 downto 0);
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SOURCE_FILTER : out STD_LOGIC_VECTOR(1 downto 0);
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--SETTLING_TIME : in STD_LOGIC_VECTOR (15 downto 0);
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STAGES : in STD_LOGIC_VECTOR (2 downto 0);
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PORT1_STAGE : in STD_LOGIC_VECTOR (2 downto 0);
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PORT2_STAGE : in STD_LOGIC_VECTOR (2 downto 0);
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PORT1_ACTIVE : out STD_LOGIC;
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PORT2_ACTIVE : out STD_LOGIC;
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SOURCE_CE : out STD_LOGIC;
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-- Debug signals
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DEBUG_STATUS : out STD_LOGIC_VECTOR (10 downto 0);
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RESULT_INDEX : out STD_LOGIC_VECTOR (15 downto 0)
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);
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end Sweep;
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architecture Behavioral of Sweep is
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signal point_cnt : unsigned(12 downto 0);
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type Point_states is (WaitInitialLow, TriggerSetup, SettingUp, Settling, WaitTriggerHigh, Exciting, WaitTriggerLow, SamplingDone, NextPoint, Done);
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signal state : Point_states;
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signal settling_cnt : unsigned(15 downto 0);
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signal settling_time : unsigned(15 downto 0);
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signal stage_cnt : unsigned (2 downto 0);
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signal config_reg : std_logic_vector(95 downto 0);
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signal source_active : std_logic;
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begin
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CONFIG_ADDRESS <= std_logic_vector(point_cnt);
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-- assemble registers
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-- source register 0: N divider and fractional division value
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SOURCE_REG_0 <= MAX2871_DEF_0(31) & "0000000000" & config_reg(5 downto 0) & config_reg(26 downto 15) & "000";
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-- source register 1: Modulus value
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SOURCE_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(38 downto 27) & "001";
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-- source register 3: VCO selection
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SOURCE_REG_3 <= config_reg(11 downto 6) & MAX2871_DEF_3(25 downto 3) & "011";
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-- output power A from config, output B disabled
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SOURCE_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(14 downto 12) & MAX2871_DEF_4(19 downto 9) & "000" & MAX2871_DEF_4(5) & config_reg(47 downto 46) & "100";
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-- LO register 0: N divider and fractional division value
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LO_REG_0 <= MAX2871_DEF_0(31) & "0000000000" & config_reg(54 downto 49) & config_reg(75 downto 64) & "000";
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-- LO register 1: Modulus value
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LO_REG_1 <= MAX2871_DEF_1(31 downto 15) & config_reg(87 downto 76) & "001";
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-- LO register 3: VCO selection
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LO_REG_3 <= config_reg(60 downto 55) & MAX2871_DEF_3(25 downto 3) & "011";
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-- both outputs enabled at +5dbm
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LO_REG_4 <= MAX2871_DEF_4(31 downto 23) & config_reg(63 downto 61) & MAX2871_DEF_4(19 downto 9) & "111111100";
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ATTENUATOR <= config_reg(45 downto 39);
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SOURCE_FILTER <= config_reg(89 downto 88);
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BAND_SELECT <= config_reg(48);
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SOURCE_CE <= source_active;
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NSAMPLES <= USER_NSAMPLES when config_reg(92 downto 90) = "000" else
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std_logic_vector(to_unsigned(6, 13)) when config_reg(92 downto 90) = "001" else
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std_logic_vector(to_unsigned(19, 13)) when config_reg(92 downto 90) = "010" else
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std_logic_vector(to_unsigned(57, 13)) when config_reg(92 downto 90) = "011" else
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std_logic_vector(to_unsigned(190, 13)) when config_reg(92 downto 90) = "100" else
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std_logic_vector(to_unsigned(571, 13)) when config_reg(92 downto 90) = "101" else
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std_logic_vector(to_unsigned(1904, 13)) when config_reg(92 downto 90) = "110" else
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std_logic_vector(to_unsigned(5712, 13));
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DEBUG_STATUS(10 downto 7) <= "0000" when state = TriggerSetup else
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"0001" when state = SettingUp else
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"0010" when state = Settling else
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"0011" when state = WaitTriggerHigh else
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"0100" when state = Exciting else
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"0101" when state = WaitTriggerLow else
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"0110" when state = SamplingDone else
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"0111" when state = NextPoint else
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"1000" when state = Done else
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"1001";
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DEBUG_STATUS(6) <= PLL_RELOAD_DONE;
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DEBUG_STATUS(5) <= PLL_RELOAD_DONE and PLL_LOCKED;
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DEBUG_STATUS(4) <= SAMPLING_BUSY;
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DEBUG_STATUS(3) <= TRIGGER_IN;
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DEBUG_STATUS(2) <= source_active;
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DEBUG_STATUS(1 downto 0) <= (others => '1');
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config_reg <= CONFIG_DATA;
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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point_cnt <= (others => '0');
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stage_cnt <= (others => '0');
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state <= WaitInitialLow;
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START_SAMPLING <= '0';
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RELOAD_PLL_REGS <= '0';
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SWEEP_HALTED <= '0';
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RESULT_INDEX <= (others => '1');
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PORT1_ACTIVE <= '0';
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PORT2_ACTIVE <= '0';
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TRIGGER_OUT <= '0';
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source_active <= '0';
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else
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case state is
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when WaitInitialLow =>
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TRIGGER_OUT <= '0';
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if TRIGGER_IN = '0' or SYNC_ENABLED = '0' then
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state <= TriggerSetup;
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end if;
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when TriggerSetup =>
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RELOAD_PLL_REGS <= '1';
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if PLL_RELOAD_DONE = '0' then
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state <= SettingUp;
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end if;
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when SettingUp =>
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-- highest bit in config_reg determines whether the sweep should be halted prior to sampling
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SWEEP_HALTED <= config_reg(95);
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RELOAD_PLL_REGS <= '0';
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case config_reg(94 downto 93) is
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when "00" => settling_time <= to_unsigned(2048, 16); -- 20us
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when "01" => settling_time <= to_unsigned(6144, 16); -- 60us
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when "10" => settling_time <= to_unsigned(18432, 16); -- 180us
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when others => settling_time <= to_unsigned(55296, 16); -- 540us
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end case;
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settling_cnt <= settling_time;
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if PLL_RELOAD_DONE = '1' and PLL_LOCKED = '1' then
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-- check if halted sweep is resumed
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if config_reg(95) = '0' or SWEEP_RESUME = '1' then
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SWEEP_HALTED <= '0';
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state <= Settling;
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end if;
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end if;
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when Settling =>
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NEW_DATA <= '0';
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source_active <= '0';
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if std_logic_vector(stage_cnt) = PORT1_STAGE then
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PORT1_ACTIVE <= '1';
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source_active <= '1';
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else
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PORT1_ACTIVE <= '0';
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end if;
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if std_logic_vector(stage_cnt) = PORT2_STAGE then
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PORT2_ACTIVE <= '1';
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source_active <= '1';
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else
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PORT2_ACTIVE <= '0';
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end if;
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-- wait for settling time to elapse
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if settling_cnt > 0 then
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settling_cnt <= settling_cnt - 1;
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else
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-- need to wait for the trigger
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state <= WaitTriggerHigh;
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if SYNC_MASTER = '1' then
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-- this device generates the stimulus signal, it needs start the trigger itself
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TRIGGER_OUT <= '1';
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end if;
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end if;
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when WaitTriggerHigh =>
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if TRIGGER_IN = '1' or SYNC_ENABLED = '0' then
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TRIGGER_OUT <= SYNC_ENABLED; -- pass on trigger signal if enabled
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START_SAMPLING <= '1';
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if SAMPLING_BUSY = '1' then
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state <= Exciting;
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end if;
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end if;
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when Exciting =>
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-- wait for sampling to finish
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START_SAMPLING <= '0';
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if SAMPLING_BUSY = '0' then
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RESULT_INDEX <= std_logic_vector(stage_cnt) & std_logic_vector(point_cnt);
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state <= WaitTriggerLow;
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end if;
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when WaitTriggerLow =>
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NEW_DATA <= '0';
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if SYNC_MASTER = '1' then
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TRIGGER_OUT <= '0';
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end if;
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if TRIGGER_IN = '0' or SYNC_ENABLED = '0' then
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TRIGGER_OUT <= '0';
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state <= SamplingDone;
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end if;
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when SamplingDone =>
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NEW_DATA <= '1';
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if stage_cnt < unsigned(STAGES) then
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stage_cnt <= stage_cnt + 1;
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-- can go directly to preperation for next stage
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state <= Settling;
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else
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state <= NextPoint;
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end if;
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settling_cnt <= settling_time;
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when NextPoint =>
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NEW_DATA <= '0';
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if point_cnt < unsigned(NPOINTS) then
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point_cnt <= point_cnt + 1;
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stage_cnt <= (others => '0');
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state <= TriggerSetup;
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else
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point_cnt <= (others => '0');
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state <= Done;
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TRIGGER_OUT <= '0';
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end if;
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when others =>
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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