149 lines
3.1 KiB
C++
149 lines
3.1 KiB
C++
#pragma once
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#include <cstdint>
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#include "Flash.hpp"
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#include "max2871.hpp"
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namespace FPGA {
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static constexpr uint16_t MaxPoints = 4501;
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static constexpr uint16_t DFTbins = 96;
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static constexpr uint32_t Clockrate = 102400000UL;
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enum class Reg {
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InterruptMask = 0x00,
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SweepPoints = 0x01,
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SamplesPerPoint = 0x02,
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SystemControl = 0x03,
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ADCPrescaler = 0x04,
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PhaseIncrement = 0x05,
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SweepSetup = 0x06,
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MAX2871Def0LSB = 0x08,
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MAX2871Def0MSB = 0x09,
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MAX2871Def1LSB = 0x0A,
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MAX2871Def1MSB = 0x0B,
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MAX2871Def3LSB = 0x0C,
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MAX2871Def3MSB = 0x0D,
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MAX2871Def4LSB = 0x0E,
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MAX2871Def4MSB = 0x0F,
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DFTFirstBin = 0x12,
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DFTFreqSpacing = 0x13,
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};
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using SamplingResult = struct _samplingresult {
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int64_t P1I, P1Q;
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int64_t P2I, P2Q;
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int64_t RefI, RefQ;
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uint16_t pointNum :13;
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uint16_t stageNum :3;
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};
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using DFTResult = struct _dftresult {
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float P1, P2;
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};
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using ADCLimits = struct _adclimits {
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int16_t P1min, P1max;
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int16_t P2min, P2max;
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int16_t Rmin, Rmax;
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};
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enum class Periphery {
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Port1Mixer = 0x8000,
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Port2Mixer = 0x4000,
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RefMixer = 0x2000,
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Amplifier = 0x1000,
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SourceRF = 0x0800,
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LO1RF = 0x0400,
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ExtRefLED = 0x0200,
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ReadyLED = 0x0100,
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DebugLED = 0x0080,
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SourceChip = 0x0010,
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LO1Chip = 0x0008,
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PortSwitch = 0x0001,
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};
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enum class Interrupt {
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LO1Unlock = 0x0001,
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SourceUnlock = 0x0002,
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NewData = 0x0004,
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DataOverrun = 0x0008,
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SweepHalted = 0x0010,
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DFTReady = 0x0020,
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};
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enum class LowpassFilter {
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M947 = 0x00,
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M1880 = 0x01,
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M3500 = 0x02,
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None = 0x03,
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Auto = 0xFF,
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};
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enum class SettlingTime {
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us20 = 0x00,
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us60 = 0x01,
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us180 = 0x02,
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us540 = 0x03,
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};
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enum class Samples {
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SPPRegister = 0x00,
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S96 = 0x01,
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S304 = 0x02,
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S912 = 0x03,
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S3040 = 0x04,
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S9136 = 0x05,
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S30464 = 0x06,
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S91392 = 0x07,
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};
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enum class Window {
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None = 0x00,
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Kaiser = 0x01,
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Hann = 0x02,
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Flattop = 0x03,
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};
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bool Configure(uint32_t start_address, uint32_t bitstream_size);
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using HaltedCallback = void(*)(void);
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bool Init(HaltedCallback cb = nullptr);
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void WriteRegister(FPGA::Reg reg, uint16_t value);
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void SetNumberOfPoints(uint16_t npoints);
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void SetSamplesPerPoint(uint32_t nsamples);
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void SetupSweep(uint8_t stages, uint8_t port1_stage, uint8_t port2_stage, bool individual_halt = false);
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void Enable(Periphery p, bool enable = true);
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void Disable(Periphery p);
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bool IsEnabled(Periphery p);
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void SetWindow(Window w);
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void EnableInterrupt(Interrupt i);
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void DisableInterrupt(Interrupt i);
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void WriteMAX2871Default(uint32_t *DefaultRegs);
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void WriteSweepConfig(uint16_t pointnum, bool lowband, uint32_t *SourceRegs, uint32_t *LORegs,
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uint8_t attenuation, uint64_t frequency, SettlingTime settling, Samples samples, bool halt = false, LowpassFilter filter = LowpassFilter::Auto);
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using ReadCallback = void(*)(const SamplingResult &result);
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bool InitiateSampleRead(ReadCallback cb);
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void SetupDFT(uint32_t f_firstBin, uint32_t f_binSpacing);
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void StopDFT();
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void StartDFT();
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DFTResult ReadDFTResult();
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ADCLimits GetADCLimits();
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void ResetADCLimits();
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void ResumeHaltedSweep();
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uint16_t GetStatus();
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void StartSweep();
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void AbortSweep();
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enum class Mode {
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FPGA,
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SourcePLL,
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LOPLL,
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};
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void SetMode(Mode mode);
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}
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