247 lines
6.2 KiB
VHDL
247 lines
6.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:27:54 05/05/2020
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-- Design Name:
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-- Module Name: Sampling - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Sampling is
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Generic(CLK_DIV : integer;
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CLK_FREQ : integer;
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IF_FREQ : integer;
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CLK_CYCLES_PRE_DONE : integer);
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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PORT1 : in STD_LOGIC_VECTOR (15 downto 0);
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PORT2 : in STD_LOGIC_VECTOR (15 downto 0);
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REF : in STD_LOGIC_VECTOR (15 downto 0);
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ADC_START : out STD_LOGIC;
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NEW_SAMPLE : in STD_LOGIC;
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DONE : out STD_LOGIC;
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PRE_DONE : out STD_LOGIC;
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START : in STD_LOGIC;
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SAMPLES : in STD_LOGIC_VECTOR (16 downto 0);
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PORT1_I : out STD_LOGIC_VECTOR (47 downto 0);
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PORT1_Q : out STD_LOGIC_VECTOR (47 downto 0);
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PORT2_I : out STD_LOGIC_VECTOR (47 downto 0);
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PORT2_Q : out STD_LOGIC_VECTOR (47 downto 0);
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REF_I : out STD_LOGIC_VECTOR (47 downto 0);
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REF_Q : out STD_LOGIC_VECTOR (47 downto 0);
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ACTIVE : out STD_LOGIC);
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end Sampling;
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architecture Behavioral of Sampling is
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COMPONENT SinCos
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PORT (
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clk : IN STD_LOGIC;
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phase_in : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
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cosine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
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sine : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
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);
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END COMPONENT;
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COMPONENT SinCosMult
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PORT (
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clk : IN STD_LOGIC;
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a : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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b : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
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p : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
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);
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END COMPONENT;
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signal p1_I : signed(47 downto 0);
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signal p1_Q : signed(47 downto 0);
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signal p2_I : signed(47 downto 0);
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signal p2_Q : signed(47 downto 0);
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signal r_I : signed(47 downto 0);
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signal r_Q : signed(47 downto 0);
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signal clk_cnt : integer range 0 to CLK_DIV - 1;
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signal sample_cnt : integer range 0 to 131071;
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constant phase_inc : integer := IF_FREQ * 4096 * CLK_DIV / CLK_FREQ;
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signal phase : std_logic_vector(11 downto 0);
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signal sine : std_logic_vector(15 downto 0);
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signal cosine : std_logic_vector(15 downto 0);
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signal mult1_I : std_logic_vector(31 downto 0);
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signal mult1_Q : std_logic_vector(31 downto 0);
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signal mult2_I : std_logic_vector(31 downto 0);
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signal mult2_Q : std_logic_vector(31 downto 0);
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signal multR_I : std_logic_vector(31 downto 0);
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signal multR_Q : std_logic_vector(31 downto 0);
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type States is (Idle, Sampling, WaitForMult, Accumulating, Ready);
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signal state : States;
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begin
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-- Always fails for simulation, comment out
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-- assert (phase_inc * CLK_FREQ / (4096*CLK_DIV) = IF_FREQ)
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-- report "Phase increment not exact"
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-- severity FAILURE;
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LookupTable : SinCos
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PORT MAP (
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clk => CLK,
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phase_in => phase,
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cosine => cosine,
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sine => sine
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);
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Port1_I_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => PORT1,
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b => cosine,
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p => mult1_I
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);
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Port1_Q_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => PORT1,
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b => sine,
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p => mult1_Q
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);
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Port2_I_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => PORT2,
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b => cosine,
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p => mult2_I
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);
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Port2_Q_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => PORT2,
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b => sine,
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p => mult2_Q
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);
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Ref_I_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => REF,
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b => cosine,
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p => multR_I
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);
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Ref_Q_Mult : SinCosMult
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PORT MAP (
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clk => CLK,
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a => REF,
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b => sine,
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p => multR_Q
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);
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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state <= Idle;
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ADC_START <= '0';
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DONE <= '0';
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PRE_DONE <= '0';
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ACTIVE <= '0';
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clk_cnt <= 0;
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sample_cnt <= 0;
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phase <= (others => '0');
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else
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-- when not idle, generate pulses for ADCs
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if state /= Idle then
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if clk_cnt = CLK_DIV - 1 then
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ADC_START <= '1';
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clk_cnt <= 0;
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else
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clk_cnt <= clk_cnt + 1;
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ADC_START <= '0';
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end if;
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else
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ADC_START <= '0';
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end if;
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-- handle state transitions
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case state is
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when Idle =>
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sample_cnt <= 0;
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DONE <= '0';
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PRE_DONE <= '0';
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ACTIVE <= '0';
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clk_cnt <= 0;
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phase <= (others => '0');
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p1_I <= (others => '0');
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p1_Q <= (others => '0');
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p2_I <= (others => '0');
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p2_Q <= (others => '0');
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r_I <= (others => '0');
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r_Q <= (others => '0');
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phase <= (others => '0');
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if START = '1' then
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state <= Sampling;
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end if;
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when Sampling =>
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DONE <= '0';
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PRE_DONE <= '0';
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ACTIVE <= '1';
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if NEW_SAMPLE = '1' then
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state <= WaitForMult;
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end if;
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when WaitForMult =>
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DONE <= '0';
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PRE_DONE <= '0';
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ACTIVE <= '1';
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state <= Accumulating;
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when Accumulating =>
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-- multipliers are finished with the sample
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p1_I <= p1_I + signed(mult1_I);
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p1_Q <= p1_Q + signed(mult1_Q);
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p2_I <= p2_I + signed(mult2_I);
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p2_Q <= p2_Q + signed(mult2_Q);
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r_I <= r_I + signed(multR_I);
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r_Q <= r_Q + signed(multR_Q);
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-- advance phase
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ACTIVE <= '1';
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DONE <= '0';
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PRE_DONE <= '0';
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phase <= std_logic_vector(unsigned(phase) + phase_inc);
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if sample_cnt < unsigned(SAMPLES) then
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sample_cnt <= sample_cnt + 1;
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state <= Sampling;
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else
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state <= Ready;
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end if;
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when Ready =>
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ACTIVE <= '1';
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DONE <= '1';
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PRE_DONE <= '1';
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PORT1_I <= std_logic_vector(p1_I);
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PORT1_Q <= std_logic_vector(p1_Q);
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PORT2_I <= std_logic_vector(p2_I);
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PORT2_Q <= std_logic_vector(p2_Q);
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REF_I <= std_logic_vector(r_I);
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REF_Q <= std_logic_vector(r_Q);
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state <= Idle;
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end case;
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end if;
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end if;
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end process;
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end Behavioral;
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