LibreVNA/FPGA/VNA
2020-09-17 15:51:20 +02:00
..
MAX2871.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
MCP33131.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
ResetDelay.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Sampling.vhd proof-of-concept spectrum analyzer mode 2020-09-17 15:51:20 +02:00
spi_slave.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
SPIConfig.vhd different settling time/samples per point in sweep 2020-09-14 11:03:37 +02:00
Sweep.vhd Experimental feature: only excite one port when other traces are paused 2020-09-15 23:22:08 +02:00
Synchronizer.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Test_MAX2871.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Test_MCP33131.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Test_PLL.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Test_Sampling.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Test_SinCos.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Test_SPI.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Test_SPICommands.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Test_Sync.vhd FPGA project adapted to new pinout 2020-08-30 16:19:18 +02:00
Test_Window.vhd Windowing option added to sampling 2020-09-16 16:13:06 +02:00
top.ucf Bugfixes and improvements for new hardware 2020-09-14 23:13:32 +02:00
top.vhd Windowing option added to sampling 2020-09-16 16:13:06 +02:00
VNA.gise proof-of-concept spectrum analyzer mode 2020-09-17 15:51:20 +02:00
VNA.xise Windowing option added to sampling 2020-09-16 16:13:06 +02:00
window.vhd Windowing option added to sampling 2020-09-16 16:13:06 +02:00