379 lines
24 KiB
XML
379 lines
24 KiB
XML
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
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<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
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<!-- -->
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<!-- For tool use only. Do not edit. -->
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<!-- -->
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<!-- ProjectNavigator created generated project file. -->
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<!-- For use in tracking generated file and other information -->
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<!-- allowing preservation of process status. -->
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<!-- -->
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<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
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<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
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<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="VNA.xise"/>
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<files xmlns="http://www.xilinx.com/XMLSchema">
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="DFT.vhi"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MAX2871.vhi"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="MCP33131.vhi"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="ResetDelay.vhi"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="SPICommands.vhi"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="SPICommands_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="Sampling.cmd_log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="Sampling.lso"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Sampling.prj"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="Sampling.syr"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Sampling.vhi"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="Sampling.xst"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="Sampling_envsettings.html"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="Sampling_summary.html"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="Sampling_xst.xrpt"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Sweep.vhi"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Synchronizer.vhi"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_DFT_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MAX2871_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_MCP33131_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_PLL_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPICommands_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SPI_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sampling_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_SinCos_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Sync_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Sync_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="Test_Sync_isim_beh.wdb"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Window_isim_beh.exe"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_Windowing_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="Test_Windowing_stx_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="Test_top_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="Windowing.vhi"/>
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<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
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<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="dft_result.vhi"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
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<file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_3"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_4"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="spi_slave.vhi"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:fileType="FILE_BIN" xil_pn:name="top.bin"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="top.bit" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="top.bld"/>
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<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="top.cmd_log"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="top.drc" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="top.lso"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top.ncd" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="top.ngc"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="top.ngd"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="top.ngr"/>
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<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="top.pad"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="top.par" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="top.pcf" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="top.prj"/>
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<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="top.ptwx"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="top.stx"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="top.syr"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="top.twr" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="top.twx" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="top.unroutes" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top.ut" xil_pn:subbranch="FPGAConfiguration"/>
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<file xil_pn:fileType="FILE_XPI" xil_pn:name="top.xpi"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="top.xst"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_envsettings.html"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="top_fpga_editor.log"/>
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<file xil_pn:fileType="FILE_NCD" xil_pn:name="top_guide.ncd" xil_pn:origination="imported"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="top_isim_beh.exe"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.map" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.mrp" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_map.ncd" xil_pn:subbranch="Map"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="top_map.ngm" xil_pn:subbranch="Map"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_map.xrpt"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_ngdbuild.xrpt"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="top_pad.csv" xil_pn:subbranch="Par"/>
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<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="top_pad.txt" xil_pn:subbranch="Par"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_par.xrpt"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_summary.html"/>
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<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="top_summary.xml"/>
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<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="top_usage.xml"/>
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<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_xst.xrpt"/>
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<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
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<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
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<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
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<file xil_pn:fileType="FILE_VHDL_INSTTEMPLATE" xil_pn:name="window.vhi"/>
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<file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="window_beh.prj"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="window_isim_beh.exe"/>
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<file xil_pn:fileType="FILE_ISIM_MISC" xil_pn:name="window_isim_beh.wdb"/>
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<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_INI" xil_pn:name="xilinxsim.ini"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
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<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
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<status xil_pn:value="InputChanged"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="DFT.vhd"/>
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<outfile xil_pn:name="MAX2871.vhd"/>
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<outfile xil_pn:name="MCP33131.vhd"/>
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<outfile xil_pn:name="ResetDelay.vhd"/>
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<outfile xil_pn:name="SPIConfig.vhd"/>
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<outfile xil_pn:name="Test_MCP33131.vhd"/>
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<outfile xil_pn:name="Test_SPICommands.vhd"/>
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<outfile xil_pn:name="Test_Sampling.vhd"/>
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<outfile xil_pn:name="Test_SinCos.vhd"/>
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<outfile xil_pn:name="Test_Window.vhd"/>
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<outfile xil_pn:name="Test_Windowing.vhd"/>
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<outfile xil_pn:name="Windowing.vhd"/>
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<outfile xil_pn:name="spi_slave.vhd"/>
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<transform xil_pn:end_ts="1604763670" xil_pn:in_ck="6306144844996157057" xil_pn:name="TRAN_regenerateCoresSim" xil_pn:prop_ck="-2723611991789822717" xil_pn:start_ts="1604763670">
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<outfile xil_pn:name="ipcore_dir/PLL.vhd"/>
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</transform>
|
|
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1600270761">
|
|
<status xil_pn:value="SuccessfullyRun"/>
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|
<status xil_pn:value="ReadyToRun"/>
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|
</transform>
|
|
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-9042377951913232490" xil_pn:start_ts="1600270761">
|
|
<status xil_pn:value="SuccessfullyRun"/>
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|
<status xil_pn:value="ReadyToRun"/>
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|
</transform>
|
|
<transform xil_pn:end_ts="1600270761" xil_pn:in_ck="277585929807082169" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1600270761">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1600270761" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="6527189854873920525" xil_pn:start_ts="1600270761">
|
|
<status xil_pn:value="SuccessfullyRun"/>
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|
<status xil_pn:value="ReadyToRun"/>
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|
</transform>
|
|
<transform xil_pn:end_ts="1661101072" xil_pn:in_ck="2241500006820465658" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="3256065936432453276" xil_pn:start_ts="1661101063">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="WarningsGenerated"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="OutputChanged"/>
|
|
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
|
<outfile xil_pn:name="top.lso"/>
|
|
<outfile xil_pn:name="top.ngc"/>
|
|
<outfile xil_pn:name="top.ngr"/>
|
|
<outfile xil_pn:name="top.prj"/>
|
|
<outfile xil_pn:name="top.stx"/>
|
|
<outfile xil_pn:name="top.syr"/>
|
|
<outfile xil_pn:name="top.xst"/>
|
|
<outfile xil_pn:name="top_xst.xrpt"/>
|
|
<outfile xil_pn:name="webtalk_pn.xml"/>
|
|
<outfile xil_pn:name="xst"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1659800190" xil_pn:in_ck="934418963425178690" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="6693835875156060939" xil_pn:start_ts="1659800190">
|
|
<status xil_pn:value="SuccessfullyRun"/>
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|
<status xil_pn:value="ReadyToRun"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1661101076" xil_pn:in_ck="5411862124762956458" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="4604875190571501774" xil_pn:start_ts="1661101072">
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|
<status xil_pn:value="SuccessfullyRun"/>
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|
<status xil_pn:value="ReadyToRun"/>
|
|
<outfile xil_pn:name="_ngo"/>
|
|
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
|
<outfile xil_pn:name="top.bld"/>
|
|
<outfile xil_pn:name="top.ngd"/>
|
|
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1661101188" xil_pn:in_ck="8512332261572065657" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-4668962392366239264" xil_pn:start_ts="1661101076">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="WarningsGenerated"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
|
<outfile xil_pn:name="top.pcf"/>
|
|
<outfile xil_pn:name="top_map.map"/>
|
|
<outfile xil_pn:name="top_map.mrp"/>
|
|
<outfile xil_pn:name="top_map.ncd"/>
|
|
<outfile xil_pn:name="top_map.ngm"/>
|
|
<outfile xil_pn:name="top_map.xrpt"/>
|
|
<outfile xil_pn:name="top_summary.xml"/>
|
|
<outfile xil_pn:name="top_usage.xml"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1661101201" xil_pn:in_ck="1117507038335044978" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1085068593928086116" xil_pn:start_ts="1661101188">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
|
<outfile xil_pn:name="top.ncd"/>
|
|
<outfile xil_pn:name="top.pad"/>
|
|
<outfile xil_pn:name="top.par"/>
|
|
<outfile xil_pn:name="top.ptwx"/>
|
|
<outfile xil_pn:name="top.unroutes"/>
|
|
<outfile xil_pn:name="top.xpi"/>
|
|
<outfile xil_pn:name="top_pad.csv"/>
|
|
<outfile xil_pn:name="top_pad.txt"/>
|
|
<outfile xil_pn:name="top_par.xrpt"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1661101208" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="3274353840855015246" xil_pn:start_ts="1661101201">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="WarningsGenerated"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
|
<outfile xil_pn:name="top.bgn"/>
|
|
<outfile xil_pn:name="top.bin"/>
|
|
<outfile xil_pn:name="top.bit"/>
|
|
<outfile xil_pn:name="top.drc"/>
|
|
<outfile xil_pn:name="top.ut"/>
|
|
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
|
|
<outfile xil_pn:name="webtalk.log"/>
|
|
<outfile xil_pn:name="webtalk_pn.xml"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1591357065" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="-2382555676865099342" xil_pn:start_ts="1591357065">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="InputAdded"/>
|
|
<status xil_pn:value="InputChanged"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
<status xil_pn:value="OutputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1591357024" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="-8856759851099153863" xil_pn:start_ts="1591357024">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="InputAdded"/>
|
|
<status xil_pn:value="InputChanged"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
<status xil_pn:value="OutputChanged"/>
|
|
<status xil_pn:value="OutputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1591357058" xil_pn:in_ck="154288899584" xil_pn:name="TRAN_genImpactFile" xil_pn:prop_ck="7381105705363676227" xil_pn:start_ts="1591357058">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="OutOfDateForOutputs"/>
|
|
<status xil_pn:value="InputAdded"/>
|
|
<status xil_pn:value="InputChanged"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
<status xil_pn:value="OutputChanged"/>
|
|
<status xil_pn:value="OutputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1604431776" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_fpgaFloorplanPostPAR" xil_pn:start_ts="1604431776">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<status xil_pn:value="OutOfDateForInputs"/>
|
|
<status xil_pn:value="InputAdded"/>
|
|
<status xil_pn:value="InputChanged"/>
|
|
<status xil_pn:value="InputRemoved"/>
|
|
</transform>
|
|
<transform xil_pn:end_ts="1661101201" xil_pn:in_ck="8512326635937592693" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1661101197">
|
|
<status xil_pn:value="SuccessfullyRun"/>
|
|
<status xil_pn:value="ReadyToRun"/>
|
|
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
|
<outfile xil_pn:name="top.twr"/>
|
|
<outfile xil_pn:name="top.twx"/>
|
|
</transform>
|
|
</transforms>
|
|
|
|
</generated_project>
|