284 lines
9.8 KiB
VHDL
284 lines
9.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 19:51:11 05/05/2020
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-- Design Name:
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-- Module Name: SPICommands - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity SPICommands is
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Port ( CLK : in STD_LOGIC;
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RESET : in STD_LOGIC;
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SCLK : in STD_LOGIC;
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MOSI : in STD_LOGIC;
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MISO : out STD_LOGIC;
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NSS : in STD_LOGIC;
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NEW_SAMPLING_DATA : in STD_LOGIC;
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SAMPLING_RESULT : in STD_LOGIC_VECTOR (303 downto 0);
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ADC_MINMAX : in STD_LOGIC_VECTOR(95 downto 0);
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SOURCE_UNLOCKED : in STD_LOGIC;
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LO_UNLOCKED : in STD_LOGIC;
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MAX2871_DEF_4 : out STD_LOGIC_VECTOR (31 downto 0);
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MAX2871_DEF_3 : out STD_LOGIC_VECTOR (31 downto 0);
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MAX2871_DEF_1 : out STD_LOGIC_VECTOR (31 downto 0);
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MAX2871_DEF_0 : out STD_LOGIC_VECTOR (31 downto 0);
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SWEEP_DATA : out STD_LOGIC_VECTOR (95 downto 0);
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SWEEP_ADDRESS : out STD_LOGIC_VECTOR (12 downto 0);
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SWEEP_WRITE : out STD_LOGIC_VECTOR (0 downto 0);
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SWEEP_POINTS : out STD_LOGIC_VECTOR (12 downto 0);
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NSAMPLES : out STD_LOGIC_VECTOR (12 downto 0);
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EXCITE_PORT1 : out STD_LOGIC;
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EXCITE_PORT2 : out STD_LOGIC;
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PORT1_EN : out STD_LOGIC;
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PORT2_EN : out STD_LOGIC;
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REF_EN : out STD_LOGIC;
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AMP_SHDN : out STD_LOGIC;
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SOURCE_RF_EN : out STD_LOGIC;
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LO_RF_EN : out STD_LOGIC;
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SOURCE_CE_EN : out STD_LOGIC;
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LO_CE_EN : out STD_LOGIC;
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PORTSWITCH_EN : out STD_LOGIC;
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LEDS : out STD_LOGIC_VECTOR(2 downto 0);
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WINDOW_SETTING : out STD_LOGIC_VECTOR(1 downto 0);
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ADC_PRESCALER : out STD_LOGIC_VECTOR(7 downto 0);
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ADC_PHASEINC : out STD_LOGIC_VECTOR(11 downto 0);
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INTERRUPT_ASSERTED : out STD_LOGIC;
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RESET_MINMAX : out STD_LOGIC;
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SWEEP_HALTED : in STD_LOGIC;
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SWEEP_RESUME : out STD_LOGIC;
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-- DFT signals
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DFT_BIN1_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
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DFT_DIFFBIN_PHASEINC : out STD_LOGIC_VECTOR (15 downto 0);
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DFT_RESULT_READY : in STD_LOGIC;
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DFT_OUTPUT : in STD_LOGIC_VECTOR (191 downto 0);
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DFT_NEXT_OUTPUT : out STD_LOGIC;
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DFT_ENABLE : out STD_LOGIC;
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DEBUG_STATUS : in STD_LOGIC_VECTOR(10 downto 0));
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end SPICommands;
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architecture Behavioral of SPICommands is
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COMPONENT spi_slave
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Generic(W : integer);
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PORT(
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SPI_CLK : in STD_LOGIC;
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MISO : out STD_LOGIC;
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MOSI : in STD_LOGIC;
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CS : in STD_LOGIC;
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BUF_OUT : out STD_LOGIC_VECTOR (W-1 downto 0) := (others => '0');
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BUF_IN : in STD_LOGIC_VECTOR (W-1 downto 0);
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CLK : in STD_LOGIC;
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COMPLETE : out STD_LOGIC
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);
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END COMPONENT;
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-- SPI control signals
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signal spi_buf_out : std_logic_vector(15 downto 0);
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signal spi_buf_in : std_logic_vector(15 downto 0);
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signal spi_complete : std_logic;
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signal word_cnt : integer range 0 to 19;
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type SPI_states is (FirstWord, WriteSweepConfig, ReadResult, WriteRegister);
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signal state : SPI_states;
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signal selected_register : integer range 0 to 31;
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signal dft_next : std_logic;
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signal last_NSS : std_logic;
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signal sweep_config_write : std_logic;
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signal unread_sampling_data : std_logic;
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signal data_overrun : std_logic;
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-- Configuration registers
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signal interrupt_mask : std_logic_vector(15 downto 0);
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signal interrupt_status : std_logic_vector(15 downto 0);
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signal latched_result : std_logic_vector(287 downto 0);
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signal sweepconfig_buffer : std_logic_vector(79 downto 0);
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begin
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SPI: spi_slave
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GENERIC MAP(w => 16)
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PORT MAP(
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SPI_CLK => SCLK,
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MISO => MISO,
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MOSI => MOSI,
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CS => NSS,
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BUF_OUT => spi_buf_out,
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BUF_IN => spi_buf_in,
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CLK => CLK,
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COMPLETE =>spi_complete
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);
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SWEEP_WRITE(0) <= sweep_config_write;
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DFT_NEXT_OUTPUT <= dft_next;
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DFT_ENABLE <= interrupt_mask(5);
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process(CLK, RESET)
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begin
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if rising_edge(CLK) then
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if RESET = '1' then
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sweep_config_write <= '0';
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data_overrun <= '0';
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SWEEP_POINTS <= (others => '0');
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NSAMPLES <= (others => '0');
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--SETTLING_TIME <= (others => '0');
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PORT1_EN <= '0';
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PORT2_EN <= '0';
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REF_EN <= '0';
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AMP_SHDN <= '1';
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SOURCE_RF_EN <= '0';
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LO_RF_EN <= '0';
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SOURCE_CE_EN <= '0';
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LO_CE_EN <= '0';
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PORTSWITCH_EN <= '0';
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EXCITE_PORT1 <= '0';
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EXCITE_PORT2 <= '0';
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LEDS <= (others => '1');
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WINDOW_SETTING <= "00";
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unread_sampling_data <= '0';
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interrupt_mask <= (others => '0');
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ADC_PRESCALER <= std_logic_vector(to_unsigned(112, 8));
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ADC_PHASEINC <= std_logic_vector(to_unsigned(1120, 12));
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RESET_MINMAX <= '0';
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INTERRUPT_ASSERTED <= '0';
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latched_result <= (others => '0');
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DFT_BIN1_PHASEINC <= (others => '0');
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DFT_DIFFBIN_PHASEINC <= (others => '0');
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dft_next <= '0';
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last_NSS <= '1';
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else
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interrupt_status <= DEBUG_STATUS(10 downto 1) & DFT_RESULT_READY & SWEEP_HALTED & data_overrun & unread_sampling_data & SOURCE_UNLOCKED & LO_UNLOCKED;
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if (interrupt_status and interrupt_mask) = "0000000000000000" then
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INTERRUPT_ASSERTED <= '0';
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else
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INTERRUPT_ASSERTED <= '1';
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end if;
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if sweep_config_write = '1' then
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sweep_config_write <= '0';
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end if;
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if dft_next = '1' then
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dft_next <= '0';
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end if;
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RESET_MINMAX <= '0';
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SWEEP_RESUME <= '0';
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if NEW_SAMPLING_DATA = '1' then
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unread_sampling_data <= '1';
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if unread_sampling_data = '1' then
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data_overrun <= '1';
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end if;
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end if;
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last_NSS <= NSS;
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if NSS = '0' and last_NSS = '1' then
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word_cnt <= 0;
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spi_buf_in <= interrupt_status;
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state <= FirstWord;
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elsif spi_complete = '1' then
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word_cnt <= word_cnt + 1;
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case state is
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when FirstWord =>
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-- initial word determines action
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case spi_buf_out(15 downto 13) is
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when "000" => state <= WriteSweepConfig;
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-- also extract the point number
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SWEEP_ADDRESS <= spi_buf_out(12 downto 0);
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when "001" => state <= FirstWord;
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SWEEP_RESUME <= '1';
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when "010" => state <= FirstWord;
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spi_buf_in <= "1111000010100101";
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when "011" => state <= FirstWord;
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RESET_MINMAX <= '1';
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when "100" => state <= WriteRegister;
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selected_register <= to_integer(unsigned(spi_buf_out(4 downto 0)));
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when "101" => state <= ReadResult;-- can use same state as read result, but the latched data will contain the DFT values
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latched_result(175 downto 0) <= DFT_OUTPUT(191 downto 16);
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spi_buf_in <= DFT_OUTPUT(15 downto 0);
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dft_next <= '1';
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when "110" => state <= ReadResult;
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latched_result <= SAMPLING_RESULT(303 downto 16);
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spi_buf_in <= SAMPLING_RESULT(15 downto 0);
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unread_sampling_data <= '0';
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when "111" => state <= ReadResult; -- can use same state as read result, but the latched data will contain the min/max ADC values
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latched_result(79 downto 0) <= ADC_MINMAX(95 downto 16);
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spi_buf_in <= ADC_MINMAX(15 downto 0);
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when others => state <= FirstWord;
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end case;
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when WriteRegister =>
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-- write received data into previously selected register
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case selected_register is
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when 0 => interrupt_mask <= spi_buf_out;
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when 1 => SWEEP_POINTS <= spi_buf_out(12 downto 0);
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when 2 => NSAMPLES <= spi_buf_out(12 downto 0);
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when 3 => PORTSWITCH_EN <= spi_buf_out(0);
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PORT1_EN <= spi_buf_out(15);
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PORT2_EN <= spi_buf_out(14);
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REF_EN <= spi_buf_out(13);
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AMP_SHDN <= not spi_buf_out(12);
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SOURCE_RF_EN <= spi_buf_out(11);
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LO_RF_EN <= spi_buf_out(10);
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LEDS <= not spi_buf_out(9 downto 7);
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WINDOW_SETTING <= spi_buf_out(6 downto 5);
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SOURCE_CE_EN <= spi_buf_out(4);
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LO_CE_EN <= spi_buf_out(3);
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EXCITE_PORT1 <= spi_buf_out(1);
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EXCITE_PORT2 <= spi_buf_out(2);
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when 4 => ADC_PRESCALER <= spi_buf_out(7 downto 0);
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when 5 => ADC_PHASEINC <= spi_buf_out(11 downto 0);
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when 8 => MAX2871_DEF_0(15 downto 0) <= spi_buf_out;
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when 9 => MAX2871_DEF_0(31 downto 16) <= spi_buf_out;
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when 10 => MAX2871_DEF_1(15 downto 0) <= spi_buf_out;
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when 11 => MAX2871_DEF_1(31 downto 16) <= spi_buf_out;
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when 12 => MAX2871_DEF_3(15 downto 0) <= spi_buf_out;
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when 13 => MAX2871_DEF_3(31 downto 16) <= spi_buf_out;
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when 14 => MAX2871_DEF_4(15 downto 0) <= spi_buf_out;
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when 15 => MAX2871_DEF_4(31 downto 16) <= spi_buf_out;
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when 18 => DFT_BIN1_PHASEINC <= spi_buf_out;
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when 19 => DFT_DIFFBIN_PHASEINC <= spi_buf_out;
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when others =>
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end case;
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selected_register <= selected_register + 1;
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when WriteSweepConfig =>
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if word_cnt = 6 then
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-- Sweep config data is complete pass on
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SWEEP_DATA <= sweepconfig_buffer & spi_buf_out;
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sweep_config_write <= '1';
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else
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-- shift next word into buffer
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sweepconfig_buffer <= sweepconfig_buffer(63 downto 0) & spi_buf_out;
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end if;
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when ReadResult =>
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-- pass on next word of latched result
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spi_buf_in <= latched_result(15 downto 0);
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latched_result <= "0000000000000000" & latched_result(287 downto 16);
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end case;
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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